CN1670955A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN1670955A
CN1670955A CNA2005100548106A CN200510054810A CN1670955A CN 1670955 A CN1670955 A CN 1670955A CN A2005100548106 A CNA2005100548106 A CN A2005100548106A CN 200510054810 A CN200510054810 A CN 200510054810A CN 1670955 A CN1670955 A CN 1670955A
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semiconductor
substrate
chip
logic chip
semiconductor device
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Granted
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CNA2005100548106A
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CN100481446C (zh
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川野连也
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Renesas Electronics Corp
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NEC Corp
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    • H01L2924/19041—Component type being a capacitor

Abstract

一种半导体器件，该半导体器件以利用凸点键合将逻辑芯片的焊盘部分连接到半导体芯片的元件区的这种方法构成，因为电信号的传输延迟被抑制，所以该半导体器件能够实现元件的高速操作性能。逻辑芯片直接连接到DRAM，因此，可以抑制由互连引起的负载电容的增加，以及通过多管脚连接保证宽的总线宽度。结果，在抑制从逻辑芯片至DRAM的信息传输延迟时，可以增强半导体器件的性能。

Description

半导体器件
本申请基于日本专利申请号2004-081743，在此将其内容引入作为参考。
技术领域
本发明涉及形成有层叠的半导体芯片的半导体器件。
背景技术
近年来，需要轻质，薄，以及小尺寸和高性能的半导体器件。在如多芯片封装等的半导体器件中，实现高密度互连，积极地促进了逻辑芯片的微型化和存储器的容量增加。
作为处理这种要求的相应方法，试图在半导体衬底上提供穿通电极时获得实现高密度互连等。日本特许专利公开号2000-12618公开了这种技术。如图10所示，日本特许专利公开号2000-12618公开了一种技术，在使用从半导体衬底12的后表面穿过半导体衬底12的电极15的同时，通过端子16和端子18使封装衬底17与缓冲电路连接，半导体衬底12上集成了通过端子13和端子14连接到半导体衬底11的缓冲电路。
发明内容
在形成层叠的系统芯片的封装中，优选通过凸点而不是引线键合连接元件。通过凸点连接元件，提高了元件的高速操作性能。具体地，在包括如需要高速操作的逻辑芯片的元件的封装中，希望元件之间通过凸点键合直接连接。此外，近年来，有逻辑芯片的尺寸变得越来越小，而存储元件的容量增加和其尺寸增加的趋势。为此，在依次形成小逻辑芯片和比逻辑芯片更大尺寸的存储元件的层叠的结构中，使用引线键合等不能将逻辑芯片的输入/输出引到外部。因此，在执行逻辑芯片和其他元件之间的凸点键合的结构中，有必要设置将衬底的后表面侧与衬底的前表面侧连接的穿通电极。
但是，现在发现相关技术中描述的结构的穿通电极是从元件的后表面跨过前表面而形成的，因此存在元件的有效使用区被减小的问题。也就是说，在形成穿通电极的区域中不可能提供互连等，因此元件的有效使用区域被减小，以致互连等的集成度恶化。在强烈地需要实现高密度互连的逻辑芯片的情况下，上述问题变得更为严重。
根据本发明，一种半导体器件包括：在第一半导体芯片的主表面上具有第一焊盘的第一半导体芯片，作为逻辑芯片的第二半导体芯片，第二半导体芯片具有半导体衬底，设置在半导体衬底的前表面上的多级互连层，穿透半导体衬底连接到设置在多级互连层内的导电元件的穿通电极以及贴装在多级互连层的顶部上的第二焊盘，其中第一半导体芯片和第二半导体芯片通过第一焊盘和第二焊盘互相倒装芯片连接。
根据本发明，第二半导体芯片通过第一焊盘和第二焊盘连接到第一半导体芯片，以及采用在逻辑芯片中设置穿通电极以实现元件的高速操作性能的结构。另一方面，采用了穿通电极连接到多级互连层内设置的导电元件的结构，因此可以有效地利用穿通电极的上部区域，以便与相关技术相比较可以提高互连密度。
根据本发明，第二半导体芯片的焊盘部分通过第一焊盘和第二焊盘连接到第一半导体芯片的元件区，因此因为电信号的传送延迟被抑制，所以可以实现元件的高速操作性能。
附图说明
从下面结合附图的说明将使本发明的上述及其他目的、优点和特点更为明显，其中：
图1是用于解释根据实施例的半导体器件结构的剖面图；
图2是用于解释根据实施例的半导体器件结构的剖面图；
图3是用于解释根据实施例的半导体器件结构的剖面图；
图4是用于解释根据实施例的半导体器件结构的剖面图；
图5是用于解释根据实施例的半导体器件结构的剖面图；
图6是用于解释根据实施例的半导体器件结构的剖面图；
图7是用于解释根据实施例的半导体器件结构的剖面图；
图8是用于解释根据实施例的半导体器件结构的剖面图；
图9是用于解释根据实施例的半导体器件结构的剖面图；以及
图10是用于解释常规半导体器件结构的剖面图。
具体实施方式
现在将参考说明性实施例在此描述本发明。本领域的技术人员将认识到使用本发明的讲解可以完成许多选择性实施例，以及发明不局限于用于解释性目的而说明的实施例。
下面，参考附图描述本发明的实施例。在整个附图中，相同的标记附于相同的元件，且在以下说明中将适当地省略详细的描述。
图1所示的半导体器件具有第一半导体芯片(DRAM 140)和第二半导体芯片(逻辑芯片200)，第一半导体芯片(DRAM 140)具有在DRAM 140的主表面上的第一焊盘(凸点142)。
在本发明中，第二半导体芯片可以具有缓冲器单元，该缓冲器单元具有输入缓冲器电路和输出缓冲器电路，以及在缓冲器单元中可以设置导电元件，而第二半导体芯片可以具有转换器电路单元，转换器电路单元具有输入电压转换器电路和输出电压转换器电路，以及在转换器电路单元中可以设置导电元件。
在本发明中，第一半导体芯片可以是存储器，以及进一步该存储器可以是DRAM或快闪存储器。
第一实施例
图1示出了根据本实施例的半导体封装100的结构的剖面图。
半导体封装100由作为电路衬底的封装衬底130、逻辑芯片200、DRAM 140以及快闪存储器160构成。这里，该封装衬底130的前表面设有互连层132，该封装衬底130的后表面设有凸点134。此外，为封装衬底130设置的互连层132通过之后描述的穿通电极110等电连接到逻辑芯片200。逻辑芯片200通过凸点120和凸点142电连接到DRAM140。这里，凸点120贴装在之后描述的逻辑电路116的顶部上。快闪存储器160贴装在DRAM 140上，以及快闪存储器160通过金引线162等电连接到为封装衬底130设置的互连层132。
图2示出逻辑芯片200的详细结构。
逻辑芯片200由衬底102、穿通电极110、逻辑电路116和转变输入信号和/或输出信号的电压和/或电流的转换器电路103构成。在本实施例中，衬底102是硅衬底。此外，逻辑电路116由用于逻辑电路的元件层149、以及形成在衬底102上的第一互连层144、第二互连层146和第三互连层148构成，逻辑电路149如此构成：在衬底102的前表面上形成晶体管等。转换器电路103由用于转换器电路的元件层113、以及在衬底102上形成的第一互连层104、第二互连层106和第三互连层108构成，转换器电路113如此构成：在衬底102的前表面上形成晶体管等。这里，转换器电路103具有转变从半导体封装100上设置的互连层132输入的电信号的电压电平和电流电平以输出到逻辑电路116的功能，以及具有转变从逻辑电路116输入的电信号的电压电平和电流电平以输出到互连层132的功能。
穿通电极110通过设置在衬底102的后表面上的凸点112电连接到设置在封装衬底130的互连层132的前表面上的凸点136。此外，穿通电极110电连接到第一互连层104中的互连114，同时穿透衬底102。在本实施例中，第一互连层104直接形成在用于逻辑电路的元件层149上。
这里，至于将穿通电极110连接到互连114的方法有各种方法。下面，将示出其一个例子。
首先，以从其后表面侧执行蚀刻衬底102的方式，形成穿透衬底102到第一互连层104中的互连114的孔。接下来，在衬底102上形成的孔的侧壁上形成绝缘膜。接着，在电镀金属时，用具有高导电性的金属如铜、铝、镍等填充孔。以如上所述的这种方式，形成穿通电极110。接下来，在穿通电极110的衬底102的后表面侧上电镀具有高导电性的金属如铜、铝、镍等以及金时，设置凸点112。根据以上所述，穿通电极110连接到互连114。
下面，将描述通过半导体封装100设有本实施例中的上述结构的事实引起的效果。
在本实施例中，穿通电极110没有电连接到第三互连层108，而是电连接到位于下层上的第一互连层104。因此，可以有效地利用设置穿通电极110的区域的原因在于在比第一互连层104更靠上的部分的区域上能够形成互连等。在穿通电极穿过互连层的顶部的结构的穿通电极中，在这种区域上不可以形成互连等，相反，在本实施例的结构中，在这点上提高了空间使用效率。
而且，因为穿通电极110、设置在逻辑芯片200的衬底102的后表面上的凸点112和设置在封装衬底130的互连层132的前表面上的凸点136彼此直接电连接，所以互连层132电连接到逻辑芯片200。在外周边设置连接端子的结构的逻辑芯片中，通过使半导体封装小型化，难以保证贴装连接端子的空间，相反，在本实施例的结构中，连接到封装衬底130的连接端子的数目能够充分地保证。因此，可以使逻辑芯片精细，以便可以使半导体封装100小型化。
此外，当制造逻辑芯片200或DRAM 140时，使用晶片工艺，因此，当在这些元件上形成穿通电极时，穿通电极形成在晶片上。这里，当其上贴装了元件的晶片面积相同时，其上形成穿通电极的每个晶片的成本相同。为此，当选择其中与由单个芯片制成较少数目的芯片的方法相比较由一个晶片能够制造大量芯片的方法形成穿通电极时，可以抑制每个芯片的制造成本增加。因此，与在大于如DRAM 140等的逻辑芯片200的大尺寸芯片上设置穿通电极的情况相比，在构成半导体封装100的半导体芯片当中，在小尺寸的逻辑芯片200上设置穿通电极110时，可以抑制每个芯片的制造成本增加。结果，可以提高逻辑芯片200的转换器电路103中的每个互连层中的空间使用效率，同时抑制制造半导体封装100的成本增加。
逻辑芯片200的电路表面设置在其上表面上；并且DRAM 140的电路表面(主表面)设置在其下表面上。这里，以在逻辑芯片200的电路表面侧上设置的凸点120面对在DRAM 140的电路表面(主表面)侧上设置的凸点142，接着彼此直接电连接的这样一种方式实现逻辑芯片200和DRAM 140之间的电连接。因此，在设置将逻辑芯片200连接到DRAM 140的互连时，可以抑制由逻辑芯片200和DRAM 140之间的电连接产生的负载电容增加。此外，由于电信号的访问数目能够随多管脚连接大大地增加，因此可以大大地增加从逻辑芯片200至DRAM140的传输信息量，从而变得可以保证宽的总线宽度。结果，抑制从逻辑芯片200至DRAM 140的电信号的传输延迟变为可能，从而能够以高速操作来操作元件。
第二实施例
在第一实施例中，一个结构是设置在封装衬底130上的互连层132通过凸点136和凸点112电连接到逻辑芯片200，但是，在封装衬底130和逻辑芯片200之间可以设置插入结构150。
图3是根据本实施例的半导体封装300的结构的剖面图。
设置在封装衬底130上的互连层132通过设置在互连层132的前表面上的凸点136和设置在插入结构150的衬底152的后表面上的凸点156电连接到插入结构150。此外，穿通电极155穿透插入结构150的衬底152，且电连接到插入结构150的互连层154。
插入结构150通过设置在插入结构150的互连层154前表面上的凸点158和设置在逻辑芯片200的衬底102后表面上的凸点112电连接逻辑芯片200，图2所示出了逻辑芯片200的详细结构。
下面，将描述半导体封装300的效果。
在某些情况下，通过逻辑芯片200的尺寸减小引起设置在逻辑芯片200的衬底102后表面上的凸点112的间距被最小化，当使对应于凸点112的间距的凸点136的间距最小化时，封装衬底的成本增加，凸点136贴装在互连层132前表面上，互连层132设置在封装衬底130上。
另一方面，在本实施例中，逻辑芯片200通过插入结构150连接到封装衬底130。为此，凸点136的间距不对应于凸点112的间距，但是凸点136的间距可以对应于贴装在插入结构150的衬底152后表面上的凸点156的间距，其中凸点136贴装在互连层132的前表面上，互连层132设置在封装衬底130上，凸点112贴装在逻辑芯片200的衬底102的后表面上。因此，凸点136的间距未被最小化可以是适合的，伴有逻辑芯片200的尺寸减小，凸点136贴装在互连层132的前表面上，互连层132设置在封装衬底130上。结果，除第一实施例的效果之外，在逻辑芯片200的转换器电路103内能够提高各个互连层的空间使用效率，同时抑制封装衬底130的成本增加。
如图4所示的半导体封装320，设置在封装衬底130上的互连层132的前表面可以直接与衬底152的后表面键合，以及设置在封装衬底130上的互连层132的前表面可以用金引线151等电连接到插入结构150的互连层154的前表面。
第三实施例
在第一实施例和第二实施例中，该结构是DRAM 140被贴装在逻辑芯片200上，但是，DRAM 140被贴装在封装衬底130上和逻辑芯片200被贴装在DRAM 140上的结构也是适合的。
图5是示出了根据本实施例的半导体封装340的结构的剖面图。
DRAM 140被贴装在封装衬底130上，逻辑芯片200被贴装在DRAM140上，以及用金引线101将贴装在逻辑芯片200的后表面上的凸点112电连接到设置在封装衬底130上的互连层132。
下面，将描述半导体封装340的效果。
DRAM 140的电路表面(主表面)设置在其上表面上；以及逻辑芯片200的电路表面设置在其下表面上。因此，以设置在逻辑芯片200的电路表面侧上的凸点120面对设置在DRAM 140的电路表面(主表面)侧的凸点142，接着彼此直接连接的这样一种方式，实现逻辑芯片200和DRAM 140之间的电连接。因此，在设置将逻辑芯片200连接到DRAM 140的互连时，可以抑制由逻辑芯片200和DRAM 140之间的电连接产生的负载电容增加。此外，由于通过多管脚连接能够大大地增加电信号的访问数目，因此可以大大地增加从逻辑芯片200到DRAM140的传输信息量，从而保证宽的总线宽度变为可能。结果，除第一实施例的效果之外，可以抑制从逻辑芯片200至DRAM 140的电信号的传输延迟，从而能够以高速操作来操作元件。
如上所述，已描述了发明的实施例。但是，当然，本发明不局限于上述实施例，且本领域的技术人员在本发明的范围内能够改变上述
实施例。
例如，在上述实施例中，使用其中逻辑电路116被设置在逻辑芯片的中心部分和转换器电路103被设置在逻辑芯片的周边的逻辑芯片200的结构；但是，如图6所示的半导体封装360，可以使用其中转换器电路103被设置在逻辑芯片的中心部分以及逻辑电路116被设置在逻辑芯片的周边的逻辑芯片220。
图7示出了逻辑芯片220的详细结构。逻辑芯片220由衬底102、穿通电极110、逻辑电路116和转换器电路103构成。此外，逻辑电路116由在衬底102的前表面上形成晶体管等的这样一种方式构成的用于逻辑电路的元件层149、形成在衬底102上的第一互连层144、第二互连层146和第三互连层148构成。转换器电路103由在衬底102上形成晶体管等的这样一种方式构成的用于转换器电路的元件层113、形成在衬底102上的第一互连层104、第二互连层106和第三互连层108构成。
穿通电极110通过贴装在衬底102的后表面上的凸点112和贴装在封装衬底130的互连层132的前表面上的凸点136电连接到封装衬底130。此外，贯穿衬底102的穿通电极110电连接到在第一互连层104内设置的互连114。
此外，在上述实施例中，该结构是穿通电极电连接到逻辑芯片的转换器电路103中的第一互连层104内的互连114，但是，可以是穿通电极电连接到各个互连层内的互连。
此外，在上述实施例中，描述了其中DRAM 140用作贴装在逻辑芯片200上的存储器的结构，但是在逻辑芯片200上贴装其它存储器如快闪存储器等以利用它也可以是适合的。
此外，如图8所示的半导体封装390，具有以通过贴装在存储器芯片170的前表面上的凸点172和贴装在存储器芯片170的后表面上的凸点174层叠具有穿通电极176的存储器芯片170的这样一种方式形成的多级结构的存储器180可以用作贴装在逻辑芯片200上的存储器。
此外，在逻辑芯片200的逻辑电路116和凸点120之间可以设置保护电路或保护元件。
此外，在上述实施例中，在转换器电路103内设置电连接到穿通电极110的互连114，但是，即使在其它位置上设置互连，互连也可以电连接到转换器电路103。
此外，在上述实施例中，描述了穿通电极110连接到转换器电路103中的第一互连层104的结构，但是，即使穿通电极110连接到其它电路如设置在逻辑电路116内的互连层，穿通电极110也可以连接到下层互连层。
此外，在上述实施例中，描述了在逻辑芯片中设置转换器电路的结构，但是，如图9所示的逻辑芯片250，可以在其中设置输入/输出缓冲器电路111。逻辑芯片250由衬底102、穿通电极110、逻辑电路116和输入/输出缓冲器电路111构成。此外，逻辑电路116由以在衬底102的前表面上形成晶体管等的这样一种方式构成的用于逻辑电路的元件层149、以及形成在衬底102的表面上的第一互连层144、第二互连层146和第三互连层148构成。此外，输入/输出缓冲器电路111由以在衬底102上形成晶体管等的这样一种方式构成的用于输入/输出缓冲器电路的元件层115、在形成衬底102上的第一互连层105、第二互连层107、第三互连层109构成。这里，至于输入/输出缓冲器电路111的例子，例如，指保护电路等。
很显然本发明不局限于上述实施例，在不脱离本发明的范围和精神的条件下可以进行改进和改变。

Claims (10)

1.一种半导体器件，包括：
第一半导体芯片，在所述第一半导体芯片的主表面上具有第一焊盘；
作为逻辑芯片的第二半导体芯片；
所述第二半导体芯片具有；
半导体衬底；
设置在所述半导体衬底的前表面上的多级互连层；
贯穿所述半导体衬底，连接到所述多级互连层内设置的导电元件的穿通电极；以及
贴装在所述多级互连层的顶部上的第二焊盘，
其中所述第一半导体芯片和所述第二半导体芯片通过所述第一焊盘和所述第二焊盘互相倒装芯片连接。
2.根据权利要求1的半导体器件，其中在所述多级互连层内的最下层中设置所述导电元件；以及所述穿通电极连接到所述导电元件。
3.根据权利要求1的半导体器件，其中所述第二半导体芯片具有逻辑电路，以及所述焊盘部分设置在所述逻辑电路的顶部上。
4.根据权利要求1的半导体器件，其中在所述穿通电极下设置电路衬底；以及所述电路衬底通过所述第一焊盘和所述第二焊盘连接到所述穿通电极的下表面。
5.根据权利要求4的半导体器件，还包括所述电路衬底和所述第二半导体芯片之间的插入结构，其中所述电路衬底电连接到所述插入结构，以及所述插入结构通过所述第一焊盘和所述第二焊盘连接到所述穿通电极的下表面。
6.根据权利要求1的半导体器件，其中所述第二半导体芯片具有缓冲器单元，该缓冲器单元具有输入缓冲器电路和输出缓冲器电路，以及所述导电元件设置在所述缓冲器单元中。
7.根据权利要求1的半导体器件，其中所述第二半导体芯片具有转换器电路单元，该转换器电路单元具有输入电压转换器电路和输出电压转换器电路，以及所述导电元件设置在所述转换器电路单元中。
8.根据权利要求1的半导体器件，其中所述第一半导体芯片是存储器。
9.根据权利要求1的半导体器件，其中所述第一半导体芯片是DRAM。
10.根据权利要求1的半导体器件，其中所述第一半导体芯片是快闪存储器。
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