CN1716619A - Soi衬底及其制造方法 - Google Patents
Soi衬底及其制造方法 Download PDFInfo
- Publication number
- CN1716619A CN1716619A CNA2005100823387A CN200510082338A CN1716619A CN 1716619 A CN1716619 A CN 1716619A CN A2005100823387 A CNA2005100823387 A CN A2005100823387A CN 200510082338 A CN200510082338 A CN 200510082338A CN 1716619 A CN1716619 A CN 1716619A
- Authority
- CN
- China
- Prior art keywords
- insulating barrier
- soi substrate
- electrode
- film
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004194639 | 2004-06-30 | ||
JP2004194639A JP4773697B2 (ja) | 2004-06-30 | 2004-06-30 | Soi基板およびその製造方法ならびに半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1716619A true CN1716619A (zh) | 2006-01-04 |
CN100463190C CN100463190C (zh) | 2009-02-18 |
Family
ID=35512997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100823387A Expired - Fee Related CN100463190C (zh) | 2004-06-30 | 2005-06-30 | Soi衬底及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7262486B2 (zh) |
JP (1) | JP4773697B2 (zh) |
CN (1) | CN100463190C (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5209477B2 (ja) | 2005-09-09 | 2013-06-12 | ノバルティス アーゲー | プリオンに特異的なペプトイド試薬 |
JP5696349B2 (ja) * | 2008-09-05 | 2015-04-08 | 株式会社Sumco | 裏面照射型固体撮像素子用ウェーハの製造方法 |
AU2010315133B2 (en) | 2009-11-04 | 2015-09-10 | Novartis Ag | Positively charged species as binding reagents in the separation of protein aggregates from monomers |
US8896102B2 (en) * | 2013-01-22 | 2014-11-25 | Freescale Semiconductor, Inc. | Die edge sealing structures and related fabrication methods |
JP6557953B2 (ja) | 2014-09-09 | 2019-08-14 | 大日本印刷株式会社 | 構造体及びその製造方法 |
KR101798574B1 (ko) * | 2016-05-02 | 2017-11-17 | 동부대우전자 주식회사 | 방열용 송풍기 및 이를 포함하는 냉장고 |
FR3062517B1 (fr) * | 2017-02-02 | 2019-03-15 | Soitec | Structure pour application radiofrequence |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02219252A (ja) * | 1989-02-20 | 1990-08-31 | Fujitsu Ltd | 半導体装置の製造方法 |
JPH02271657A (ja) * | 1989-04-13 | 1990-11-06 | Nec Corp | 能動層2層積層cmosインバータ |
JP2776149B2 (ja) * | 1992-06-15 | 1998-07-16 | 日本電気株式会社 | 半導体集積回路 |
US5426072A (en) * | 1993-01-21 | 1995-06-20 | Hughes Aircraft Company | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate |
JP2000323484A (ja) * | 1999-05-07 | 2000-11-24 | Mitsubishi Electric Corp | 半導体装置及び半導体記憶装置 |
JP2001068647A (ja) * | 1999-08-30 | 2001-03-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6576957B2 (en) * | 2000-12-31 | 2003-06-10 | Texas Instruments Incorporated | Etch-stopped SOI back-gate contact |
JP4020367B2 (ja) | 2001-04-17 | 2007-12-12 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6815751B2 (en) * | 2002-07-01 | 2004-11-09 | International Business Machines Corporation | Structure for scalable, low-cost polysilicon DRAM in a planar capacitor |
-
2004
- 2004-06-30 JP JP2004194639A patent/JP4773697B2/ja not_active Expired - Lifetime
-
2005
- 2005-06-17 US US11/154,514 patent/US7262486B2/en active Active
- 2005-06-30 CN CNB2005100823387A patent/CN100463190C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN100463190C (zh) | 2009-02-18 |
JP4773697B2 (ja) | 2011-09-14 |
US7262486B2 (en) | 2007-08-28 |
US20060001090A1 (en) | 2006-01-05 |
JP2006019424A (ja) | 2006-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C56 | Change in the name or address of the patentee |
Owner name: RENESAS ELECTRONICS CORPORATION Free format text: FORMER NAME: NEC CORP. |
|
CP01 | Change in the name or title of a patent holder |
Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa, Japan Patentee before: NEC Corp. |
|
ASS | Succession or assignment of patent right |
Owner name: DESAILA ADVANCED TECHNOLOGY COMPANY Free format text: FORMER OWNER: RENESAS ELECTRONICS CORPORATION Effective date: 20141029 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20141029 Address after: American California Patentee after: Desella Advanced Technology Company Address before: Kanagawa, Japan Patentee before: Renesas Electronics Corporation |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090218 Termination date: 20190630 |
|
CF01 | Termination of patent right due to non-payment of annual fee |