CN1168133C - 半导体晶片、半导体器件及其制造方法 - Google Patents

半导体晶片、半导体器件及其制造方法 Download PDF

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CN1168133C
CN1168133C CNB011238097A CN01123809A CN1168133C CN 1168133 C CN1168133 C CN 1168133C CN B011238097 A CNB011238097 A CN B011238097A CN 01123809 A CN01123809 A CN 01123809A CN 1168133 C CN1168133 C CN 1168133C
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semiconductor
semiconductor chip
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resin molding
chip
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CN1336687A (zh
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宫川优一
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Renesas Electronics Corp
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Abstract

本发明的目的在于当切割半导体晶片时,可容易地防止半导体背面上的碎裂,能够容易地防止焊丝的边缘接触。在为半导体芯片(8)的芯片分割而设置的边界区(对应于6)周围形成树脂膜(14)。然后,沿着边界区的中心部分(对应于7)切割半导体晶片。此外,在半导体衬底上形成有半导体元件的半导体器件中,在为了芯片分割而设置的边界区的部分上形成了与每个芯片的焊盘(3)匹配的树脂膜(14)。也可以是,在上述边界区周围以预定宽度形成了树脂膜(14)。还可以是,在安装半导体芯片中连接焊丝(16)时,其设置使得半导体衬底(9)和上述焊丝不接触。

Description

半导体晶片、半导体器件及其制造方法
技术领域
本发明涉及半导体晶片、半导体器件及其制造方法。本发明特别涉及半导体晶片的切割部分的结构、用于芯片分割的切割方法和半导体器件的边缘部分的结构。
背景技术
像绝缘栅场效应晶体管(下文称为MOS晶体管)等的半导体元件的结构微型化仍在快速发展。在微型化方面,目前正在研究采用尺寸大约为0.1μm至0.2μm的半导体元件,利用这些尺寸作为设计原则,含有16Gb级的DRAM、超高速逻辑或二者兼有的ULSI半导体器件正处于研制和发展中。
为了半导体器件的高度集成、高速度、高性能和其它的多种功能,用于安装半导体器件的高密度半导体芯片安装技术,与用于制造半导体器件的精加工技术一起扮演着重要的角色。特别是近些年,为了用于便携式设备,利用多芯片封装(MCP)技术(在一个封装中含有两个或更多个芯片)、芯片规格封装(chip scale package)技术等安装半导体芯片以及半导体集成电路(IC)微型化已经是很重要的了。
发展上述高密度安装技术,需要在含有半导体器件的半导体晶片上利用树脂膜形成保护绝缘膜。因此,目前在上述半导体晶片上形成了光敏树脂膜如聚酰亚胺树脂膜。
此外,在切割半导体晶片以分离半导体芯片的工艺中,认为这种树脂膜在防止半导体芯片表面上的缺陷(碎裂)方面起着重要的作用。
据此,形成了上述用于保护半导体芯片的树脂膜,使其覆盖半导体晶片的切割部分(切割通道)的整个表面,沿着这个切割通道,用金刚石切刀来切割半导体晶片。例如,在日本未审专利申请第一次公开No.62-063446和日本未审专利申请第一次公开No.62-112348中描述了该技术。
下面是传统技术的说明,参考图8,图8是半导体晶片的局部平面图。这里,示出了四个芯片的边缘部分。此外,为了清楚,在覆盖半导体晶片的树脂膜上画出了斜纹线。
如图8所示,半导体元件区(半导体芯片)102、102a、102b和102c形成在半导体晶片101上。这里,在每个半导体元件区的边缘部分上形成了焊盘103。除了设在焊盘103上的开口104之外,在整个表面上形成了树脂膜105。这里,在半导体元件区102、102a、102b和102c之间以预定的宽度形成为芯片分割而提供的切割通道(即边界区106),形成的树脂膜覆盖该切割通道106的整个表面。
在切割半导体晶片以形成半导体芯片的情况下,沿图8中虚线所示的分割线107,用金刚石切刀切割半导体晶片。这里,将金刚石切刀在覆盖切割通道106的树脂膜顶部切割,透过该树脂膜来切割上述半导体晶片。
然而,已知上述传统技术存在下列问题。如果在切割通道上形成了树脂膜105,必然会减小在半导体晶片切割工艺中的碎裂。然而,在半导体晶片被切割后,本发明人对半导体芯片进行了仔细的检查,发现在半导体芯片的背面很容易出现大量的碎裂。
一般,在完成半导体器件制造工艺的前一半(扩散工艺)之后,将半导体晶片的背面研磨到300μm的厚度之下。经过上述处理后,切割半导体晶片。具有高性能或多功能的半导体集成电路(IC)的半导体晶片在研磨后具有更小的厚度。结果,当制造上述前沿半导体集成电路(IC)时,经过上述切割后,在半导体芯片的安装工艺(后半部分制造工艺)、例如管芯键合工艺中,半导体芯片背面上的碎裂容易引起如与夹具接触不良的问题。这种问题在上述MCP的安装中尤为严重。
因此,为了解决传统技术的上述问题,如图9(a)所示,提出了一种方法,在半导体元件区102、102a、102b和102c中形成树脂膜105a,但去掉切割通道106上的树脂膜。然后沿着分割线107切割半导体晶片,形成半导体芯片。
然而,在这种情况下,如图9(b)所示,当安装通过切割半导体晶片形成的半导体芯片时,在焊丝的连接方面出现了大问题。下面描述图9(b)所示的半导体芯片108的剖面结构:在形成了半导体元件的半导体衬底109上形成了无机绝缘膜110,在其上面形成了焊盘103,在顶部形成了具有开口104的树脂膜105a。在带状衬底或安装在衬底上的针脚(stitch)111与焊盘103之间连接焊丝112。然而,该焊丝很容易弯曲,成为变形的焊丝113,这种变形的焊丝会使其与半导体芯片108的边缘接触。这里,在图9(a)所描述的方法中,由于半导体衬底109的表面在切割通道106处被暴露,焊丝112引起与半导体衬底109的短路,这种短路阻碍了半导体器件的工作。也就是说,很容易出现焊丝的边缘接触,可能频繁地制造出有缺陷的半导体集成电路(IC)。
发明内容
本发明的目的是防止在半导体晶片切割过程中,在半导体芯片背面上出现的碎裂。本发明的另一个目的是使其能够容易地防止上述边缘接触。
因此,在本发明的半导体晶片中,将用于分割半导体芯片的切割通道的区域分为与半导体芯片周边相接邻的周边区域和要被切割的切割区域,将树脂膜涂敷到周边区域。
此外,在本发明的半导体器件制造方法中,将设定在半导体晶片上的用于分割半导体芯片的切割通道的区域分为与半导体芯片周边相接邻的周边区域和要用切刀切割的切割区域,将树脂膜涂敷到周边区域,沿着切割区域的中心部位切割半导体晶片。这里树脂膜的宽度大于10μm。
此外,在本发明的半导体器件中,将用于分割半导体芯片的切割通道的区域分为与半导体芯片周边相接邻的周边区域和切割区域,将树脂膜涂敷到周边区域。
树脂膜的宽度设定为大于10μm。也可以将树脂膜的厚度设定为大于或等于0.1μm。
在本发明中,在为半导体芯片的分割而设置的切割区域的周围形成了树脂膜。因此,当切割半导体晶片时,所形成的半导体芯片的背面上的碎裂被显著减小。此外,在安装通过切割半导体晶片而形成的半导体芯片时,当连接焊丝时,根本不会出现上述边缘接触问题。通过这种方式,显著提高了半导体芯片安装工序的成品率。
附图说明
图1是说明本发明第一实施例的半导体晶片的平面图;
图2A和2B是半导体晶片切割后的截面图,说明本发明的效果;
图3A是半导体晶片的平面图,说明本发明的第二实施例;
图3B是说明半导体芯片安装的剖视图;
图4是说明本发明第二实施例的另一个半导体晶片的平面图;
图5是说明本发明第二实施例的另一个半导体晶片的平面图;
图6是说明本发明第二实施例的另一个半导体晶片的平面图;
图7是MCP的剖视示意图,其中安装了半导体芯片;
图8是说明传统技术的半导体晶片平面图;以及
图9A和9B是说明传统技术的半导体晶片平面图和说明半导体芯片安装的剖视图。
具体实施方式
下面是基于图1和图2的关于第一实施例的描述。图1是半导体晶片的局部平面图。这里,与图8的说明类似,示出了四个芯片的边缘部分。此外,为了清楚,在覆盖半导体晶片的树脂膜上画出了阴影线。
如图1所示,在半导体晶片1上形成了作为半导体芯片的半导体元件区2、2a、2b和2c。在每个半导体元件区的边缘形成了焊盘3。以树脂膜图形存在的树脂膜5、5a、5b和5c分别覆盖半导体元件区2、2a、2b和2c,但避免覆盖设在每个焊盘3上的开口4和连接通道6的中央区域,该连接通道是为芯片分离而提供的边界区域。这里,控制每个树脂膜从半导体元件区延伸到连接通道6区的量也就是图1所示覆盖量d是很重要的。这一点在下面将要描述。这里树脂膜5、5a、5b和5c包括光敏树脂例如聚酰亚胺树脂等。
当切割上述半导体晶片,以形成半导体芯片时,是沿着图1中的虚线所示的切割线7,用金刚石切刀来切割的。这里,将金刚石切刀施加在半导体晶片1的暴露的半导体衬底上,不像传统的技术那样接触树脂膜。在传统技术中,像聚酰亚胺等的树脂膜粘到金刚石切刀上,降低了切割效率。因此,在切割时需要给刀片施加大功率。然而,在本发明中,没有出现像上面提到的粘树脂,因而在切割时降低了刀片施加到半导体衬底上的力。结果,如下面所提到的,本发明减小了碎裂量。
参考图2和表1,下面是本实施例的效果说明。这里,图2(a)是本发明的情况,图2(b)是图8所描述的传统技术的情况。
如图2(a)所示,在本发明中,通过切割形成了半导体芯片8和8a。这里,在图2(a)中虚线所示的半导体衬底9和9a上形成了无机绝缘膜10,并且分别在顶部上形成了树脂膜5和5a。上述切割引起在半导体芯片8和8a的表面侧的边缘出现碎裂11和11a,在相反侧出现背面的碎裂12和12a。
类似地,如图2(b)所示,在传统方法中,通过切割形成半导体芯片108和108a。这里,穿过图2(b)中虚线所示的树脂膜105的区域,切割半导体晶片101。在半导体衬底109和109a上形成了无机绝缘膜110,在顶部形成了树脂膜105并切割该绝缘膜。上述切割引起在半导体芯片108和108a的表面侧边缘出现表面碎裂,在相反侧上出现背面的碎裂115和115a。
通过表1描述了这种碎裂的程度。如表1所示,在本发明的情况下,大大减小了背面碎裂12和12a的长度,该长度小于或等于在传统方法中背面碎裂115和115a长度的十分之一。这里,碎裂的长度是碎裂从半导体芯片的边缘延伸到半导体元件区内侧的长度。
                          表1
本发明(碎裂长度) 传统方法(碎裂长度)
  半导体芯片表面     5-10μm     5-10μm
  半导体芯片背面     到15μm     150-200μm
更详细地说,在本发明的情况下,如图1所示,半导体芯片表面上的碎裂长度为5-10μm。此外,在传统方法中,半导体芯片表面上的碎裂长度为5-10μm,与本发明相同。这就是说,在本发明中,从半导体元件区的边缘到切割通道6区,树脂膜5、5a、5b和5c的覆盖量d最好大于10μm。这是因为表面碎裂11和11a的长度如上所述为10μm或更小。如果覆盖量超过d超过这个值,那么表面碎裂不会到达半导体元件区,因此对半导体元件没有任何影响。
另一方面,在背面上,在本发明的情况下,背面的碎裂长度为15μm或更小。而在传统方法的情况下,背面碎裂的长度达到150μm至200μm。
当制造上述前沿半导体集成电路(IC)时,在半导体芯片安装工艺中的管芯键合过程中,这种背面碎裂的减小显著降低了与夹具的不良接触。
下面基于图3至图6描述本发明的第二实施例。在该第二实施例中,描述了容易地避免上述半导体芯片的边缘接触问题的方法。图3(a)和图4至图6是半导体晶片的局部平面图。这里,为了简便,示出了两个芯片的边缘部分。此外,为了清楚,在覆盖半导体晶片的树脂膜上画出了阴影线。图3(b)是图3(a)中的半导体晶片经切割后得到半导体芯片的截面图,该半导体芯片通过焊丝与安装夹具连接。这里,与第一实施例相同的部分用相同的标号来表示。
如图3(a)所示,在半导体晶片1上形成了半导体元件区2和2a。在每个半导体元件区的边缘部分上形成了焊盘3。树脂膜13和13a分别覆盖半导体元件区2和2a,但是要避免覆盖设在每个焊盘3上的开口4。
在切割通道6区中形成了边缘接触防护膜,也就是树脂膜图形,每个都对应于上述焊盘3。这里,上述树脂膜13、13a和边缘接触防护膜14包括光敏聚酰亚胺树脂膜。
在切割上述半导体晶片,形成半导体芯片的情况下,沿着图3(a)中虚线所示的分割线7,用金刚石切刀来切割。这里,金刚石切刀施加在半导体晶片1的暴露的半导体衬底,金刚石切刀不像传统技术那样接触树脂膜。因此,就像在第一实施例中所提到的,减小了半导体芯片的碎裂量。
在图3(b)所示的第二实施例的情况下,在安装通过切割上述半导体晶片而形成的半导体芯片中连接焊丝时,根本不会出现边缘接触问题。这一点将参考图3(b)来说明。
下面描述图3(b)所示的半导体芯片8的轮廓:在形成了半导体元件的半导体衬底9上形成了无机绝缘膜10,在其上部形成了焊盘3,在顶部形成了具有开口4的树脂膜13。在与安装夹具的外端连接的针脚15和焊盘3之间连接焊丝16。这里,如在传统技术中所描述的,焊丝16可很容易地弯曲,成为变形的线17,这会使焊丝与半导体芯片108的边缘接触。
然而,在本发明中,如图3(a)和图3(b)所示,边缘接触防护膜14形成在切割通道6区的部分中,面对焊盘3。这里,如图3(b)所示,形成边缘接触防护膜14,使其与树脂膜13成为一个整体。既然边缘接触防护膜14使变形的焊丝17和半导体衬底隔离开,绝不会出现上述传统技术的情况下提到的短路现象,因而不会出现有缺陷的半导体集成电路(IC)产品。这种边缘接触防护膜14的厚度可以是0.1μm或更大。
在第二实施例中,图3(a)所示的边缘接触防护膜14的图形形状可以有几种变化。该树脂膜图形的形状将参考图4-6来描述。下面关于图形的说明主要集中在边缘防护膜。注意没有描述的部分与图3(a)所描述的一样。
如图4所示,形成半导体元件区2和2a,在各半导体元件区的边缘部分形成焊盘3。树脂膜13和13a分别覆盖半导体元件区2和2a,但避免覆盖设在焊盘3上的开口4。
在半导体元件区2的所有的焊盘3的旁边,在切割通道6区中形成一个边缘接触防护膜18。此外,在半导体元件区2a的焊盘3的旁边形成边缘防护膜19和20。
在图5中,在半导体元件区2和2a的焊盘旁边,在切割通道6区中形成了边缘防护膜21、22、21a和22a。
如图6所示,在半导体元件区2和2a的焊盘旁边,在切割通道6区中,形成了边缘接触防护膜23和24。
在切割上述半导体晶片形成半导体芯片的情况下,是沿着图6中虚线所示的分割线用金刚石切刀来切割的。这里,金刚石切刀也接触边缘防护膜23和24,并切割这些区。然而,在这种情况下,有些区没有被边缘接触防护膜覆盖。既然金刚石切刀接触上述没有被边缘防护膜覆盖的区中的半导体衬底表面,在这些区中,金刚石切刀被刷干净。结果,即使树脂膜粘到切刀上,也被移去了。在这种情况下,背面碎裂的出现也少于在传统技术的情况下出现的碎裂。
在第二实施例中描述的方法对MCP安装技术很有效果。上述MCP安装情况的例子将参考图7来说明。如图7所示,在衬底上形成第一布线层32,并连接到外封装端子31。通过第一热压键合片33使第一半导体芯片34形成与衬底的连接。该第一半导体芯片34的焊盘通过第一焊丝即焊丝35与第一布线层32电连接。
此外,通过第二热压键合片36将第二半导体芯片37连接到第一半导体芯片34上。然后,通过第二焊丝即焊丝38将第二半导体芯片37的焊盘与第二布线层39电连接。这里,例如,在第一半导体芯片34上形成了SRAM,然后在第二半导体芯片37上形成了闪速存储器。以这种方式,就构成了具有新功能的半导体集成电路(IC)。
在这种MCP中,具有长的焊丝。在图7所示的情况下,用于连接第二半导体芯片37的第二焊丝38比正常的焊丝更长。因此,如上所述该焊丝很容易弯曲,很可能出现变形的焊丝与第二半导体芯片37的边缘接触。也会出现与第一半导体芯片34的边缘接触。
这里,如果用本发明的方法制造这些半导体芯片,特别是第二半导体芯片37,由于上述边缘接触防护膜,不会出现第一焊丝38和第二半导体芯片37之间的短路现象。
在本发明中,在为半导体芯片的芯片分割而设置的边界区的周围形成了树脂膜。然后,沿着边界区的中心部分切割半导体晶片。结果,显著减少了由切割而引起的半导体芯片的背面上的碎裂。
此外,在具有半导体元件的半导体器件中,其中该半导体元件形成在半导体衬底上,在为芯片分割而提供的边界区的部分中形成了树脂膜图形,该图形与每个芯片的焊盘相匹配。也可以沿着边界区以预定的宽度形成树脂膜图形。结果,在安装通过切割半导体晶片而形成的半导体芯片时,当连接焊丝时,根本不会出现边缘接触问题,即半导体衬底和上述焊丝接触的问题。
以这种方式,显著提高了半导体芯片安装工序的成品率。本发明有助于高密度封装的半导体器件的超高集成化和高密度化。

Claims (12)

1.一种半导体晶片,其特征在于:将用于分割半导体芯片的切割通道的区域分为与半导体芯片周边相接邻的周边区域和要被切割的切割区域,将树脂膜涂敷到上述周边区域。
2.如权利要求1所述的半导体晶片,其中所述树脂膜与所述半导体芯片上设定的焊盘位置相对应而设定。
3.如权利要求1所述的半导体晶片,其中所述树脂膜被设定在芯片周边区域的整个周边。
4.如权利要求1所述的半导体晶片,其中所述树脂膜的宽度被设定为大于10μm。
5.一种半导体器件的制造方法,其特征在于,将设定在半导体晶片上的用于分割半导体芯片的切割通道的区域分为与半导体芯片周边相接邻的周边区域和要用切刀切割的切割区域,将树脂膜涂敷到上述周边区域,沿着所述切割区域的中心部位切割半导体晶片。
6.如权利要求5所述的半导体器件的制造方法,其中所述树脂膜与所述半导体芯片上设定的焊盘位置相对应而设定。
7.如权利要求5所述的半导体器件的制造方法,其中所述树脂膜被设定在芯片周边区域的整个周边。
8.如权利要求5所述的半导体器件的制造方法,其中,所述树脂膜的宽度被设定为大于10μm。
9.一种在半导体衬底上形成有半导体元件的半导体器件,其特征在于,将用于分割半导体芯片的切割通道的区域分为与半导体芯片周边相接邻的周边区域和切割区域,将树脂膜涂敷到上述周边区域。
10.如权利要求9所述的半导体器件,其中所述树脂膜被设定在所述半导体芯片上。
11.如权利要求9所述的半导体器件,其中所述树脂膜的宽度被设定为大于10μm。
12.如权利要求9所述的半导体器件,其中,所述树脂膜的厚度被设定为大于或等于0.1μm。
CNB011238097A 2000-07-31 2001-07-30 半导体晶片、半导体器件及其制造方法 Expired - Fee Related CN1168133C (zh)

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JP2003338519A (ja) * 2002-05-21 2003-11-28 Renesas Technology Corp 半導体装置及びその製造方法
JP4796271B2 (ja) * 2003-07-10 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7183137B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
JP4488733B2 (ja) * 2003-12-24 2010-06-23 三洋電機株式会社 回路基板の製造方法および混成集積回路装置の製造方法。
US20060028430A1 (en) * 2004-06-21 2006-02-09 Franz Harary Video device integratable with jacket, pants, belt, badge and other clothing and accessories and methods of use thereof
JP4471852B2 (ja) * 2005-01-21 2010-06-02 パナソニック株式会社 半導体ウェハ及びそれを用いた製造方法ならびに半導体装置
JP4757056B2 (ja) * 2006-02-21 2011-08-24 富士通株式会社 樹脂層の形成方法並びに半導体装置及びその製造方法
JP4822880B2 (ja) * 2006-03-02 2011-11-24 株式会社リコー 半導体ウエハ、半導体装置及び半導体装置の製造方法
US7382038B2 (en) * 2006-03-22 2008-06-03 United Microelectronics Corp. Semiconductor wafer and method for making the same
KR20120019095A (ko) * 2010-08-25 2012-03-06 삼성전자주식회사 반도체 패키지, 이를 갖는 멀티-칩 패키지, 및 이들의 제조 방법
JP2013168624A (ja) * 2012-01-20 2013-08-29 Semiconductor Components Industries Llc 半導体装置
US9958918B2 (en) * 2016-05-23 2018-05-01 Qualcomm Incorporated Systems and methods to separate power domains in a processing device
JP2019054172A (ja) * 2017-09-15 2019-04-04 東芝メモリ株式会社 半導体装置
US20190131247A1 (en) * 2017-10-31 2019-05-02 Microchip Technology Incorporated Semiconductor Wafer Cutting Using A Polymer Coating To Reduce Physical Damage

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