CN1913149A - 包括叠层芯片的半导体器件生产方法及对应的半导体器件 - Google Patents

包括叠层芯片的半导体器件生产方法及对应的半导体器件 Download PDF

Info

Publication number
CN1913149A
CN1913149A CNA2006100928824A CN200610092882A CN1913149A CN 1913149 A CN1913149 A CN 1913149A CN A2006100928824 A CNA2006100928824 A CN A2006100928824A CN 200610092882 A CN200610092882 A CN 200610092882A CN 1913149 A CN1913149 A CN 1913149A
Authority
CN
China
Prior art keywords
chip
redistribution layer
working surface
mold
reconstructed wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006100928824A
Other languages
English (en)
Other versions
CN100517694C (zh
Inventor
H·赫德勒
T·迈尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN1913149A publication Critical patent/CN1913149A/zh
Application granted granted Critical
Publication of CN100517694C publication Critical patent/CN100517694C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

形成第一重构晶片(reconstituted chip)的方法包括以下步骤：用由塑模填充的第一间隙将第一组多个芯片水平地分隔开来；在第一重构晶片的工作表面上形成第一再分配层。在上述步骤之前和/或之后，并行地形成了第二重构晶片。沿第二间隙切割上述第二重构晶片，以便形成各个嵌入式芯片。此后，在上述嵌入式芯片的工作表面和倾斜侧壁上形成了第二再分配层。

Description

包括叠层芯片的半导体器件生产方法及对应的半导体器件
技术领域
本发明涉及一种包括叠层芯片的半导体器件的生产方法以及对应的半导体器件。
背景技术
尽管原则上能将本发明应用于包括叠层芯片的半导体器件的任何生产方法，但在下文中将通过包括两个存储器芯片的半导体存储器件的生产方法来阐述本发明和其潜在问题。
计算机、手机、照相机等现代电子产品由多个包括半导体存储器件的单个电子器件组成。要求生产工艺减少单个电子器件的数目，以缩短电子产品的生产时间。因此，将几个存储器芯片归并到单个半导体存储器件内，以便通过单个生产步骤将这些存储器芯片设置在电子产品中。而且，要求电子产品小型化。通过把存储器芯片归并或预集成在单个外壳内，可获得更高集成密度的存储器芯片，从而可以减小它们的外部尺寸。
公知的一种半导体存储器件包括两个如图1所示的存储器芯片。第一存储器芯片110设置在插入衬底(interposer substrate)150上，并经过接触垫152和连接线151与插入衬底150电连接。沿第一存储器芯片110工作表面的边界设置接触垫152，并用粘合层161将隔层160固定在介于接触垫152之间的第一芯片110的工作表面区域中。第二存储器芯片110′固定在隔层160上。在第二存储器芯片110′工作表面边界处也设有接触垫152′。接触垫152′经过连接线151′与插入衬底150连接。上述没置允许第一存储器芯片110和第二存储器芯片110′通过插入衬底150进行互连，从而可减小外部触点153的数目。此外，与各包括一个封装的存储器芯片的两个半导体存储器相比，外壳154内集成的两个存储器芯片110、110′所占据的空间得到了显著的减小。
必须用最小压力将连接线151、151′设置到接触垫152、152′。因为隔层160未对第二存储器芯片110′的边界(即接触垫152′所在区域)提供机械支撑，因而连接线151′的接触将导致第二存储器芯片110′的内部产生较大的机械应力。为避免损害第二存储器芯片110′，则不能进一步减小其厚度。此外，隔层160本身增大了半导体器件的高度。因此，应用前述概念来进一步减小半导体存储器件的外部尺寸是不现实的。
上述结构的另一缺点在于，在生产期间，必须用连接机械来使各条连接线151、151′与各个接触垫进行接触。这些连接步骤显著地延长了生产时间，并由此增加了半导体存储器件的成本。
发明内容
本发明的一个目的是提供一种改进的用于生产包括叠层芯片的半导体器件的方法。
本发明的另一目的是提供一种用于生产包括叠层芯片的半导体器件的方法，在其中，减小了半导体器件的高度。另一个目的是减少生产封装的半导体器件所需的时间。
根据本发明，通过创造性的生产方法和半导体器件，至少实现了上述一个目的和其他目的。上述生产包括叠层芯片的半导体器件的创造性方法包含以下步骤：用由塑模填充的第一间隙将第一组多个芯片水平地分隔开来，其中，上述第一组多个芯片的接触垫设置在上述第一重构晶片的工作表面(active surface)中；在第一重构晶片的工作表面上形成第一再分配层，其中上述再分配层与上述第一组多个芯片的接触垫接触，并在上述塑模上延伸。在上述步骤之前和/或之后，并行地形成了第二重构晶片，其方法包括：用由塑模填充的第二间隙将第二组多个芯片水平地分隔开来，其中，上述第二组多个芯片的接触垫设置在与上述第二重构晶片的背侧相对的工作表面中。沿上述第二间隙切割上述第二重构晶片，以便形成各个嵌入式芯片，这些芯片具有与上述重构晶片的工作表面成大于90度夹角的倾斜侧壁。并且，上述嵌入式芯片的背侧设置在上述第一再分配层上的第一重构晶片的工作表面上。此后，在上述嵌入式芯片的工作表面和倾斜侧壁上形成了第二再分配层，其中，上述第二再分配层连接了上述第二组多个芯片的接触垫和上述第一再分配层。
本发明的半导体器件至少包含第一芯片和第二芯片，其中，上述第一芯片具有与之水平相邻的第一塑模，上述第二芯片具有与之水平相邻的第二塑模，上述第二芯片设置在上述第一芯片的工作表面上，且至少上述第二塑模包含倾斜的侧壁，而上述第一塑模具有比上述第二塑模更大的水平尺寸。在所有这些芯片的工作表面上设置了再分配层，并由该再分配层将这些芯片的接触垫进行互连，其中，上述再分配层沿上述倾斜侧壁分布。而且，将具有接触垫的载体与该再分配层在第一塑模区域中进行连接。
本发明的基本概念在于，当多个芯片设置在第一重构晶片中或第一重构晶片上时，可以并行地处理这些芯片。因此，在同一步骤中，为多个芯片形成了第一和第二再分配层。
本发明的第二个主要特征是为嵌入式芯片提供了倾斜侧壁。因此，能够使第二再分配层沿该倾斜侧壁分布，并因此将位于嵌入式芯片的工作表面上的第二再分配层与在塑模上延伸的第一再分配层连接在一起。从而，不需提供通孔或连接线来接触上部的第二芯片的接触垫。应当理解，并非沿倾斜侧壁分布的第二再分配层的所有引线均需连接到第一再分配层。允许在倾斜侧壁上延伸的第二再分配层接触较下方或最下方的嵌入芯式片上的第二再分配层。由于在叠层顶部不设置触点，因此这种方式有利于减小叠层的高度。
应当理解，因为倾斜侧壁与第二重构晶片的工作表面形成了大于90度的夹角，因而嵌入式芯片的背侧表面比其工作表面更大。
从属权利要求给出了对上述生产方法和半导体器件的有利改进和改善。
根据上述改进内容，在形成第二再分配层之后，沿第一间隙切割第一重构晶片，从而提供了互连的主要芯片产品。
根据优选的改进内容，在第三嵌入式芯片的工作表面上形成第三再分配层后，将第四嵌入式芯片的背侧设置在上述第三嵌入式芯片的工作表面上，并在上述第四嵌入式芯片的工作表面上形成第四再分配层。上述第三嵌入式芯片可以是第二嵌入式芯片，且上述第三再分配层可以是上述第二再分配层。因此，可以形成三个或更多个芯片的主要芯片产品。
根据另一改进内容，第一间隙比第二间隙宽。因此，当将嵌入式芯片设置在第一芯片上时，第一间隙中的塑模的局部仍然暴露在外面，从而，可以将第二再分配层设置在上述塑模上，并使其与第一再分配层接触。
根据另一优选的改进内容，将上述互连的主要芯片产品设置在载体上，且第一再分配层与该载体上提供的接触区域相接触。
附图说明
在附图中示出了本发明的示范性实施例，并在下面的说明中更详细地阐述了本发明的这些实施例。
图1示出了公知的具有叠层芯片的半导体器件；
图2-19示出了创造性方法的各个步骤；和
图20示出了根据本发明的半导体器件的第二个实施例。
在图2-20中，相同的附图标记代表相同或功能等价的部件。
具体实施方式
在第一步骤(图2)中，提供了中间载体1或载体板。将粘合层2或粘胶带设置在中间载体1上(图3)。切割一个或多个经过处理的半导体晶片，由此提供了一些单个的芯片10。这些芯片10的功能和/或尺寸可以相同，也可以不同。芯片10设置在中间载体1上，且两个相邻的芯片10之间通过间隙4进行水平分隔。优选地，相邻芯片10之间的所有间隙4的宽度d(两个相邻芯片10之间的距离)均相同。每个芯片10的工作表面均设置在中间载体1上。包含接触垫11的芯片10的那个表面即为工作表面12。因此，工作表面12由中间载体1进行覆盖，且与工作表面12相对的背侧13仍然暴露在外面(图4)。
在随后的步骤中，在上述结构上设置塑模5。淀积塑模5，以便使芯片10嵌入在该塑模中(图5)。该塑模5可以由树脂或聚合物制成。随后，除去中间载体1和粘合层2(图6)。这样，便留下了基本的重构晶片20，该晶片包括多个嵌入在塑模5中的芯片10。且芯片10的工作表面12暴露在外面。
任选地，在以100标识的方向上，可进行抛光步骤来除去与工作表面12相对的表面上的塑模5，或使该塑模变薄。优选地，方向100垂直于芯片10的工作表面12。该抛光步骤也可减小芯片10的厚度(图7)。
将基本的重构晶片20的背侧13(即存储器芯片10的背侧13)设置到切割层8上。沿间隙4切割该基本的重构晶片20，从而，在塑模5中形成了开口7(图8)。在进行切割步骤之后，各个芯片10均具有在水平方向上与之邻接的塑模5的一部分。以下，将具有与之水平邻接的塑模5的局部的芯片10称为嵌入式芯片30(图9)。嵌入式芯片30的侧壁是倾斜的(例如，侧壁21与嵌入式芯片30的工作表面12形成的角度α大于90度)。可通过用V字形刀片切割基本的重构晶片20或以与工作表面12成大于90°的角切割基本的重构晶片20来实现这个结构。
用与形成基本的重构晶片20类似或相同的步骤(图2至7)形成了第一重构晶片20′。与基本的重构晶片20相比，第一重构晶片20′可包含不同或相同的芯片10′。优选地，两个相邻芯片10′之间的距离d′大于基本重构晶片20的两个相邻芯片10之间的距离d。
在第一重构晶片20′的工作表面12′上形成第一再分配层15′。第一再分配层15′接触第一芯片10′的接触垫11′，并延伸到塑模5′上(图11)。在第一芯片10′上和/或第一重构晶片20′的工作表面12′上设置了粘合层16′(图12)。
在粘合层16′上设置嵌入式芯片30″(优选地，该芯片的形成方式与图9所示的嵌入式芯片30形成的方式类似)。设定嵌入式芯片30″的方位，使得其背侧13″指向第一重构晶片20′。通过第二重构晶片20″形成了嵌入式芯片30″，其中，两个相邻的芯片10″之间的间隙d″远小于第一重构晶片20′的两个第一芯片10′之间的间隙d′。在一个例子中，第二重构晶片中的间隙的宽度为d″，在对第二重构晶片进行切割之后，每个嵌入式芯片30″包括宽度为d″/2的、并与之水平邻接的塑模5″。在该特定的实例中，d′远大于d″。第一再分配层15′在塑模5′上的延伸部分比嵌入式芯片30″的剩余塑模5″的宽度d″/2长。因此，至少一部分第一再分配层15′没有被嵌入式芯片30″覆盖(图13)。
此后，在与接触垫11″接触的嵌入式芯片30″的工作表面12″上形成第二再分配层15″。同样，也将第二再分配层15″设置在嵌入式芯片30″的倾斜侧壁21″上。从而，可以使第一再分配层15′与第二再分配层15″相互接触(图14)。而且，可形成第二再分配层15″的一些部分，这些部分不接触第一再分配层15′，但它们却延伸到第一重构晶片20′上的工作表面12′。可以用现有技术中公知的淀积技术与光刻步骤来形成再分配层15′和15″。
在随后的步骤中，沿7′切割第一重构晶片20′，以形成主要的叠层芯片产品10′、10″，这些芯片包括两个再分配层15′和15″，而这些再分配层又将第一和第二芯片10′、10″互相连接在一起(图15)。
以下，将说明用于密封或封装上述叠层芯片40的任选步骤。提供了插入衬底或任意的其它载体50，并在载体50的上表面设置了粘合层51(图16)。将具有叠层芯片40的产品淀积到粘合层51上(图17)。连接线51与最下方的嵌入式芯片30′的工作表面12′上设置的接触垫52连接。可将接触垫52仅设置在第一重构晶片30′的工作表面12″上。由于不需将连接线连接到上部的嵌入式芯片30″，因而可将半导体器件的高度最小化(图18)。
为最后完成该半导体器件，用树脂54来覆盖叠层芯片10′、10″，和/或在插入衬底50处设置外部触点53(图19)。
与通过连接线51使第一和第二再分配层15′和15″接触不同，可以沿最下方的嵌入式芯片的倾斜侧壁来设置这些互连层，其中，上述互连层向下延伸，并到达第一嵌入式芯片30′的背侧13′所在的水平面。因此，必须以与形成嵌入式芯片30类似的方式(图8)来切割第一重构晶片20′，以便形成倾斜的侧壁。
本发明不限于两个芯片的叠层结构。图20示出了三个芯片30′、30″、30的叠层结构的例子。应当注意，从最上方的嵌入式芯片30开始，直到最下方的嵌入式芯片30′，直径不断增大。这便使再分配层15从最上方的嵌入式芯片30向下延伸至最下方的嵌入式芯片30′的工作表面12′成为可能。
尽管基于上述优选的典型实施例描述了本发明，但是，本发明不限于这些实施例，相反地，可以对这些实施例进行许多种修改。
特别地，在嵌入式芯片之间可设置一些附加结构。
附图标记
1中间载体
2粘合层
4间隙
d、d′、d″距离
5、5′、5″塑模
7开口
10、10′、10″、10芯片
11、11′、11″接触垫
12、12′、12″工作表面
13、13′、13″背侧
15′、15″、15再分配层
16′、16″粘合层
20、20′、20″基本、第一、第二重构晶片
21侧壁
30、30′、30″、30嵌入式芯片
51连接线
52接触垫
53外部触点
54树脂
100抛光方向
α角度
110、110′芯片
150插入机构
151、151′连接线
152、152′接触垫
153外部触点
160隔层
161、161′粘合层

Claims (8)

1.一种包括叠层芯片的半导体器件的生产方法包括以下步骤：
(a)形成第一重构晶片，该晶片包括以填充了塑模的第一间隙进行水平分隔的第一组多个芯片，其中，所述第一组多个芯片的接触垫设置在所述第一重构晶片的工作表面中；
(b)在所述第一重构晶片的所述工作表面上形成第一再分配层，所述第一再分配层接触所述第一组多个芯片的接触垫，并在所述塑模上延伸；
(c)形成第二重构晶片，该晶片包括通过填充了塑模的第二间隙进行水平分隔的第二组多个芯片，其中，所述第二组多个芯片的接触垫设置在与所述第二重构晶片的背侧相对的工作表面中；
(d)沿所述第二间隙切割所述第二重构晶片，以形成各个嵌入式芯片，这些芯片具有与所述第二重构晶片的工作表面成大于90度夹角的倾斜侧壁；
(e)将所述嵌入式芯片的背侧设置在所述第一重构晶片的工作表面与所述第一再分配层上；
(f)在所述嵌入式芯片的工作表面和倾斜侧壁上形成第二再分配层，所述第二再分配层连接了所述第二组多个芯片的接触垫和所述第一再分配层。
2.根据权利要求1所述的方法，其特征在于，在形成所述第二再分配层之后，沿所述第一间隙切割所述第一重构晶片，从而提供了互连的叠层芯片。
3.根据权利要求1或2所述的方法，其特征在于，在第三嵌入式芯片的工作表面上形成第三再分配层后，将第四嵌入式芯片的背侧设置在所述第三嵌入式芯片的工作表面上；并在所述第四嵌入式芯片的工作表面上形成第四再分配层。
4.根据权利要求3所述的方法，其特征在于，所述第三嵌入式芯片是所述第二嵌入式芯片，而所述第三再分配层是所述第二再分配层。
5.根据权利要求1-4所述的方法，其特征在于，所述第一间隙比所述第二间隙宽。
6.根据权利要求2-5所述的方法，其特征在于
(a)将所述互连的主要芯片产品设置在载体上；
(b)所述第一再分配层与所述载体上提供的接触区域接触。
7.根据权利要求6所述的方法，其特征在于，通过连接线来接触所述第一再分配层。
8.一种半导体器件，所述器件包含
至少第一芯片和第二芯片，其中，所述第一芯片具有与之水平邻接的第一塑模，所述第二芯片具有与之邻接的第二塑模，所述第二芯片设置在所述第一芯片的工作表面上，且至少所述第二塑模包含了倾斜的侧壁，而所述第一塑模具有比所述第二塑模更大的水平尺寸；
设置在所有芯片的工作表面上的再分配层，而这便将所述芯片的接触垫连接在一起，其中，所述再分配层沿所述倾斜侧壁分布；
具有接触区域的载体，且所述接触区域与所述再分配层在所述第一塑模的区域内相连。
CNB2006100928824A 2005-05-11 2006-05-11 包括叠层芯片的半导体器件生产方法及对应的半导体器件 Expired - Fee Related CN100517694C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/126392 2005-05-11
US11/126,392 US7208345B2 (en) 2005-05-11 2005-05-11 Method of manufacturing a semiconductor device comprising stacked chips and a corresponding semiconductor device

Publications (2)

Publication Number Publication Date
CN1913149A true CN1913149A (zh) 2007-02-14
CN100517694C CN100517694C (zh) 2009-07-22

Family

ID=37419665

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006100928824A Expired - Fee Related CN100517694C (zh) 2005-05-11 2006-05-11 包括叠层芯片的半导体器件生产方法及对应的半导体器件

Country Status (2)

Country Link
US (1) US7208345B2 (zh)
CN (1) CN100517694C (zh)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101499432B (zh) * 2008-02-01 2011-06-22 茂德科技股份有限公司 晶片堆叠结构及其堆叠方法
CN102110667A (zh) * 2010-12-23 2011-06-29 东南大学 一种进行圆片级电互连与引出的装置及其加工方法
US8349654B2 (en) 2006-12-28 2013-01-08 Tessera, Inc. Method of fabricating stacked packages with bridging traces
US8426957B2 (en) 2006-10-10 2013-04-23 Tessera, Inc. Edge connect wafer level stacking
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US8461672B2 (en) 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8466542B2 (en) 2009-03-13 2013-06-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
US8476774B2 (en) 2006-10-10 2013-07-02 Tessera, Inc. Off-chip VIAS in stacked chips
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
CN106876284A (zh) * 2015-12-10 2017-06-20 三星电子株式会社 半导体封装件及其制造方法
CN111725140A (zh) * 2020-07-01 2020-09-29 济南南知信息科技有限公司 一种多芯片封装及其制造方法

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
JP2006210402A (ja) * 2005-01-25 2006-08-10 Matsushita Electric Ind Co Ltd 半導体装置
US7442564B2 (en) * 2006-01-19 2008-10-28 Cree, Inc. Dispensed electrical interconnections
US7714450B2 (en) 2006-03-27 2010-05-11 Marvell International Technology Ltd. On-die bond wires system and method for enhancing routability of a redistribution layer
US20080116584A1 (en) * 2006-11-21 2008-05-22 Arkalgud Sitaram Self-aligned through vias for chip stacking
US8178982B2 (en) * 2006-12-30 2012-05-15 Stats Chippac Ltd. Dual molded multi-chip package system
US7687318B2 (en) 2007-05-04 2010-03-30 Stats Chippac, Ltd. Extended redistribution layers bumped wafer
JP5388422B2 (ja) * 2007-05-11 2014-01-15 スパンション エルエルシー 半導体装置及びその製造方法
US8723332B2 (en) * 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
WO2009035849A2 (en) 2007-09-10 2009-03-19 Vertical Circuits, Inc. Semiconductor die mount by conformal die coating
JP2009094432A (ja) * 2007-10-12 2009-04-30 Toshiba Corp 積層型半導体パッケージの製造方法
FR2923081B1 (fr) * 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
US20090160053A1 (en) * 2007-12-19 2009-06-25 Infineon Technologies Ag Method of manufacturing a semiconducotor device
KR101554761B1 (ko) 2008-03-12 2015-09-21 인벤사스 코포레이션 지지부에 실장되는 전기적으로 인터커넥트된 다이 조립체
US20090243069A1 (en) * 2008-03-26 2009-10-01 Zigmund Ramirez Camacho Integrated circuit package system with redistribution
US9059074B2 (en) * 2008-03-26 2015-06-16 Stats Chippac Ltd. Integrated circuit package system with planar interconnect
US7863159B2 (en) 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
KR100997787B1 (ko) * 2008-06-30 2010-12-02 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
KR101429722B1 (ko) * 2008-07-28 2014-09-25 삼성전자주식회사 적층된 칩들을 갖는 전자 장치 형성 방법
US9293385B2 (en) * 2008-07-30 2016-03-22 Stats Chippac Ltd. RDL patterning with package on package system
US8043894B2 (en) * 2008-08-26 2011-10-25 Stats Chippac Ltd. Integrated circuit package system with redistribution layer
US7910404B2 (en) * 2008-09-05 2011-03-22 Infineon Technologies Ag Method of manufacturing a stacked die module
JP5126002B2 (ja) 2008-11-11 2013-01-23 セイコーエプソン株式会社 半導体装置及び半導体装置の製造方法
US8471582B2 (en) * 2009-01-27 2013-06-25 Qualcomm Incorporated Circuit for detecting tier-to-tier couplings in stacked integrated circuit devices
US8003445B2 (en) * 2009-03-26 2011-08-23 Stats Chippac Ltd. Integrated circuit packaging system with z-interconnects having traces and method of manufacture thereof
US8680687B2 (en) 2009-06-26 2014-03-25 Invensas Corporation Electrical interconnect for die stacked in zig-zag configuration
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
TWI544604B (zh) 2009-11-04 2016-08-01 英維瑟斯公司 具有降低應力電互連的堆疊晶粒總成
US8304917B2 (en) * 2009-12-03 2012-11-06 Powertech Technology Inc. Multi-chip stacked package and its mother chip to save interposer
US8436707B2 (en) * 2010-01-12 2013-05-07 Infineon Technologies Ag System and method for integrated inductor
US8421226B2 (en) * 2010-02-25 2013-04-16 Infineon Technologies Ag Device including an encapsulated semiconductor chip and manufacturing method thereof
US8513771B2 (en) 2010-06-07 2013-08-20 Infineon Technologies Ag Semiconductor package with integrated inductor
US8796137B2 (en) 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect
US9721872B1 (en) 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
JP5289484B2 (ja) * 2011-03-04 2013-09-11 株式会社東芝 積層型半導体装置の製造方法
US10388584B2 (en) * 2011-09-06 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming Fo-WLCSP with recessed interconnect area in peripheral region of semiconductor die
WO2013057867A1 (ja) * 2011-10-21 2013-04-25 パナソニック株式会社 半導体装置
US20130154106A1 (en) 2011-12-14 2013-06-20 Broadcom Corporation Stacked Packaging Using Reconstituted Wafers
US9548251B2 (en) 2012-01-12 2017-01-17 Broadcom Corporation Semiconductor interposer having a cavity for intra-interposer die
US20130187284A1 (en) 2012-01-24 2013-07-25 Broadcom Corporation Low Cost and High Performance Flip Chip Package
US8587132B2 (en) 2012-02-21 2013-11-19 Broadcom Corporation Semiconductor package including an organic substrate and interposer having through-semiconductor vias
US8558395B2 (en) 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias
US8872321B2 (en) 2012-02-24 2014-10-28 Broadcom Corporation Semiconductor packages with integrated heat spreaders
US9275976B2 (en) 2012-02-24 2016-03-01 Broadcom Corporation System-in-package with integrated socket
US8749072B2 (en) 2012-02-24 2014-06-10 Broadcom Corporation Semiconductor package with integrated selectively conductive film interposer
US8928128B2 (en) 2012-02-27 2015-01-06 Broadcom Corporation Semiconductor package with integrated electromagnetic shielding
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR102001880B1 (ko) * 2013-06-11 2019-07-19 에스케이하이닉스 주식회사 적층 패키지 및 제조 방법
KR101538541B1 (ko) * 2013-07-16 2015-07-22 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US10206288B2 (en) 2015-08-13 2019-02-12 Palo Alto Research Center Incorporated Bare die integration with printed components on flexible substrate
US10165677B2 (en) 2015-12-10 2018-12-25 Palo Alto Research Center Incorporated Bare die integration with printed components on flexible substrate without laser cut
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US10847384B2 (en) 2017-05-31 2020-11-24 Palo Alto Research Center Incorporated Method and fixture for chip attachment to physical objects
US11158607B2 (en) * 2018-11-29 2021-10-26 Apple Inc. Wafer reconstitution and die-stitching
US11024604B2 (en) 2019-08-10 2021-06-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11515225B2 (en) 2020-09-10 2022-11-29 Rockwell Collins, Inc. Reconstituted wafer including mold material with recessed conductive feature
US11605570B2 (en) 2020-09-10 2023-03-14 Rockwell Collins, Inc. Reconstituted wafer including integrated circuit die mechanically interlocked with mold material

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USH208H (en) * 1984-02-17 1987-02-03 At&T Bell Laboratories Packaging microminiature devices
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6472758B1 (en) * 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US9899353B2 (en) 2006-10-10 2018-02-20 Tessera, Inc. Off-chip vias in stacked chips
US8426957B2 (en) 2006-10-10 2013-04-23 Tessera, Inc. Edge connect wafer level stacking
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US9378967B2 (en) 2006-10-10 2016-06-28 Tessera, Inc. Method of making a stacked microelectronic package
US8461673B2 (en) 2006-10-10 2013-06-11 Tessera, Inc. Edge connect wafer level stacking
US9048234B2 (en) 2006-10-10 2015-06-02 Tessera, Inc. Off-chip vias in stacked chips
US8476774B2 (en) 2006-10-10 2013-07-02 Tessera, Inc. Off-chip VIAS in stacked chips
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8349654B2 (en) 2006-12-28 2013-01-08 Tessera, Inc. Method of fabricating stacked packages with bridging traces
US8461672B2 (en) 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
CN101809739B (zh) * 2007-07-27 2014-08-20 泰塞拉公司 具有后应用的衬垫延长部分的重构晶片堆封装
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
CN101499432B (zh) * 2008-02-01 2011-06-22 茂德科技股份有限公司 晶片堆叠结构及其堆叠方法
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8466542B2 (en) 2009-03-13 2013-06-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
CN102110667A (zh) * 2010-12-23 2011-06-29 东南大学 一种进行圆片级电互连与引出的装置及其加工方法
CN106876284A (zh) * 2015-12-10 2017-06-20 三星电子株式会社 半导体封装件及其制造方法
CN106876284B (zh) * 2015-12-10 2021-10-22 三星电子株式会社 半导体封装件及其制造方法
CN111725140A (zh) * 2020-07-01 2020-09-29 济南南知信息科技有限公司 一种多芯片封装及其制造方法
CN111725140B (zh) * 2020-07-01 2022-06-07 中山市优帝智能科技有限公司 一种多芯片封装及其制造方法

Also Published As

Publication number Publication date
US7208345B2 (en) 2007-04-24
CN100517694C (zh) 2009-07-22
US20060258044A1 (en) 2006-11-16

Similar Documents

Publication Publication Date Title
CN1913149A (zh) 包括叠层芯片的半导体器件生产方法及对应的半导体器件
CN1151554C (zh) 半导体器件、其制造方法以及组合型半导体器件
CN1093318C (zh) 半导体装置及其制造方法
CN1320644C (zh) 晶片级封装、多封装叠层、及其制造方法
CN1099711C (zh) 半导体器件及其制造方法
CN1783447A (zh) 制造具有外部接触连接的半导体元件的方法
CN1885536A (zh) 半导体封装
CN1716601A (zh) 半导体器件和半导体晶片及其制造方法
CN101079372A (zh) 基板处理方法和半导体装置的制造方法
CN1734764A (zh) 具有预防裂痕的环状结构的半导体装置及其制造方法
CN1155067C (zh) 半导体器件的生产方法
CN1897240A (zh) 多芯片器件及其制造方法
CN1453847A (zh) 半导体装置及其制造方法、电路基片和电子仪器
CN101809739A (zh) 具有后应用的衬垫延长部分的重构晶片堆封装
CN1187812C (zh) 半导体器件、半导体器件的制造方法和半导体器件的设计方法
US10083941B2 (en) Stacked semiconductor dies with selective capillary under fill
CN1747630A (zh) 基板制造方法和电路板
CN1929130A (zh) 多芯片堆叠式封装结构
CN1319890A (zh) 半导体器件和使用该半导体器件的半导体组件
CN1538520A (zh) 半导体封装和制造方法
CN1168133C (zh) 半导体晶片、半导体器件及其制造方法
US7687919B2 (en) Integrated circuit package system with arched pedestal
CN1624912A (zh) 器件封装件和印刷电路板及电子装置
CN1550041A (zh) 位于透明基片上的彩色图像传感器及其制造方法
CN1231959C (zh) 产生金属层虚拟图案的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
C56 Change in the name or address of the patentee
CP01 Change in the name or title of a patent holder

Address after: Munich, Germany

Patentee after: Infineon Technologies AG

Address before: Munich, Germany

Patentee before: Infineon Technologies AG

TR01 Transfer of patent right

Effective date of registration: 20120917

Address after: Munich, Germany

Patentee after: QIMONDA AG

Address before: Munich, Germany

Patentee before: Infineon Technologies AG

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20151224

Address after: German Berg, Laura Ibiza

Patentee after: Infineon Technologies AG

Address before: Munich, Germany

Patentee before: QIMONDA AG

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090722

Termination date: 20170511

CF01 Termination of patent right due to non-payment of annual fee