CN1151554C - 半导体器件、其制造方法以及组合型半导体器件 - Google Patents
半导体器件、其制造方法以及组合型半导体器件 Download PDFInfo
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Abstract
一种树脂密封型半导体器件、其制造方法和封装结构能够减小半导体器件的尺寸并获得高密度封装。为此,具有暴露在外表面的引线的树脂密封型半导体器件备有点引线,所述点引线借助于夹在其间的绝缘胶粘带而粘附到半导体元件的电路形成面、各自独立地规则排列并且暴露到外面,而所述半导体元件被设置在里面。
Description
技术领域
本发明涉及树脂密封型半导体器件、其制造方法以及其封装结构。
背景技术
在最近几年,随着IC卡和存储卡的快速进步,已经要求把安装在所述卡中的树脂密封型半导体器件做得更薄。响应这种需求,已经提出了许多把所述半导体器件减薄的方法。
这些建议中的一个涉及这样一种结构,其中,如在日本专利申请第6-273262号中所公开的,芯片座的上表面和半导体元件的下表面是曝露的。根据这种结构,可以把封装的总厚度调整到大约0.5毫米。
此外,如日本专利公开公告第5-309983号(日本专利申请第4-119133号)中所公开的,通过把引线弯成L形来实现减小封装面积的技术。
但是,在上述先有技术的树脂封装型半导体器件中,即使封装变薄了,封装面积仍然未变。就是说,引线伸出到模制树脂外面很长,因此,在印刷电路板上的封装面积与半导体元件的面积相比显著地大了。对于实现高密度封装来说,这种结构是不够的。
发明内容
本发明的目的在于减小树脂密封型半导体器件的尺寸和实现高密度封装,以及消除上述问题。
本发明提供了一种半导体器件,其特征在于包括:形成半导体电路的半导体元件;包括设置在与所述半导体电路一起形成的表面上的绝缘胶粘带的绝缘层;固定在上述绝缘胶粘带上的多个点引线,它们各自在电气上是独立的并且被规则地排列在所述绝缘层上,它们的表面曝露在外部;至少在所述绝缘层和所述半导体元件的侧面上形成的模制树脂部分;金属隆起物,它设置在所述点引线和与所述半导体电路一起形成的表面之间的、不具备所述绝缘层的部分上,用于实现半导体芯片和点引线的电连接。
优选地,所述点引线的至少曝露在外部的表面镀有金属镀层。
在所述绝缘层上设置支持部分,该支持部分包括与所述点引线的相同的构件、但是是独立于所述点引线的。其中,可以通过切断从所述点引线延续形成的引线框而使所述点引线和所述支持部分彼此独立。
所述点引线包含延伸引线并且在电气上通过在所述延伸引线的前端或者中间部分的所述金属隆起物而连接到所述半导体元件。
本发明还提供了一种制造树脂密封型半导体器件的方法,所述半导体器件包括半导体元件、绝缘层、点引线、金属隆起物和模制树脂部分,所述方法依次包括以下步骤:制备引线框架的步骤,所述引线框架包括框构件、分隔构件、连接分隔构件的支架及从分隔构件向内延伸的多个引线;在所述多个引线的前端镀金属镀层;进行热压配合,将引线粘附到胶粘带上;将引线与胶粘带之间的非接触部分,即分隔构件和引线前端之间的部分冲断,形成引线的外部连接端;将半导体元件粘附到胶粘带的另一面;在没有胶粘带的区域设置金属隆起物来实现半导体元件和点引线的电连接;用模制树脂对上述半导体器件进行密封;其特征在于所述的进行热压配合将引线粘附到胶粘带上的步骤还包括以下步骤:(a)利用绝缘胶粘带把引线框中的支持部分固定地粘附到所述绝缘层上并且独立于所述点引线,以及(b)把所述多个点引线与所述引线框分开。
其中,所述利用绝缘胶粘带把引线框中的支持部分固定地粘附到所述绝缘层上的步骤是利用绝缘胶粘带固定地粘附引线框中的所述绝缘层的具有多个点引线的一个面,并且独立于所述点引线;和把半导体元件粘附到所述胶粘带的另一面并用树脂密封所述半导体元件;以及所述把所述多个点引线与所述引线框分开的步骤包括:把所述多个点引线与所述引线框分开,并且把所述点引线的前缘从所述半导体元件的侧面部分的外面向下弯曲成为L形,以及在所述点引线和与所述半导体电路一起形成的表面之间的、不具备所述绝缘层的部分上设置金属隆起物。
本发明又提供了一种半导体器件,其特征在于包括:形成半导体电路的半导体元件,包括设置在与所述半导体电路一起形成的表面上的绝缘胶粘带的绝缘层,在电气上各自独立的并规则地排列在所述绝缘层上的多个点引线,所述多个点引线的表面曝露在外部、并且它们的前端从所述半导体元件的侧面部分的外面向下延伸成为L形,金属隆起物,它设置在所述点引线和与所述半导体电路一起形成的表面之间的、不具备所述绝缘层的部分上,以及至少在所述绝缘层和所述半导体元件的侧面形成模制树脂部分。
本发明提供了一种封装多个半导体器件的方法,其特征在于包括以下步骤:以并排的关系设置多个具有若干L形引线的半导体器件,所述引线从模制树脂部分中半导体元件的上表面曝露到外部,同时,它们的前端从该半导体元件的侧面部分的外面向下延伸,并且,所述L形引线彼此连接,以及把所述L形引线的连接部分连接到设置在接线板上的同一个支点图案上。
本发明还提供了一种组合型半导体器件,其特征在于包括:多个具有若干L形引线的半导体器件,所述引线从模制树脂部分中半导体元件的上表面曝露到外部,同时,它们的前端从所述半导体元件的侧面部分的外面向下延伸,其中,所述多个半导体器件以面对面的关系配置,使得所述L形引线的前端彼此相对,并且所述L形引线彼此连接;其中,在所述多个半导体器件中,各树脂封装分别是模制树脂封装,并且,用粘合剂把所述树脂封装的下表面彼此固定在一起。
本发明还提供了一种组合型半导体器件,其特征在于包括:多个具有若干L形引线的半导体器件,所述引线从模制树脂部分中半导体元件的上表面曝露到外部,同时,它们的前端从所述半导体元件的侧面部分的外面向下延伸,其中,把所述多个半导体器件以这样的方式层叠,使得所述L形引线的前端以彼此相同的方向排列;在所述多个层叠的半导体器件中,所述上层半导体器件的所述L形引线的前端连接到所述下层半导体器件的所述L形引线的弯曲部分;在所述多个半导体器件中,各树脂封装分别是模制树脂封装,并且,利用粘合剂把所述上层半导体器件的树脂封装的下表面固定到所述下层半导体器件的树脂封装的上表面。
基于这种结构,就有可能减小树脂封装型半导体器件的尺寸并且实现其高密度封装。其中与半导体元件的连接不但涉及金属隆起物的应用,而且涉及绝缘胶粘带的应用,从而消除由热膨胀的差别引起的所述金属隆起物上的应力。因此,有可能避免出现以下情况:由于金属隆起物的破裂等等而使电气性能变坏或者下降。
在所述点引线的曝露的外表面镀有金属镀层。这种金属镀层可以镀在与所述曝露的外表面相对的表面上,即,半导体元件一侧的表面上,但不应当镀在点此线的侧面上。更具体地说,在形成于所述侧面上的、具有模压树脂部分的接触部分上不镀金属镀层,从而有可能避免模压之后树脂的破裂。可以在不必非常依赖于用来形成电路的结区的位置的情况下,在半导体元件上以阵列的形式形成所述外部接线端子(点引线)。
用本发明的这种方法形成所述支持部分,并且可以加固所述半导体器件的结构,从而可以得到坚固的和高可靠的半导体器件。可以利用引线框架而同时形成所述点引线和支持部分,因此,用较少的工艺步骤得到结构上加固的半导体器件。
由于所述支持部分和点引线是同时形成的,所以可以提高生产线效率。在电镀之后,利用绝缘胶粘带把所述点引线固定地粘附,并且此后使它穿孔(开孔)伸出。因此,点引线被固定在模标位置,并且具有预定的尺寸。此外,预先进行了金属电镀,因此,往后甚至在组装半导体器件时都不需要再电镀。此外,所述半导体元件被胶粘带稳定地支持住,并且,借助于所述支持部分能够得到坚固的树脂密封型半导体器件。
这样,L形引线沿着半导体元件的侧面曝露在外侧,因此,有可能提高用来把所述外部接线端子连接到印刷电路板的支点图案上的焊点的结合强度。
在本发明的方案中,不是在加工形成引线框之后进行模制树脂密封来形成所述点引线的,而是在组装所述半导体器件的模制树脂密封步骤之后对所述此线框进行加工处理来形成所述点引线的。因此,有可能制造能够高密度封装的树脂密封型半导体器件。并且,可以把两根L形引线一起连接到同一个印刷线路板的支点图案上。
上面的树脂密封型半导体器件倒置地层叠在封装在所述线路板上的下面的树脂密封型半导体器件上,并且,各个树脂密封型半导体器件的L形引线的前端被连接。因上级可能在所述线路板上获得高密度的封装。
利用粘合剂把上面的和下面的树脂密封型半导体器件的下表面彼此固定在一起,因此,能够得到坚固的紧凑的组合型半导体器件。
根据本发明的组合型半导体器件的结构,制备多个具有若干L形引线的半导体器件,所述引线从模制树脂部分中半导体元件的上表面曝露到外部,同时,它们的前端从该半导体元件的侧面部分的外面向下延伸。然后,把所述多个半导体器件这样层叠在一起,使得所述L形引线具有彼此相同的方向。即,上面的半导体器件也以相同的方向层叠在下面的半导体器件上。按照相同的方向进行更多次的层叠,将得到具有更多层次的组合型半导体器件。例如,通过再层叠一个树脂密封型半导体器件而把所述半导体器件叠加成三层的形式,并且,连接共L形引线,从而有可能在所述线路板上得到更高密度的封装。
把上层半导体器件按照相同的方向层叠在封装在所述线路板上的下层半导体器件上,并且,各个半导体器件的L形引线的前端和弯曲部分被彼此连接。因此,通过按照相同的方向顺序地层叠所述树脂密封型半导体器件,就能够简单地在所述线路板上获得更高密度的封装。利用所述粘合剂把上面的和下面的半导体器件彼此固定在一起,从而能够得到坚固的紧凑的半导体器件。
在以下结合附图的讨论中,将明白本发明的其它目的和优点。
附图说明
图1是说明本发明第一实施例的树脂密封型半导体器件的剖面图;
图2是说明本发明第一实施例的树脂密封型半导体器件的局部透视图。
图3是说明本发明第一实施例的修改的实施例的树脂密封型半导体器件的剖面图;
图4是说明本发明第一实施例的修改的实施例的树脂密封型半导体器件的局部透视图;
图5是说明树脂密封型半导体器件中固有的问题的说明性示意图;
图6是说明在本发明第一实施例中制造引线框的步骤的平面图;
图7是说明本发明第一实施例的第二个修改的实施例的树脂密封型半导体器件的主要部分的透视图;
图8是说明本发明第二实施例的树脂密封型半导体器件的剖面图;
图9是说明本发明第二实施例的修改的实施例的树脂密封型半导体器件的剖面图;
图10是说明本发明第二实施例的修改的实施例的树脂密封型半导体器件的局部透视图;
图11是说明本发明第二实施例的第一个应用实施例的剖面图;
图12是说明本发明第二实施例的第二个应用实施例的剖面图;
图13是说明本发明第二实施例的第三个应用实施例的剖面图;
图14是说明本发明第二实施例的第四个应用实施例的剖面图;
具体实施方式
下面将参考附图详细讨论本发明的实施例。
图1是说明本发明第一实施例的树脂密封型半导体器件的剖面图。图2是树脂密封型半导体器件的局透视图。
如图1和2中所示,把点引线7和半导体元件支架4一起粘附到绝缘胶粘带(简称为“胶粘带”)2的一个面上。此外,把半导体元件1粘附到胶粘带2的另一面,把半导体元件1的电路形成面设置成与所述点引线具有面对面的关系。
通过设置在没有胶粘带2这个介物的区域的金属隆起物9来实现半导体元件1和点引线7的电连接。金属隆起物9包括诸如合金焊料等等的导电金属,并且设置在形成于半导体元件1的侧面的未示出的电极表面上。
点引线7镀有作为外部接线端(图中的上表面)和内部接点(图中的下表面)的金属镀层8。应当指出,所述点引线的侧面可以不镀金属镀层。
至少点引线7、支架4和半导体元件1的外侧部分和下面部分被用模制树脂6密封。
顺便说说,本实施例的上述点引线7被规则地排列在半导体元件1的区域内、即、半导体元件1的宽度范围内。
此外,金属隆起物9的高度基本上与胶粘带2厚度相同。
由此可见,所述半导体器件的厚度是半导体元件1的厚度、金属隆起物9的高度以及点引线7的厚度之和。此外,根据本实施例,构成外部接线端的所述点引线基本上与所述半导体器件的表面齐平。
更具体地说,所述半导体器件薄到0.4-0.5毫米,其中,点引线7的厚度是大约0.125毫米、金属隆起物9的高度是0.5毫米以及半导体元件1的厚度是0.250毫米。此外,半导体元件1能够适应各种结构构件。还有,点引线7与半导体元件1之间的连接不但涉及金属隆起物9的应用,而且涉及绝缘胶粘带2的应用,从而消除由热膨胀的差别引起的所述金属隆起物9上的应力。因此,有可能避免出现以下情况:由于金属隆起物9的破裂等等而使电气性能变坏或者下降。
此外,图1和2中描绘的结构是这样的:支架4沿着图2中的前后方向伸展、贯穿该半导体器件的中心部分,因此,能够实现竖固的封装结构。
顺便说说,所述半导体元件支架在提高半导体器件的刚性方面是有效的,但是并不是必不可少的。当然,也可以利用如图3和4中所示的去掉支架4的树脂密封型半导体器件。
此外,如图5中所示,点引线7和模制树脂6在热膨胀系数方面是不同的,因此,当用模制树脂6密封之后恢复到正常温度时,在各个边界之间形成缝隙101。此外,可以估计,这可能发展成为裂缝102。然后,如图1和3中所示,这些边界处的紧密接触特性的增强可能这样的接合,使得点引线7的侧面不与作为外部接线端和内部接点的金属镀层8接触。这是由于金属镀层8导致与模制树脂6的紧密接触的退化。然后,模制树脂6和金属镀层8之间的接触面被分离。
使用这种结构,由于不存在模制树脂6和金属镀层8之间的接触,所以,能够避免模制之后所述模制树脂的破裂等等。
图6(A)和6(b)是说明制造本发明的第一实施例的引线框的步骤的平面图。图6(A)是说明被切断之前的引线框的平面图。图6(b)是说明被切断之后的引线框的平面图。
首先,如图6(a)中所示,制备引线框10,它包括:框构件10a;分隔构件10b;用来连接框构件10a的支架4;以及多个从分隔构件10b向内延伸的引线7A。所述多个引线7A的前端镀有金属镀层8,并且此后这样进行热压配合,以便把它粘附到胶粘带2上。
此后,如图6(B)中所示,指导引线7A和胶粘带2之间非接触部分,即,分隔构件10b和引线7A的前端之间的部分冲断(punched out),这样,最后形成点引线7。即,以这样的尺寸进行所述冲断,使得点引线7成为外部接线端。这样冲断的点引线7被固定在胶粘带2上,并且,所述处理过程直接进入该半导体器件的组装步骤。
如上所述,根据第一实施例,在电镀了金属镀层8之后,所述多个引线被用胶粘带2固定住,接着,为了把所述部分冲断而形成点引线7,把点引线按照预定的尺寸固定在目标位置。此外,由于预先进行了金属电镀,所以,往后甚至在组装该半导体器件的步骤中都不需要再进行金属电镀。
下面将说明本发明的第一实施例的第二个修改的实施例。
图7是说明本发明第一实施例的第二个修改的实施例的树脂密封型半导体器件的主要部分的透视图。
参考图7,图中未出模制树脂6、点引线7、延伸引线7-1、电镀在点引线7上和延伸引线7-1的表面上的金属镀层8、以及金属隆起物9。
在第一实施例中,将点引线7排列,并且相应地焊接到印刷电路板(未示出)的支点图案上(未示出)。半导体元件1的结区处在与点引线7相同的位置上,这意味着所述半导体没有自由度,并且在形成电路方面可能受到约束。因此,根据本实施例,即使该半导体元件上的结区在排列方向有一定程度的偏移,也可以借助于延伸引线7-1来排列点引线7的外部接线端。
即,作为外部接线端的点引线7备有延伸引线7-1,后者作为延伸的导线延伸到半导体元件上的结区,金属隆起物9连接到延伸引线7-1的前端。
因此,可以在不非常依赖于半导体元件上用来形成电路的结区的位置的情况下以阵列的表式形成所述外部接线端。
下面将描述本发明的第二实施例。
图8是说明本发明第二实施例的树脂密封型半导体器件的剖面图。
如图中所示,虽然所述结构基本上与第一实施例的相同,但是,上述点引线被露出,直至半导体元件1的侧面,并且把L形引线12弯曲成L形。
因此,与第一实施例不同,所述点引线的形成过程是这样的;不是在加工形成引线框之后进行模制树脂密封,而是在组装半导体器件的模制树脂密封步骤之后加工形成所述引线。
这样,L形引线12被露出、直至半导体元件1的侧面,因此能够增强用来把外部接线端子连接到犯刷电路板(未示出)的支点图案(未示出)的焊点的接合强度。
顺便说说,当然可以在省去图8中所示的支架4的情况下构成所述树脂密封型半导体器件。
图10是说明树脂密封型半导体器件的主要部分的透视图,所述树脂密封型半导体器件是这样构成的,使得图9中所示的半导体元件支架被省去,其中,镀有金属镀层8的L形引线排列在用来密封半导体元件的模制树脂6的两侧。
图1是说明本发明第二实施例的第一个应用实施例的剖面图。
根据第二实施例中所示的用模制树脂6密封的树脂密封型半导体器件,由于L形引线12存在于侧面,所以,可以把彼此相邻的树脂密封型半导体器件B的L形引线12b和树脂密封型半导体器件A的L形引线12a相互连接。
此外,可以通过焊点14把L形引线12a和L形引线12b一起连接到同一块印刷电路板13上的支点图案15。即,可以把L形引线12a和L形引线12b共用于同一个支点图案15上。可以在许多作为存储器的半导体器件的场合看到这种连接方法,其中,彼此相邻的半导体元件的电路是以反向的形式形成的,并且端子的输入/输出也是反向的。
这样,在树脂密封型半导体器件的侧面上形成L形引线12,因此,有可能在同一块印刷电路板13上以串联的形式紧凑地封装所述树脂密封型半导体器件。
此外,可以简化印刷电路板上的布线。
图12是说明本发明第二实施例的第二个应用实施例的剖面图。
根据本发明的第二实施例中所示的用模制树脂6密封的树脂密封型半导体器件,L形引线12沿着侧面一直延伸到相反的一面,因此,如图12中所示,如果所述树脂密封型半导体器件是反向的(使其底面彼此相对)并且被层叠成两层,那么,通过焊点14把树脂密封型半导体器件B的L形引线12a的前端固定到树脂密封型半导体器件A的L形引线12b的前端。树脂密封型半导体器件A的L形引线12a的前端也通过焊点14固定到树脂密封型半导体器件B的L形引线12b的前端。此外,所述半导体器件(树脂封装)的底面用粘合剂16彼此固定在一起。
这样,L形引线沿着所述树脂封装的侧面向外延伸直至所述底面,使得树脂密封型半导体器件A和与它反向的树脂密封型半导体器件B的各个L形引线12的前端可以通过焊点彼此连接。此外,所述半导体元件的底面用粘合剂16彼此固定在一起,因此,能够提高凶刷电路板13上的封装密度。
应当指出,这里使用的树脂密封型半导体器件在各个半导体元件1的电路结构方面以及端子的输入/输出方面是反相的。
图13是说明本发明第二实施例的第三个应用实施例的剖面图。
根据该第三个应用实施例,如图13中所示,在图12中所示的上述两层上再层叠一层而形成三层的结构。更具体地说,把作为第三层的树脂密封型半导体器件C按照与第一层的相同的方向层叠在作为第二层的树脂密封型半导体器件B上,其中,把各个L形引线12连接在一起。
这样,根据本发明第二实施例的树脂密封型半导体器件被层叠成三层的形式,因此,能够更进一步地提高印刷电路板13上的封装密度。
可以进一步增加层的数目,例如,增加到四层、五层等等。
图14是说明本发明第二实施例的第四个应用实施例的剖面图。
由于L形引线12沿着所述树脂封装的侧面向外延伸、直至底面附近的部分,所以,如图14中所示,可以把本发明的第二实篱例中所示的用模制树脂6密封的树脂密封型半导体器件按照相同的向上的方向层叠。更具体地说,树脂密封型半导体器件A被封装在印刷电路板13上,并且,树脂密封型半导体器件B按照相同方向层叠其上。然后,通过在L形引线12的前端和L形变曲部分处的焊点14,把树脂密封型半导体器件A的L形引线12a连接到树脂密封型半导体器件B的L形引线12a。同样,把树脂密封型半导体器件A的L形引线12b连接到树脂密封型半导体器件B的L形引线12b。此外,用粘合剂16把树脂密封型半导体器件A和B彼此固定在一起。
因此,能够提高印刷电路板13上的封装密度。在许多具有完全相同的电路结构元件的可以层叠成多层结构的半导体存储器的场合,可以看到这样连接方法。
应当指出,本发明不限于上述实施例,而是可以用基于本发明的要点的各种各样的方法修改,这些修改并不被排除在本发明的范围之外。
Claims (11)
1.一种半导体器件,其特征在于包括:
形成半导体电路的半导体元件;
包括设置在与所述半导体电路一起形成的表面上的绝缘胶粘带的绝缘层;
固定在上述绝缘胶粘带上的多个点引线,它们各自在电气上是独立的并且被规则地排列在所述绝缘层上,它们的表面曝露在外部;
至少在所述绝缘层和所述半导体元件的侧面上形成的模制树脂部分;
金属隆起物,它设置在所述点引线和与所述半导体电路一起形成的表面之间的、不具备所述绝缘层的部分上,用于实现半导体芯片和点引线的电连接。
2.根据权利要求1的半导体器件,其特征在于:
所述点引线的至少曝露在外部的表面镀有金属镀层。
3.根据权利要求1的半导体器件,其特征在于:
在所述绝缘层上设置支持部分,该支持部分包括与所述点引线的相同的构件、但是是独立于所述点引线的。
4.根据权利要求3的半导体器件,其特征在于:
通过切断从所述点引线延续形成的引线框而使所述点引线和所述支持部分彼此独立。
5.根据权利要求1的半导体器件,其特征在于:
所述点引线包含延伸引线并且在电气上通过在所述延伸引线的前端或者中间部分的所述金属隆起物而连接到所述半导体元件。
6.一种制造树脂密封型半导体器件的方法,所述半导体器件包括半导体元件、绝缘层、点引线、金属隆起物和模制树脂部分,所述方法依次包括以下步骤:
制备引线框架的步骤,所述引线框架包括框构件、分隔构件、连接分隔构件的支架及从分隔构件向内延伸的多个引线;
在所述多个引线的前端镀金属镀层;
进行热压配合,将引线粘附到胶粘带上;
将引线与胶粘带之间的非接触部分,即分隔构件和引线前端之间的部分冲断,形成引线的外部连接端;
将半导体元件粘附到胶粘带的另一面;
在没有胶粘带的区域设置金属隆起物来实现半导体元件和点引线的电连接;
用模制树脂对上述半导体器件进行密封;
其特征在于所述的进行热压配合将引线粘附到胶粘带上的步骤还包括以下步骤:
(a)利用绝缘胶粘带把引线框中的支持部分固定地粘附到所述绝缘层上并且独立于所述点引线,以及
(b)把所述多个点引线与所述引线框分开。
7.根据权利要求6的制造半导体器件的方法,其特征在于:
所述利用绝缘胶粘带把引线框中的支持部分固定地粘附到所述绝缘层上的步骤是利用绝缘胶粘带固定地粘附引线框中的所述绝缘层的具有多个点引线的一个面,并且独立于所述点引线;和把半导体元件粘附到所述胶粘带的另一面并用树脂密封所述半导体元件,以及
所述把所述多个点引线与所述引线框分开的步骤包括:把所述多个点引线与所述引线框分开,并且把所述点引线的前缘从所述半导体元件的侧面部分的外面向下弯曲成为L形,以及在所述点引线和与所述半导体电路一起形成的表面之间的、不具备所述绝缘层的部分上设置金属隆起物。
8.一种半导体器件,其特征在于包括:
形成半导体电路的半导体元件,
包括设置在与所述半导体电路一起形成的表面上的绝缘胶粘带的绝缘层,
在电气上各自独立的并规则地排列在所述绝缘层上的多个点引线,所述多个点引线的表面曝露在外部、并且它们的前端从所述半导体元件的侧面部分的外面向下延伸成为L形,
金属隆起物,它设置在所述点引线和与所述半导体电路一起形成的表面之间的、不具备所述绝缘层的部分上,以及
至少在所述绝缘层和所述半导体元件的侧面形成模制树脂部分。
9.封装多个半导体器件的方法,其特征在于包括以下步骤:
以并排的关系设置多个具有若干L形引线的半导体器件,所述引线从模制树脂部分中半导体元件的上表面曝露到外部,同时,它们的前端从该半导体元件的侧面部分的外面向下延伸,并且,所述L形引线彼此连接,以及
把所述L形引线的连接部分连接到设置在接线板上的同一个支点图案上。
10.一种组合型半导体器件,其特征在于包括:
多个具有若干L形引线的半导体器件,所述引线从模制树脂部分中半导体元件的上表面曝露到外部,同时,它们的前端从所述半导体元件的侧面部分的外面向下延伸,
其中,所述多个半导体器件以面对面的关系配置,使得所述L形引线的前端彼此相对,并且所述L形引线彼此连接;
其中,在所述多个半导体器件中,各树脂封装分别是模制树脂封装,并且,用粘合剂把所述树脂封装的下表面彼此固定在一起。
11.一种组合型半导体器件,其特征在于包括:
多个具有若干L形引线的半导体器件,所述引线从模制树脂部分中半导体元件的上表面曝露到外部,同时,它们的前端从所述半导体元件的侧面部分的外面向下延伸,
其中,把所述多个半导体器件以这样的方式层叠,使得所述L形引线的前端以彼此相同的方向排列;
在所述多个层叠的半导体器件中,所述上层半导体器件的所述L形引线的前端连接到所述下层半导体器件的所述L形引线的弯曲部分;
在所述多个半导体器件中,各树脂封装分别是模制树脂封装,并且,利用粘合剂把所述上层半导体器件的树脂封装的下表面固定到所述下层半导体器件的树脂封装的上表面。
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Families Citing this family (84)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3881751B2 (ja) * | 1997-08-20 | 2007-02-14 | 沖電気工業株式会社 | 半導体チップの実装構造および実装方法 |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
KR100304959B1 (ko) * | 1998-10-21 | 2001-09-24 | 김영환 | 칩 적층형 반도체 패키지 및 그 제조방법 |
US6853086B1 (en) * | 1998-10-30 | 2005-02-08 | Seiko Epson Corporation | Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument |
KR20010037247A (ko) * | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | 반도체패키지 |
KR100421774B1 (ko) * | 1999-12-16 | 2004-03-10 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조 방법 |
US6404046B1 (en) * | 2000-02-03 | 2002-06-11 | Amkor Technology, Inc. | Module of stacked integrated circuit packages including an interposer |
US7042068B2 (en) | 2000-04-27 | 2006-05-09 | Amkor Technology, Inc. | Leadframe and semiconductor package made using the leadframe |
US6576494B1 (en) * | 2000-06-28 | 2003-06-10 | Micron Technology, Inc. | Recessed encapsulated microelectronic devices and methods for formation |
US6545345B1 (en) | 2001-03-20 | 2003-04-08 | Amkor Technology, Inc. | Mounting for a package containing a chip |
KR100369393B1 (ko) * | 2001-03-27 | 2003-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드프레임 및 이를 이용한 반도체패키지와 그 제조 방법 |
KR100393448B1 (ko) * | 2001-03-27 | 2003-08-02 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
US6597059B1 (en) | 2001-04-04 | 2003-07-22 | Amkor Technology, Inc. | Thermally enhanced chip scale lead on chip semiconductor package |
SG111919A1 (en) * | 2001-08-29 | 2005-06-29 | Micron Technology Inc | Packaged microelectronic devices and methods of forming same |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
SG120879A1 (en) * | 2002-08-08 | 2006-04-26 | Micron Technology Inc | Packaged microelectronic components |
US7723210B2 (en) | 2002-11-08 | 2010-05-25 | Amkor Technology, Inc. | Direct-write wafer level chip scale package |
US6905914B1 (en) | 2002-11-08 | 2005-06-14 | Amkor Technology, Inc. | Wafer level package and fabrication method |
SG114585A1 (en) * | 2002-11-22 | 2005-09-28 | Micron Technology Inc | Packaged microelectronic component assemblies |
AU2003291199A1 (en) * | 2002-12-09 | 2004-06-30 | Advanced Interconnect Technologies Limited | Package having exposed integrated circuit device |
US6798047B1 (en) | 2002-12-26 | 2004-09-28 | Amkor Technology, Inc. | Pre-molded leadframe |
US6750545B1 (en) | 2003-02-28 | 2004-06-15 | Amkor Technology, Inc. | Semiconductor package capable of die stacking |
US6794740B1 (en) | 2003-03-13 | 2004-09-21 | Amkor Technology, Inc. | Leadframe package for semiconductor devices |
US7368810B2 (en) * | 2003-08-29 | 2008-05-06 | Micron Technology, Inc. | Invertible microfeature device packages |
DE102004012979B4 (de) * | 2004-03-16 | 2009-05-20 | Infineon Technologies Ag | Kopplungssubstrat für Halbleiterbauteile, Anordnungen mit dem Kopplungssubstrat, Kopplungssubstratstreifen, Verfahren zur Herstellung dieser Gegenstände und Verfahren zur Herstellung eines Halbleitermoduls |
KR100688501B1 (ko) * | 2004-09-10 | 2007-03-02 | 삼성전자주식회사 | 미러링 구조를 갖는 스택 boc 패키지 및 이를 장착한양면 실장형 메모리 모듈 |
US7645640B2 (en) * | 2004-11-15 | 2010-01-12 | Stats Chippac Ltd. | Integrated circuit package system with leadframe substrate |
US7507603B1 (en) | 2005-12-02 | 2009-03-24 | Amkor Technology, Inc. | Etch singulated semiconductor package |
US7943431B2 (en) * | 2005-12-02 | 2011-05-17 | Unisem (Mauritius) Holdings Limited | Leadless semiconductor package and method of manufacture |
US7572681B1 (en) | 2005-12-08 | 2009-08-11 | Amkor Technology, Inc. | Embedded electronic component package |
SG135074A1 (en) | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7968998B1 (en) | 2006-06-21 | 2011-06-28 | Amkor Technology, Inc. | Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package |
US7687893B2 (en) | 2006-12-27 | 2010-03-30 | Amkor Technology, Inc. | Semiconductor package having leadframe with exposed anchor pads |
US7829990B1 (en) | 2007-01-18 | 2010-11-09 | Amkor Technology, Inc. | Stackable semiconductor package including laminate interposer |
US7982297B1 (en) | 2007-03-06 | 2011-07-19 | Amkor Technology, Inc. | Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same |
US7977774B2 (en) | 2007-07-10 | 2011-07-12 | Amkor Technology, Inc. | Fusion quad flat semiconductor package |
US7687899B1 (en) | 2007-08-07 | 2010-03-30 | Amkor Technology, Inc. | Dual laminate package structure with embedded elements |
US7777351B1 (en) | 2007-10-01 | 2010-08-17 | Amkor Technology, Inc. | Thin stacked interposer package |
US8089159B1 (en) | 2007-10-03 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor package with increased I/O density and method of making the same |
US7847386B1 (en) | 2007-11-05 | 2010-12-07 | Amkor Technology, Inc. | Reduced size stacked semiconductor package and method of making the same |
US7956453B1 (en) | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US8063474B2 (en) * | 2008-02-06 | 2011-11-22 | Fairchild Semiconductor Corporation | Embedded die package on package (POP) with pre-molded leadframe |
US8067821B1 (en) | 2008-04-10 | 2011-11-29 | Amkor Technology, Inc. | Flat semiconductor package with half package molding |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US7808084B1 (en) | 2008-05-06 | 2010-10-05 | Amkor Technology, Inc. | Semiconductor package with half-etched locking features |
US8125064B1 (en) | 2008-07-28 | 2012-02-28 | Amkor Technology, Inc. | Increased I/O semiconductor package and method of making same |
US8184453B1 (en) | 2008-07-31 | 2012-05-22 | Amkor Technology, Inc. | Increased capacity semiconductor package |
US7847392B1 (en) | 2008-09-30 | 2010-12-07 | Amkor Technology, Inc. | Semiconductor device including leadframe with increased I/O |
US7989933B1 (en) | 2008-10-06 | 2011-08-02 | Amkor Technology, Inc. | Increased I/O leadframe and semiconductor device including same |
US8008758B1 (en) | 2008-10-27 | 2011-08-30 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe |
US8089145B1 (en) | 2008-11-17 | 2012-01-03 | Amkor Technology, Inc. | Semiconductor device including increased capacity leadframe |
US8072050B1 (en) | 2008-11-18 | 2011-12-06 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including passive device |
US7875963B1 (en) | 2008-11-21 | 2011-01-25 | Amkor Technology, Inc. | Semiconductor device including leadframe having power bars and increased I/O |
US7982298B1 (en) | 2008-12-03 | 2011-07-19 | Amkor Technology, Inc. | Package in package semiconductor device |
US8487420B1 (en) | 2008-12-08 | 2013-07-16 | Amkor Technology, Inc. | Package in package semiconductor device with film over wire |
US20170117214A1 (en) | 2009-01-05 | 2017-04-27 | Amkor Technology, Inc. | Semiconductor device with through-mold via |
US8680656B1 (en) | 2009-01-05 | 2014-03-25 | Amkor Technology, Inc. | Leadframe structure for concentrated photovoltaic receiver package |
US8058715B1 (en) | 2009-01-09 | 2011-11-15 | Amkor Technology, Inc. | Package in package device for RF transceiver module |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
US7960818B1 (en) | 2009-03-04 | 2011-06-14 | Amkor Technology, Inc. | Conformal shield on punch QFN semiconductor package |
US8575742B1 (en) | 2009-04-06 | 2013-11-05 | Amkor Technology, Inc. | Semiconductor device with increased I/O leadframe including power bars |
US8796561B1 (en) | 2009-10-05 | 2014-08-05 | Amkor Technology, Inc. | Fan out build up substrate stackable package and method |
US8937381B1 (en) | 2009-12-03 | 2015-01-20 | Amkor Technology, Inc. | Thin stackable package and method |
US9691734B1 (en) | 2009-12-07 | 2017-06-27 | Amkor Technology, Inc. | Method of forming a plurality of electronic component packages |
US8324511B1 (en) | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8294276B1 (en) | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8791501B1 (en) | 2010-12-03 | 2014-07-29 | Amkor Technology, Inc. | Integrated passive device structure and method |
US8674485B1 (en) | 2010-12-08 | 2014-03-18 | Amkor Technology, Inc. | Semiconductor device including leadframe with downsets |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
TWI557183B (zh) | 2015-12-16 | 2016-11-11 | 財團法人工業技術研究院 | 矽氧烷組成物、以及包含其之光電裝置 |
US8648450B1 (en) | 2011-01-27 | 2014-02-11 | Amkor Technology, Inc. | Semiconductor device including leadframe with a combination of leads and lands |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US9704725B1 (en) | 2012-03-06 | 2017-07-11 | Amkor Technology, Inc. | Semiconductor device with leadframe configured to facilitate reduced burr formation |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
KR101486790B1 (ko) | 2013-05-02 | 2015-01-28 | 앰코 테크놀로지 코리아 주식회사 | 강성보강부를 갖는 마이크로 리드프레임 |
KR101563911B1 (ko) | 2013-10-24 | 2015-10-28 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US9673122B2 (en) | 2014-05-02 | 2017-06-06 | Amkor Technology, Inc. | Micro lead frame structure having reinforcing portions and method |
EP3499552A1 (en) * | 2017-12-14 | 2019-06-19 | Nexperia B.V. | Semiconductor device and method of manufacture |
CN115274461B (zh) * | 2022-05-31 | 2024-10-11 | 浙江禾芯集成电路有限公司 | 一种应用于平面型功率器件的封装结构的封装方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59222947A (ja) | 1983-06-02 | 1984-12-14 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US4849857A (en) * | 1987-10-05 | 1989-07-18 | Olin Corporation | Heat dissipating interconnect tape for use in tape automated bonding |
US4908736A (en) | 1987-12-04 | 1990-03-13 | General Electric Company | Self packaging chip mount |
JPH0719859B2 (ja) * | 1988-12-12 | 1995-03-06 | 松下電器産業株式会社 | Icカード用モジュールの製造方法 |
JPH02177553A (ja) * | 1988-12-28 | 1990-07-10 | Matsushita Electric Ind Co Ltd | 集積回路装置およびその製造方法 |
JPH02296345A (ja) | 1989-05-10 | 1990-12-06 | Seiko Epson Corp | 半導体装置 |
US5583375A (en) | 1990-06-11 | 1996-12-10 | Hitachi, Ltd. | Semiconductor device with lead structure within the planar area of the device |
JP2839941B2 (ja) | 1990-07-26 | 1998-12-24 | 株式会社日立製作所 | 半導体装置 |
JP3170519B2 (ja) | 1992-05-12 | 2001-05-28 | 沖電気工業株式会社 | メモリカード |
JPH0661404A (ja) | 1992-08-10 | 1994-03-04 | Nec Corp | 半導体装置 |
US5302849A (en) * | 1993-03-01 | 1994-04-12 | Motorola, Inc. | Plastic and grid array semiconductor device and method for making the same |
KR0152901B1 (ko) * | 1993-06-23 | 1998-10-01 | 문정환 | 플라스틱 반도체 패키지 및 그 제조방법 |
KR970002140B1 (ko) * | 1993-12-27 | 1997-02-24 | 엘지반도체 주식회사 | 반도체 소자, 패키지 방법, 및 리드테이프 |
JPH088389A (ja) * | 1994-04-20 | 1996-01-12 | Fujitsu Ltd | 半導体装置及び半導体装置ユニット |
JPH0817864A (ja) | 1994-06-24 | 1996-01-19 | New Japan Radio Co Ltd | 半導体パッケ−ジ |
KR0145768B1 (ko) * | 1994-08-16 | 1998-08-01 | 김광호 | 리드 프레임과 그를 이용한 반도체 패키지 제조방법 |
JPH08213513A (ja) | 1994-11-08 | 1996-08-20 | Miyazaki Oki Electric Co Ltd | 樹脂封止型半導体装置の構造 |
KR100214463B1 (ko) * | 1995-12-06 | 1999-08-02 | 구본준 | 클립형 리드프레임과 이를 사용한 패키지의 제조방법 |
JP3501316B2 (ja) * | 1995-06-16 | 2004-03-02 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
KR0179803B1 (ko) * | 1995-12-29 | 1999-03-20 | 문정환 | 리드노출형 반도체 패키지 |
JPH09321212A (ja) * | 1996-05-30 | 1997-12-12 | Nec Kyushu Ltd | 半導体装置およびその製造方法 |
-
1996
- 1996-03-27 JP JP8070829A patent/JPH09260538A/ja not_active Withdrawn
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1997
- 1997-02-26 US US08/806,614 patent/US6208021B1/en not_active Expired - Fee Related
- 1997-03-06 EP EP97103710A patent/EP0798780A3/en not_active Withdrawn
- 1997-03-17 KR KR1019970008969A patent/KR970067781A/ko not_active Application Discontinuation
- 1997-03-27 CN CNB971102023A patent/CN1151554C/zh not_active Expired - Fee Related
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2000
- 2000-12-12 US US09/733,969 patent/US6403398B2/en not_active Expired - Fee Related
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EP0798780A2 (en) | 1997-10-01 |
JPH09260538A (ja) | 1997-10-03 |
US6208021B1 (en) | 2001-03-27 |
EP0798780A3 (en) | 2000-09-13 |
KR970067781A (ko) | 1997-10-13 |
CN1167339A (zh) | 1997-12-10 |
US6403398B2 (en) | 2002-06-11 |
US20010001217A1 (en) | 2001-05-17 |
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