CN1538520A - 半导体封装和制造方法 - Google Patents

半导体封装和制造方法 Download PDF

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Publication number
CN1538520A
CN1538520A CNA2004100338033A CN200410033803A CN1538520A CN 1538520 A CN1538520 A CN 1538520A CN A2004100338033 A CNA2004100338033 A CN A2004100338033A CN 200410033803 A CN200410033803 A CN 200410033803A CN 1538520 A CN1538520 A CN 1538520A
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semiconductor packages
wafer
semiconductor
packages
heat radiation
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CN100414702C (zh
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ɽҰТ��
山野孝治
吉原孝子
春原昌宏
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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Shinko Electric Co Ltd
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Abstract

在批处理中在一晶片上集体地制作多个半导体封装，并然后将该晶片切割以获得分离的半导体封装。半导体封装是通过键合两个或更多半导体器件而形成的堆叠体。每个半导体器件包括衬底和在该衬底上形成的器件布图。这些半导体器件以这样的方式堆叠起来，以致于下面的半导体器件的器件布图表面面向堆叠在其上的半导体器件的非器件布图表面。

Description

半导体封装和制造方法
技术领域
本发明涉及具有在衬底封装的半导体器件的半导体封装。更具体地说，本发明涉及能够具有高密度封装或所谓“CSP(芯片尺寸封装)”的小的和高性能的半导体封装。本发明进一步涉及一种容易地和高产出地在晶片级制造这种半导体封装的方法。
背景技术
为了应付电子设备的性能提高和尺寸减小即所谓“缩小化”，近年来提出了组合了诸如IC芯片、LSI芯片等半导体器件的各种半导体封装，或具有安装在衬底上的半导体芯片的半导体器件。为了在这种半导体封装中实现高密度封装，各研究机构和公司提出了一些三维封装模型。虽然已提出了将半导体芯片互相叠置起来、并通过连接线将它们连接起来的方法，最有前途的方法可能是通过倒装晶片(FC)将叠置的芯片键合在一起并在芯片之间填充底层填料的方法。
最近，有人提出了没有FC的缩小尺寸的半导体封装。例如，如图1所示，有人提出了一种通过使用绝缘粘合剂106在布图膜104上堆叠多个晶片(半导体芯片)105而制作的堆叠半导体器件114(参见日本未经审查的专利公开2000-252411)。在这种堆叠半导体器件114中，在堆叠的晶片体105的外表面和内表面上形成纵向布线布图116，并通过外部连接布图103在布图膜104的下表面上安排外部连接端子111。然而，在这种堆叠半导体器件的情况下，各晶片的堆叠、切割、硅蚀刻和施加绝缘粘合剂必须重复地进行，以便形成具有多个所需数量的晶片级的堆叠体，并且这些制造步骤是极为复杂的。另一个问题是必须单独地包括纵向布线布图的形成步骤。
也已提出了如图2所示通过首先制造在其相对表面上具有突出的电极164的半导体芯片162、并把多个(图中是6个)半导体芯片162以这样的方式堆叠在一起以致于彼此抵住而制造的半导体器件161(参见日本未经审查的专利公开2001-94039)。每个半导体芯片162在其每个表面上具有一绝缘层172，并具有在其相对表面之间形成的通孔166。在通孔166内部顺序地形成绝缘膜168和导体件170。然而，由于这种半导体器件采用了顺序地堆叠半导体芯片的方法，它具有产出低的缺点。此外，利用模子的用于绝缘层的转移步骤是复杂的。
发明内容
本发明的一个目的是解决如上所述的现有技术的问题。
本发明的另一目的是提供一种具有高密度封装的小的或缩减尺寸的和高性能的半导体封装。
本发明的再一个目的是提供一种在晶片级容易地和高产出地制造具有高密度封装的小的和高性能的半导体封装的方法。
从以下详细解释中将容易地理解本发明的上述和其他目的。
根据本发明的一个方面，提供了一种半导体封装，该半导体封装的形成方法是在批处理中在一晶片上集体地制造多个半导体封装，并将其切割为分离的半导体封装，其中半导体封装是通过使用一绝缘层键合两个或更多半导体器件而形成的堆叠体；这些半导体器件中的每个包括一衬底和在该衬底上形成的器件布图；并且下面的半导体器件的器件布图表面面向在该较低的半导体器件之上堆叠的半导体器件的非器件布图表面。
根据本发明的另一个方面，提供了一种制造半导体封装的方法，该半导体封装包括由两个或更多半导体器件构成的堆叠体，每个半导体器件具有一衬底和在该衬底的一个表面上形成的器件布图，该方法包括以下步骤：
处理包括半导体材料的晶片以在批处理中集体地制作多个在其一个表面上具有预定器件布图的半导体器件，以由此制造出半导体器件封装晶片，并重复进行这种半导体器件封装晶片的制造；
在下面的半导体器件封装晶片上通过绝缘层键合另一半导体器件封装晶片，另一半导体器件封装晶片的非器件布图表面面向下，其中在制造另一半导体器件封装晶片的步骤中，包括所述半导体材料的晶片被键合到所述下面的半导体器件封装晶片的器件布图表面上，并且制作所键合的晶片以集体地制作多个在其表面上具有预定器件布图的半导体器件；以及
在键合完成该半导体封装所需要数量的半导体器件封装晶片之后，沿着预定的切割线将所产生的晶片堆叠体切割，以从该晶片堆叠体获得分离的半导体封装。
附图说明
图1是根据现有技术的半导体封装的一个例子的透视图；
图2是根据现有技术的半导体封装的另一个例子的透视图；
图3是根据本发明的一个优选实施例的半导体封装的截面图；
图4是根据本发明的另一个优选实施例的半导体封装的截面图；
图5A至5J是顺序显示出根据本发明的一个优选实施例的半导体封装的制造方法的截面图；以及
图6A至6M是顺序显示出根据本发明的另一优选实施例的半导体封装的制造方法的截面图。
具体实施方式
根据本发明的半导体封装及其制造方法可以有利地在各种实施例中实现。下面将解释本发明的优选实施例。
根据本发明的半导体封装是通过在批处理中在晶片级(即在晶片上)集体地制作多个半导体封装，并将由此获得的晶片产品切割为分离的半导体封装。换言之，根据本发明的半导体封装在其构造和制造方法上不同于过去广泛使用的半导体封装，过去的半导体封装是通过预先制作两个或更多半导体器件(例如，诸如IC、LSI等半导体器件)，然后把这些半导体器件堆叠在一起并在半导体器件之间填充底层填料。正向通过以下解释将容易地理解的那样，本发明的可进行三维封装尤其是在晶片级进行三维封装的特点对于高密度封装和减少制作步骤是有利的。
根据本发明的半导体封装满足下列要求。
(1)半导体封装是通过使用绝缘层键合两个或更多半导体器件而得到的堆叠体，其中绝缘层插在邻接的半导体器件之间；
(2)每个半导体器件包括衬底和在该衬底上形成的器件布图；
(3)下面的半导体器件的器件布图表面面对着堆叠在该下面的半导体器件之上的半导体器件的非器件布图表面；
半导体封装是通过使用绝缘层把两个或更多半导体器件键合在一起而获得的堆叠体。然而，该半导体封装不是通过键合所需数量的已制作好的半导体器件而制作的，而是通过这样的方法制造的，即在所需数量的晶片中进行器件布图的形成和使用绝缘层将晶片彼此键合在一起以获得晶片堆叠体(在其上安装了半导体器件的晶片的堆叠体)并将该堆叠体切割为分离的半导体封装。
在本发明的实践中，用于所产生的半导体器件的衬底的堆叠晶片的数量并不受特别限制，并可以根据所需半导体封装的构造任意地堆叠必要数量的晶片。要堆叠的晶片的数量通常是2至8个，优选地是4个。虽然晶片可以用各种材料形成，半导体材料例如硅作为衬底通常是优选的。陶瓷材料例如玻璃也可用作衬底。晶片的厚度通常是在约50至725μm的范围内。
在根据本发明的半导体封装中，使用绝缘层将半导体器件(或晶片)彼此键合在一起。绝缘层优选地是由绝缘树脂材料形成的，并且例如聚酰亚胺树脂和环氧树脂可用作绝缘层材料。为形成绝缘层，可施加这种树脂材料的溶液，并使其硬化。如有必要，可通过使用粘合剂或粘合剂膜来形成绝缘层。绝缘层的厚度通常在约10至75μm的范围内，并且优选地在约10至45μm的范围内。
在根据本发明的半导体封装中，在半导体封装中包括的两个或更多半导体器件中的每个被以这样的方式构成以包括衬底和在该衬底的一个表面上形成的器件布图。需要时，半导体器件可包括其他元件。如上所述，衬底是从半导体晶片或其他晶片切割而成的，并且器件布图被形成在衬底的一个表面上。“器件布图”包括但不限于布线层(包括重新布线层等)、电极、衬底通透电极、导体台、有源芯片和无源芯片。器件布图通常是在衬底的表面上形成的，但需要时，也可在衬底的背面或内部形成。
在根据本发明的半导体封装中，下面的半导体器件的器件布图表面面向在该下面的半导体器件上堆叠的半导体器件的背面。换言之，根据本发明的半导体封装不采用这样的构造，其中各晶片表面侧(器件布图表面)彼此抵住并键合在一起，而是采用这样的构造，其中晶片的表面侧(器件布图表面)和晶片的背面(晶片的非器件布图表面，即需要时可在其上进行背面抛光的BSG侧)彼此抵住并键合在一起。应注意，根据现有技术，这种子片级的三维封装是非常困难的。这种键合构造对于减少半导体封装的厚度、布线长度和制造步骤是有用的。
此外，根据本发明的半导体封装可具有附加的一层或多层以改善其构造和性能。例如，根据本发明的半导体封装中最底部的半导体器件的非器件布图表面优选地进一步具有由具有高传热率的材料构成的热辐射或热释放层。热辐射层相当于在常规半导体封装中单独地被键合的冷却板、热辐射鳍等，并改善了半导体器件的热辐射特性。取决于半导体器件的厚度，热辐射层也可充当其支撑。
热辐射层优选地在半导体封装被个别地切割而成之前沉积在作为最底层的晶片的非器件布图表面。热辐射层优选地通过使用薄膜形成技术，例如溅射或真空沉积来形成。换言之，由于根据本发明的热辐射层可在晶片级作为薄膜而形成，它极其有助于减少半导体封装厚度和制造步骤。
可利用各种材料以任何所需的厚度形成热辐射层。例如，当使用溅射形成薄膜时，铜、铝或其合金适合于作为热辐射层的材料，尽管并不限于它们。热辐射层的厚度通常在0.1到1μm的范围内，并优选地在0.1到0.5μm的范围内。
根据本发明，热辐射层可在晶片级生产半导体封装过程中的任何阶段形成，并可最有用地在生产过程的最后阶段在晶片的BSG侧形成。需要时，当在不具有堆叠构造的半导体器件和半导体封装的制造过程中，在晶片阶段中的BSG侧形成热辐射层时，也可获得本发明所构想的操作和效果。
在根据本发明的半导体封装中，并且优选地在堆叠的半导体器件中，通过在一个半导体器件中同时形成的一个布线层，优选地通过重新布线层，以及衬底通透电极，即穿过衬底而形成的电极，将器件布图彼此电连接在一起。换言之，在根据本发明的半导体封装中，当重新布线层和衬底通透电极优选地同时形成时，可简化构造并减少制造步骤。重新布线层和衬底通透电极均可以有利地通过镀以铜或其合金而形成。
此外，在根据本发明的半导体封装中，作为最上层的半导体器件优选地进一步包括在其器件布图表面上的一树脂密封层。如对上述热辐射层同样的方式，树脂密封层优选地在将半导体封装分离地切割而成之前在作为最上层的晶片的器件布图表面上形成。用于形成树脂密封层的树脂没有特别的限制，并可以有利地使用作为常规密封树脂的环氧树脂。可以通过涂层、罐封、薄膜键合等方法将密封树脂施加在器件布图表面上。树脂密封层对于保护半导体封装及其器件布图免受湿气侵入和撞击是有用的。树脂密封层的厚度通常在约50至90μm的范围内，并优选地在60至80μm的范围内。
此外，本发明在于一种半导体封装的制造方法，该半导体封装包括两个或更多半导体器件的堆叠体，每个半导体器件包括衬底和在该衬底的表面上形成的器件布图。如从上述对半导体封装的解释和从以下参照附图对本发明的实施例的解释可以理解的，根据本发明的制造方法包括下以步骤：
(1)处理半导体材料的晶片以在批处理中集体地制造多个各在晶片表面上具有预定器件布图的半导体器件，以由此形成半导体器件封装晶片，并重复进行这种半导体器件封装晶片的形成；
(2)在下面的半导体器件封装晶片上通过绝缘层键合另一半导体器件封装晶片，另一半导体器件封装晶片的非器件布图表面面向下，其中在制造另一半导体器件封装晶片的步骤中，将半导体材料构成的晶片通过所述绝缘层键合到所述下面的半导体器件封装晶片的器件布图表面上，并且制作所键合的晶片以集体地制作多个各在其表面上具有预定器件布图的半导体器件；以及
(3)在键合完成该半导体封装所需数量的半导体器件封装晶片之后，沿着预定的切割线将所产生的晶片堆叠体切割。
在这里应注意，术语“半导体器件封装晶片”是指根据本发明的半导体封装的前体，并表示这样的晶片，在该晶片中已制作了对应于将被切割而成的若干半导体封装的若干半导体器件。换言之，当按照预先设计堆叠预定数量的半导体封装晶片以获得晶片堆叠体并将堆叠体切割时，可分离地获得所需数量的半导体封装。
实例
下面，将参照附图解释本发明的实例。但是应当注意，本发明不限于以下实例。在以下对半导体封装的制造方法的解释中，为了简化起见，放大地示出了一个半导体封装。但是在实践中，由于制造是在晶片级进行的，所以使用了集体地和成批地在一个晶片中制作大量半导体封装并将该晶片切割为分离的半导体器件的方法。
图3是根据本发明的半导体封装的一个优选示例的截面图。半导体封装10是通过根据预先设计在一个硅晶片中制作大量半导体器件并沿着切割线“D”将该晶片切割而制造的。在所示的半导体封装10中，具有下面硅衬底11的第一半导体器件和具有上面硅衬底21的第二半导体器件通过由环氧树脂形成的绝缘层而彼此键合在一起。
参见第一半导体器件，硅衬底11的一个表面相当于本发明所指的“器件布图表面”，并且硅衬底11包括由铝(Al)构成的电极台12、由聚酰亚胺树脂构成的保护膜13和由铜(Cu)构成的布线层(在这里为重新布线层)14。硅衬底11的背面是背面研磨的表面(BSG表面)，并已使用化学机械抛光(CMP)进行了研磨以获得具有所需厚度的硅衬底11。
下一步，参见第二半导体器件，它以这样的方式被堆叠以使其BSG表面面向第一半导体器件的器件布图表面，硅衬底21的一个表面相当于器件布图表面。硅衬底21包括由铝(Al)构成的电极台22、由聚酰亚胺树脂构成的保护膜23和由铜(Cu)构成的布线层(在这里为重新布线层)24。硅衬底21具有由铜(Cu)构成并穿过硅衬底21的通透电极26。衬底通透电极26是与布线层24同时形成的并将布线层24和布线层14电连接在一起。在硅衬底21的器件布图表面的整个表面上覆盖环氧树脂的树脂密封层27。在布线层24的预定位置上植入由铜(Cu)构成的导体柱28，并进一步在布线层24上安置焊球29。焊球29构成外部连接端子，并且可以使用焊块(solder bump)或类似物来代替焊球29。
所图示的半导体封装具有的特征是晶片的器件布图表面和晶片的BSG表面在晶片的键合步骤中彼此抵住，衬底通透电极即过孔电极以这样的方式形成以穿过硅衬底，布线层和过孔电极是不使用CMP而同时形成的，以及对晶片进行切割以集体地获得大量半导体封装。由于这些特征，可减少各芯片间的布线长度，并可提供高速封装。此外，由于三维构造，高密度封装成为可能。
图4的截面图示出了在根据本发明的半导体封装中的晶片的背面提供冷却板功能的示例。以对图3所示的半导体封装相同的方式，通过沿着切割线“D”对半导体器件封装晶片的堆叠体进行切割而获得半导体封装10。在所示的半导体封装10中，具有下面硅衬底11的第一半导体器件和具有上面硅衬底21的第二半导体器件通过环氧树脂构成的绝缘层15而被键合在一起。
对于第一半导体器件，为简化说明起见，省略了其构造的细节。通过CMP对硅衬底11的背面进行抛光以获得具有所需厚度的硅衬底，并通过键合环氧树脂膜而键合背面保护膜31。进一步在保护膜31的背面堆叠通过溅射铝(Al)而形成的热辐射层32。
以这样的方式堆叠第二半导体器件以使其BSG表面面向第一半导体器件的器件布图表面。第二半导体器件的硅衬底21的一个表面相当于器件布图表面，并且第二半导体器件具有由铝(Al)构成的电极台22、由聚酰亚胺树脂构成的保护膜23和由铜(Cu)构成的布线层(在这里为重新布线层)24。在硅衬底21的整个器件布图表面上覆盖由环氧树脂构成的树脂密封层27。在布线层24的预定位置上植入由铜(Cu)构成的导体柱28，并进一步安置焊球29。焊球29构成外部连接端子，并且可以安置焊块或类似物来代替焊球29。
所示的半导体封装具有的特征是晶片的器件布图表面和晶片的BSG表面在晶片的键合步骤中彼此抵住，热辐射层是由具有高传热率的材料构成的并被用作支撑，并且将包括该支撑的各衬底进行切割以获得大量半导体封装。由于这些特征，可减少各芯片间的布线长度，并可提供高速封装。此外，由于三维构造，高密度封装成为可能。除了根据本发明的半导体封装所固有的这些特征外，该半导体封装提供了新的效果，即由于热辐射层作为冷却板的替代与晶片整体地形成，可改善芯片的热辐射特性，并可减少制造步骤。
图5A至5J的截面图顺序示出了具有类似于图3所示构造的半导体封装的优选制造方法。
首先，为了制作所需数量的半导体器件，准备图5A所示的硅晶片11。顺便提一下，如已经说明的那样，为简化说明起见，该图只示出了硅晶片11的一部分(即与一个半导体封装相应的部分；因此，是所产生的半导体封装的硅衬底)。
下一步，通过在如此准备的硅衬底11的器件布图表面上涂镀和蚀刻而形成由铝(Al)构成的电极台12，并在该电极台12上覆盖由聚酰亚胺树脂构成的绝缘膜13。绝缘膜13可以通过例如施加聚酰亚胺树脂的前体溶液并通过加热固化该溶液而形成。在绝缘膜13中的电极台12的部分保持敞开，以便在下一步骤中连接布线层。下一步，通过在预定布图中镀铜(Cu)而形成布线层(这里为重新布线层)14。
在形成布线层14后，如图5B所示，在硅晶片11的器件布图表面上以预定厚度涂敷环氧树脂，以形成绝缘层15。可通过键合环氧树脂膜形成绝缘层15，或者可通过其他材料形成绝缘层，只要这些材料可用于相互键合硅晶片并提供所需的绝缘效果即可。
下一步，如图5C所示，硅晶片21被堆叠在硅晶片11上，并且通过绝缘层15被键合。硅晶片21的尺寸与硅晶片11的尺寸相同。
随后，按照以下步骤，在硅晶片21中制作所需数量的第二半导体器件：
首先，如图5D所示，在硅晶片21的衬底通透电极(过孔电极)形成部分形成通透孔36。可通过常规技术，例如反应离子蚀刻(RIE)、激光处理、蚀刻等来形成通透孔36。作为形成通透孔36的结果，绝缘层15的表面被部分暴露。
下一步，如图5E所示，通过在硅晶片21的器件布图表面上涂镀和蚀刻而形成由铝(Al)构成的电极台22。
此后，如图5F所示，在硅晶片21上覆盖由聚酰亚胺树脂构成的绝缘膜23。绝缘膜23是通过例如施加聚酰亚胺树脂的前体溶液并通过加热固化而形成的。在绝缘膜23中，电极台22的部分保持敞开，以在下一步骤中连接布线层。在已形成的通透孔36的侧壁上也覆盖了绝缘膜23。
随后，暴露在通透孔36远端的绝缘层15被有选择地清除，以形成更深的通透孔37，从而暴露出下面的布线层14，如图5G所示。这是为了在下一步骤中将硅晶片11的器件布图与硅晶片21的器件布图电连接在一起。可使用常规技术，例如湿蚀刻、干蚀刻(化学干蚀刻)、激光处理等来将绝缘层清除和敞开。
此后，如图5H所示，在硅衬底21的器件布图表面上在预定布图上形成由铜(Cu)构成的布线层(这里为重新布线层)24，并同时在前一步骤形成的过孔37中填入Cu以形成过孔电极26。可通过例如电镀或化学镀铜来有利地同时形成布线层24和过孔电极26。在该镀铜步骤之前，优选地通过溅射或类似方法以Cr、Ti、Cu等形成势垒金属层和种子层。
当以上述方式在硅晶片21中同时形成布线层24和过孔电极26之后，如图5I所示，形成导体(Cu)柱28，并使用环氧树脂覆盖整个晶片21以形成树脂密封层27。这一步骤可有利地以这样的方式进行，即通过例如使用抗蚀布图(未示出)作为掩膜电镀铜而形成Cu柱28。当通过蚀刻清除种子层之后，按照树脂罐封法罐封环氧树脂以形成树脂密封层27。
最后，在于前一步骤形成的Cu柱28上设置焊球29，并在升高的温度下使焊料回流。进一步地，当沿着预定切割线(未示出)将硅晶片11和21切割后，可集体地获得大量具有期望构造的半导体封装10，如图5J所示。
图6A至6M的截面图顺序示出了具有类似于图4所示构造的半导体封装的一种优选制造方法。
首先，如图6A所示，在硅晶片11的器件布图表面上放置硅晶片21，在硅晶片11中构造有预定数量的第一半导体器件(未示出)，其放置的方式使硅晶片21的BSG表面面向硅晶片11的器件布图表面。硅晶片21的尺寸与硅晶片11的尺寸相同。已通过CMP将硅晶片21的BSG表面抛光，以获得具有所需厚度的硅晶片21。通过环氧树脂构成的绝缘层(未示出)将硅晶片11和硅晶片21键合在一起。
下一步，如图6B所示，为在下一步骤中形成布线层而进行预处理。首先，通过在硅晶片21的器件布图表面上涂镀和蚀刻而形成由铝(Al)构成的电极台22。顺序地形成聚硅酸盐玻璃(PSG)钝化膜41和SiN绝缘膜。
随后，如图6C所示，以所述顺序形成势垒金属层43和种子层(导体层)44。例如，可通过溅射Cr、Ti等而形成势垒金属层43，并可通过溅射Cu等而形成种子层44。
当如上所述完成了预处理之后，以如下方式进行布线层(在此为重新布线层)的形成步骤。
首先，如图6D所示，以这样的方式形成导引抗蚀膜45，以排除重新布线层的形成区域。导引抗蚀膜45的形成方式可以是，例如将抗蚀剂施加到硅晶片21的整个表面，固化抗蚀剂并溶解和清除不需要的部分。
下一步，如图6E所示，在有导引抗蚀膜45的情况下进行镀铜(Cu)以在硅衬底21的器件布图表面上形成Cu的重新布线层。镀Cu可通过例如Cu的电镀或化学镀进行。
当以上述方式形成了Cu的重新布线层24之后，如图7F所示，溶解并清除已不再需要的导引抗蚀膜45，并通过CMP研磨硅晶片的BSG表面。在图中由虚线所示的部分被从硅晶片11中去除。
下一步，如图6G所示，在导体柱的形成部分48以外的部分中形成用于柱形成导引的抗蚀膜46。该柱形成导引抗蚀膜46是通过例如这样的方式形成的，即在硅晶片21的整个表面上施加抗蚀剂，固化抗蚀剂，并从区域48中溶解和清除抗蚀剂。
当以上述方式形成柱形成导引抗蚀膜46之后，如图6H所示，形成导体(Cu)柱28，并进一步在Cu柱28上形成势垒金属层38。该步骤可以有利地以这样的方式形成，即通过在有抗蚀膜45作为掩膜的情况下电镀Cu来形成Cu柱28，并随后溅射势垒金属(Cr、Ti等)
下一步，如图6I所示，溶解和清除用作形成Cu柱28的掩膜的抗蚀膜46。在该阶段，在硅晶片21上形成的用于电镀的势垒金属层43和种子层44被清除。
随后，如图6J所示，将环氧树脂键合在硅晶片11和21的堆叠体的背面(硅晶片11的BSG表面)，以形成背面保护膜31。
此后，如图6K所示，在所产生的晶片堆叠体的器件布图表面上沉积环氧树脂，沉积厚度能够完全掩埋Cu柱以形成树脂密封层27。可通过例如罐封环氧树脂来形成树脂密封层27。
当树脂密封完成后，如图6L所示，进一步在于前一步骤形成的背面保护膜31上形成热辐射层32。该步骤可有利地通过例如溅射具有高传热率材料的铝(Al)而进行。
最后，在于前一步骤形成的Cu柱28上设置焊球29，并在高温下使焊球回流。进一步地，沿着切割线(未示出)将硅晶片11和21切割，以集体地制造出大量如图6M所示具有所需结构的半导体封装。
如以上详细描述的，本发明可提供一种具有高密度封装的小的和高性能的半导体封装，以及一种在晶片级容易地和高产出地制造这种半导体封装的方法。当在晶片级在该半导体封装的背面形成由具有高传热率的材料构成的、和具有冷却板功能的热辐射层时，与现有技术中键合冷却板的情况相比，可改善该半导体封装的热辐射性能，并可减少生产步骤的数量。
特别值得注意的是，尽管过去认为对构造进行晶片级三维封装是困难的，在这种三维封装中晶片的表面(器件布图表面)和晶体的背面(作为非器件布图表面的BSG表面)被彼此抵住并键合在一起，本发明却能够实现这种构造，并容易地在晶片级完成高密度封装。当采用本发明提出的手段时，可获得的优点是用于制造组合衬底的现有材料和现有装置可被原样用于本发明。
根据本发明，封装是在晶片级进行的，并且重新布线层是在晶片的器件布图表面上形成的。在所产生的半导体封装中，可缩短半导体芯片和半导体芯片之间的布线长度，并且可实现从用于射频DRAM的半导体封装开始的高速半导体封装。
根据本发明，进一步地，当在晶片的器件布图表面上形成重新布线层时，不需要通常的在布线层的形成之前使用的CMP(化学机械抛光)，并可同时形成过孔电极。因此，可极大地减少制造步骤并将其简化。

Claims (18)

1.一种半导体封装，它是通过在批处理中在晶片上集体地制作多个半导体封装、并将所产生的晶片产品切割为分离的半导体封装而获得的，其中
所述半导体封装是通过使用绝缘层键合两个或更多半导体器件而形成的一堆叠体；
所述半导体器件中的每个包括衬底和在其一个表面上形成的器件布图；以及
下面的半导体器件的器件布图表面面向在该下面的半导体器件上堆叠的半导体器件的非器件布图表面。
2.根据权利要求1的半导体封装，其中被放置为最底层的所述半导体器件进一步包括热辐射层，该热辐射层由具有高传热率的材料在其非器件布图表面上构成。
3.根据权利要求2的半导体封装，其中所述热辐射层是在所述半导体封装被切割之前沉积在作为最底层的晶片的非器件布图表面上的热辐射层。
4.根据权利要求2或3的半导体封装，其中所述热辐射层是通过薄膜形成技术而形成的热辐射层。
5.根据权利要求2或3的半导体封装，其中所述热辐射层是由铜、铝或其合金构成的。
6.根据权利要求2或3的半导体封装，其中所述热辐射层也充当支撑。
7.根据权利要求1或2的半导体封装，其中所述绝缘层包括聚酰亚胺树脂或环氧树脂。
8.根据权利要求1或2的半导体封装，其中被放置为最上层的所述半导体器件进一步包括在其器件布图表面上的树脂密封层，并且所述树脂密封层是在所述半导体封装被切割而成之前在作为最上层的晶片的器件布图表面上形成的树脂密封层。
9.根据权利要求1或2的半导体封装，其中所述堆叠的半导体器件的器件布图是通过在一个半导体器件中同时形成的重新布线层和衬底通透电极而彼此电连接起来的。
10.根据权利要求9的半导体封装，其中所述重新布线层和所述衬底通透电极是由铜或其合金构成的。
11.一种制造半导体封装的方法，该半导体封装包括两个或更多半导体器件的堆叠体，每个半导体器件具有一衬底和在其一个表面上形成的器件布图，该方法包括以下步骤：
处理包括半导体材料的晶片，以在批处理中集体地制作多个在其一个表面上具有预定器件布图的半导体器件，以便由此制造半导体器件封装晶片，并重复进行所述半导体器件封装晶片的制造；
通过绝缘层将另一个半导体器件封装晶片键合在下面的半导体器件封装晶片上，所述另一个半导体器件封装晶片的非器件布图表面面向下，其中在制造所述另一个半导体器件封装晶片的步骤中，将包括所述半导体材料的晶片键合到所述下面的半导体器件封装晶片的所述器件布图表面上，并且制作所述被键合的晶片以集体地制作多个在其一个表面上具有预定器件布图的半导体器件；以及
当键合完成所述半导体封装所需数量的所述半导体器件封装衬底后，沿着预定切割线将所产生的晶片堆叠体切割，以从所述晶片堆叠体获得分离的半导体封装。
12.根据权利要求11的半导体封装的制造方法，其中在所述晶片堆叠体中作为最底层的所述半导体器件封装晶片的非器件布图表面上由具有由高传热率材料形成的热辐射层。
13.根据权利要求12的半导体封装的制造方法，其中所述热辐射层是由薄膜形成技术形成的。
14.根据权利要求12或13的半导体封装的制造方法，其中所述热辐射层是由铜、铝或其合金构成。
15.根据权利要求11或12的半导体封装的制造方法，其中所述绝缘层是由聚酰亚胺树脂或环氧树脂构成。
16.根据权利要求11或12的半导体封装的制造方法，其中在所述晶片堆叠体中作为最上层的所述半导体器件封装晶片的器件布图表面上进一步形成一树脂密封层。
17.根据权利要求11或12的半导体封装的制造方法，其中在制造所述另一个半导体器件封装晶片的步骤中同时形成一重新布线层和一衬底通透电极。
18.根据权利要求17的半导体封装的制造方法，其中所述重新布线层和所述衬底通透电极是由铜或其合金构成的。
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