CN1453847A - 半导体装置及其制造方法、电路基片和电子仪器 - Google Patents

半导体装置及其制造方法、电路基片和电子仪器 Download PDF

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CN1453847A
CN1453847A CN03124021A CN03124021A CN1453847A CN 1453847 A CN1453847 A CN 1453847A CN 03124021 A CN03124021 A CN 03124021A CN 03124021 A CN03124021 A CN 03124021A CN 1453847 A CN1453847 A CN 1453847A
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mentioned
hole
semiconductor device
semiconductor chip
manufacture method
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CN1241252C (zh
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宫泽郁也
池原忠好
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Seiko Epson Corp
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Seiko Epson Corp
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    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
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    • F16K1/18—Lift valves or globe valves, i.e. cut-off apparatus with closure members having at least a component of their opening and closing motion perpendicular to the closing faces with pivoted closure-members with pivoted discs or flaps
    • F16K1/22—Lift valves or globe valves, i.e. cut-off apparatus with closure members having at least a component of their opening and closing motion perpendicular to the closing faces with pivoted closure-members with pivoted discs or flaps with axis of rotation crossing the valve member, e.g. butterfly valves
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Abstract

在形成有集成电路(12)的半导体基片(10)上形成贯穿孔(30)，该贯穿孔(30)具有从开口朝深度方向逐渐变细的锥度。从开口向贯穿孔(30)供给绝缘材料，以在贯穿孔(30)的内表面形成绝缘层(32)。从开口向形成有绝缘层(32)的贯穿孔(30)供给导电材料，以在绝缘层(32)的内侧形成导电部(44)。

Description

半导体装置及其制造方法、电路基片和电子仪器
技术领域
本发明涉及一种半导体装置及其制造方法、电路基片和电子仪器。
背景技术
现在开发了三维立体封装形式的半导体装置。为实现立体封装，在半导体芯片上形成贯通电极。详细而言是在半导体芯片上形成贯通孔，在贯通孔的内面形成绝缘层，在绝缘层内侧形成贯通电极。这种情况下，在小的贯通孔内面很难形成绝缘层，在绝缘层内侧也很难形成导电电极。
发明内容
为解决这些问题，本发明的目的在于：可以简单地形成贯通电极。
(1)本发明的半导体装置的制造方法包括：
(a)在形成了集成电路的半导体基片上，形成从开口向纵深方向逐渐变细的锥形贯通孔；
(b)从上述开口向上述贯通孔供给绝缘材料，在上述贯通孔的内面形成绝缘层；
(c)从上述开口向形成了上述绝缘层的上述贯通孔供给导电材料，在上述绝缘层的内侧形成导电部。
根据本发明，贯通孔的开口变大，便于供给绝缘材料和导电材料，可以简单地形成贯通电极。
(2)在该半导体装置的制造方法中，
可以采用包括喷砂的方法形成上述贯通孔。
(3)在该半导体装置的制造方法中，
也可以在上述半导体基片上形成利用上述喷砂方法形成的锥形凹部，对上述凹部的底面进行激光加工形成上述贯通孔。
(4)在该半导体装置的制造方法中，
上述半导体基片的第1面具有电极；
也可以在与上述半导体基片上形成了上述电极的第1面相反侧的第2面上形成上述贯通孔。
(5)在该半导体装置的制造方法中，
也可以使上述贯通孔贯通上述电极。
(6)在该半导体装置的制造方法中，
也可以在形成上述贯通孔时，使上述半导体基片的表面与上述贯通孔的内壁面之间的角度为70℃以上90℃以下。
(7)在该半导体装置的制造方法中，
上述半导体基片是半导体晶片，多个上述集成电路形成在上述半导体基片上，分别对应上述集成电路形成上述导电部。
另外包括在上述(C)工序后，切断上述半导体基片。
(8)本发明的半导体装置的制造方法包括：
层积根据上述方法制造的多个半导体装置，通过上述导电部电连接。
(9)本发明的半导体装置根据上述方法制造。
(10)本发明的半导体装置具有：
集成电路；
半导体基片，形成有从开口向纵深方向逐渐变细的锥形贯通孔；
设置于上述贯通孔内面的绝缘层；
设置于上述绝缘层内侧的导电部。
(11)本发明的半导体装置包括：
具有上述多个半导体；
层积的上述多个半导体通过上述导电部电连接。
(12)本发明的电路基片封装有上述半导体装置。
(13)本发明的电子仪器具有上述半导体装置。
附图说明
图1(A)～图1(E)是说明适用了本发明的实施例的半导体装置制造方法的图。
图2(A)～图2(D)是说明适用了本发明的实施例的半导体装置制造方法的图。
图3(A)～图3(D)是说明适用了本发明的实施例的半导体装置制造方法的图。
图4是说明适用了本发明的实施例的半导体装置制造方法的图。
图5是说明适用了本发明的实施例的半导体装置的图。
图6是说明本发明实施例的电路基片的图。
图7是说明本发明实施例的电子仪器的图。
图8是说明本发明实施例的电子仪器的图。
发明的具体实施方式
下面，参照附图就本发明的实施例加以说明。
图1(A)～图3(D)是说明适用了本发明的实施例的半导体装置制造方法的图。本实施例中使用半导体基片10。图1(A)中表示的半导体基片10可以是半导体晶片，也可以是半导体芯片。在半导体基片10上形成至少1个(半导体晶片上为多个，半导体芯片上为1个)集成电路(例如具有三晶体管和存储器的电路)12。半导体基片10上形成多个电极(例如衬垫)14。各电极14电连接集成电路12。各电极14也可以由铝形成。不限定电极14的表面形状，但多数为矩形。半导体基片10是半导体晶片时，在多个半导体芯片区域内分别形成2个以上(1组)的电极14。
半导体基片10上形成1层或1层以上的钝化膜16、18。钝化膜16、18可以由例如：SiO2、SiN、聚酰亚胺树脂等形成。图1(A)表示例中，在钝化膜16上形成电极14、连接集成电路12和电极14的布线(无图示)。另外，别的钝化膜18避开电极14的表面的至少一部分形成。钝化膜18覆盖电极14的表面形成后，刻蚀其中一部分，可以露出电极14的一部分。刻蚀可以采用干法刻蚀或湿法刻蚀中的任意一种。刻蚀钝化膜18时，也可以刻蚀电极14的表面。
本实施例中，在半导体基片10上形成贯通孔30(参照图1(D))。为此，如图1(B)所示也可以在半导体基片10上形成抗蚀膜20。抗蚀膜20也可以形成在与形成电极14的第1面相反侧的第2面上。抗蚀膜20构图具有开口22。形成开口22时也可以至少有一部分与电极14重叠。在开口22内形成贯通孔30。
如图1(C)所示，为形成贯通孔30，也可以在半导体基片10上形成凹部24。形成从开口向纵深方向逐渐变细的锥形凹部24。即凹部24的开口比底面大。半导体基片10的表面(第2面)与凹部24的内壁面之间的角度α可以是70℃以上90℃以下。这种形状的凹部24也可以采用喷砂方法形成。
如图1(D)所示，在凹部24的底面形成贯通孔26。形成时也可以使用例如激光(YAG激光、CO2激光、准分子激光等)。也可以采用刻蚀(干法刻蚀或湿法刻蚀)。贯通孔26可以贯通电极14。在半导体基片10上，由凹部24和贯通孔26形成贯通孔30。贯通孔30的一部分内壁面是凹部24的内壁面。因此，贯通孔30从开口向纵深方向逐渐变细呈锥形。贯通孔30贯通电极14。
如图1(E)所示，在贯通孔30的内面形成绝缘层32。绝缘层32也可以形成至与半导体基片10的电极14相反侧的面(第2面)。贯通孔30贯通电极14时，也可以在形成于电极14的孔的内面形成绝缘层32。只是，形成绝缘层32时，电极14至少露出一部分(例如表面)。向贯通孔30供给绝缘材料形成绝缘层32。从贯通孔30的锥形开口(凹部24的开口)供给绝缘材料。通过这种作法，可以从大的开口供给绝缘材料，容易形成绝缘层32。绝缘材料可以采用屏幕印刷方式、喷墨打印方式、化学汽相沉积(CVD)、喷射方式或利用垫片涂抹。
如图2(A)所示，在绝缘层32上形成导电层34。导电层34至少在贯通孔30内形成。形成导电层34包括向贯通孔30内供给导电材料。导电材料可以采用屏幕印刷方式、喷墨打印方式、化学汽相沉积(CVD)、喷射方式或利用垫片涂抹。导电层34至少可以包括阻挡层。阻挡层是防止在其上的材料扩散到半导体基片10(例如Si)。形成阻挡层的材料也可以不同于其上面的材料(例如TiW、TiN)。导电层34也可以包括薄膜层。薄膜层在形成阻挡层以后形成。形成薄膜层的材料也可以与其上面的材料一样(例如Cu)。导电层34也可以设计为不填满贯通孔30。即在贯通孔30内可以形成由导电层34包围的贯通孔。导电层34只在绝缘层32上形成时，导电层34不与电极14电连接。
如图2(B)所示，在导电层(第1导电层)34及电极14上形成导电层(第2导电层)36。导电层36的内容与导电层34的内容相同。导电层36也可以形成至钝化膜18上。形成导电层36时也可以不堵塞贯通孔30。即在导电层36上形成与贯通孔30连通的孔。
如图2(C)所示形成抗蚀膜40。抗蚀膜40构图具有开口42。开口42与贯通孔30重叠。除贯通孔30内的区域之外，抗蚀膜40也可以覆盖导电层34、36。
如图2(D)所示，向贯通孔30内供给导电材料形成导电层(第3导电层)38。导电层38也可以由例如Cu形成。导电层38也可以由无电解镀膜或喷墨方式形成。导电层38也可以比与半导体基片10上形成电极14的第1面相反侧的第2面(例如绝缘层32或导电层34的表面)突出。
通过以上工序，可以形成导电部44。导电部44是为了电连接半导体基片10的两面形成的。在本实施例中，由导电层34、36、38构成导电部44。贯通电极44从锥形开口向形成了绝缘层32的贯通孔30供给导电材料。这样可以从大的开口供给导电材料，容易形成导电部44。
如图3(A)所示，去除抗蚀膜40，也可以如图3(B)所示形成其他的抗蚀膜50。抗蚀膜50构图具有开口52。形成开口52时至少与电极14有部分重叠。除去电极14的至少一部分之外，抗蚀膜50也可以覆盖导电层34、36、38。在开口52内(电极14或其上形成的导电层36上)形成导电层(第4导电层)54。导电层54也可以采用无电解镀膜或喷墨方式形成。导电层54也可以比与半导体基片10上了形成电极14的第1面(例如钝化膜18或导电层36的表面)突出。
如图3(C)所示去除抗蚀膜50。另外，导电层38作为掩模，也可以去除(例如刻蚀)其下面形成的导电层34的一部分(导电层38的外侧部分)。同样，导电层54作为掩模，也可以去除(例如刻蚀)其下面形成的导电层36的一部分(导电层54的外侧部分)。
如图3(D)所示，也可以在导电部44(或导电层38)上设置钎焊材料(软钎料或硬钎料)56。钎焊材料56也可以设置在电极14侧的导电层54上。
通过以上工序，可以形成贯通电极60。在本实施例中，贯通电极60具有导电部44(导电层34、36、38)及导电层54，也可以具有钎焊材料56。贯通电极60可以贯通半导体基片10，在形成了电极14的第1面和其相反侧的第2面之间电连接。贯通电极60也可以从半导体基片10的两面突出来。贯通电极60贯通电极14，与电极14电连接。贯通电极60设置在半导体基片10的贯通孔30(参照图1(D))的内侧。半导体基片10的基材和贯通电极60之间，通过绝缘层32电绝缘。
如图4所示，半导体基片10是半导体晶片时，也可以分别对应各自的集成电路12(参照图1(A))形成贯通孔30，形成贯通电极60，切断(例如切割)半导体基片10。切断时也可以使用刀具(例如切割机)70或激光(例如CO2激光、YAG激光等)。
通过以上工序，可以制造半导体装置。半导体装置具有半导体基片10。在半导体基片10上形成从开口向纵深方向逐渐变细的锥形贯通孔30。在贯通孔30的内面形成绝缘层32。在绝缘层32的内侧形成导电部44。其他构成为通过上述制造方法得到的内容。
另外，也可以如图5所示层积根据上述方法制造的多个半导体装置，通过贯通电极60分别进行电连接。本实施例有利于进行这种三维立体封装。如图5所示的半导体装置具有多个半导体基片10。位于电极14(第1面)方向上最外侧(图5中最下方)的半导体基片10具有外部端子(例如锡球)62。外部端子62设置在形成于树脂层(例如应力缓冲层)64的布线66上。布线66在电极14侧连接于贯通电极60。
图6表示封装了层积有多个半导体芯片的半导体装置1的电路基片1000。多个半导体芯片通过上述贯通电极60电连接。作为具有上述半导体装置的电子仪器，图7表示笔记本型个人计算机2000，图8表示移动电话机3000。
本发明不限定于以上实施例，可以有多种变形。例如：本发明包括实质上与实施例中说明的结构相同的结构。例如：功能、方法及结果相同的结构，或目的及结果相同的结构。本方法还包括置换了实施例中说明的结构中非本质部分的结构。另外，本发明包括与在实施例中说明的结构具有相同作用效果的结构，或者可以达成同一目的的结构。此外，本发明包括在实施例中说明的结构上附加公知技术的结构。

Claims (13)

1.一种半导体装置的制造方法，其特征在于：
包括：
(a)在形成了集成电路的半导体基片上形成从开口向纵深方向逐渐变细的锥形贯通孔；
(b)从上述开口向上述贯通孔供给绝缘材料，在上述贯通孔的内面形成绝缘层；
(c)从上述开口向形成了上述绝缘层的上述贯通孔供给导电材料，在上述绝缘层的内侧形成导电部。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于：
采用包括喷砂的方法形成上述贯通孔。
3.根据权利要求2所述的半导体装置的制造方法，其特征在于：
在上述半导体基片上形成利用上述喷砂方法形成的锥形凹部，对上述凹部的底面进行激光加工，形成上述贯通孔。
4.根据权利要求1～3中任意一项所述的半导体装置的制造方法，其特征在于：
上述半导体基片的第1面具有电极；
上述贯通孔，形成在与上述半导体基片上形成了上述电极的第1面相反侧的第2面上。
5.根据权利要求4所述的半导体装置的制造方法，其特征在于：
上述贯通孔可以贯通上述电极。
6.根据权利要求1～3中任意一项所述的半导体装置的制造方法，其特征在于：
形成上述贯通孔时，使上述半导体基片的表面与上述贯通孔的内壁面之间的角度为70℃以上90℃以下。
7.根据权利要求1～3中任意一项所述的半导体装置的制造方法，其特征在于：
上述半导体基片是半导体晶片，多个上述集成电路形成在上述半导体基片上，分别对应上述多个集成电路形成上述导电部。
另外包括在上述(c)工序后，切断上述半导体基片。
8.一种半导体装置的制造方法，包括：
层积根据权利要求1～3中任意一项所述的半导体装置的制造方法制造的多个上述半导体装置，通过上述导电部进行电连接。
9.一种半导体装置，其特征在于：
根据权利要求1～3中任意一项所述的方法制造。
10.一种半导体装置，其特征在于：
具有：
集成电路；
半导体基片，形成有从开口向纵深方向逐渐变细的锥形贯通孔；
设置于上述贯通孔内面的绝缘层；
设置于上述绝缘层内侧的导电部。
11.一种半导体装置，其特征在于：
具有权利要求10中所述的多个半导体装置；
层积上述多个半导体，通过上述导电部电连接。
12.一种电路基片，其特征在于：
封装了权利要求10或11中所述的半导体装置。
13.一种电子仪器，其特征在于：
具有权利要求10或11中所述的半导体装置。
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CN104054164A (zh) * 2012-01-06 2014-09-17 凸版印刷株式会社 半导体装置及其制造方法

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