JP5826782B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5826782B2 JP5826782B2 JP2013056586A JP2013056586A JP5826782B2 JP 5826782 B2 JP5826782 B2 JP 5826782B2 JP 2013056586 A JP2013056586 A JP 2013056586A JP 2013056586 A JP2013056586 A JP 2013056586A JP 5826782 B2 JP5826782 B2 JP 5826782B2
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Description
Claims (1)
- 基板の裏面に導電性膜を形成する工程と、
前記基板の表裏を貫通し、前記導電性膜に達する貫通孔を形成する工程と、
前記貫通孔の内壁面、前記導電性膜の前記貫通孔から露出した面および前記基板の表面に銅を含むシード膜を形成する工程と、
電解メッキ法を用いて、前記基板の表裏を貫通する貫通孔の一方の端面から他方の端面へ向けて銅を含む第1の金属層をボトムアップ成長させて、前記他方の端面から前記貫通孔の半径以下の深さまでを残して前記貫通孔を埋める工程と、
電解メッキ法を用いて、前記第1の金属層によって前記一方の端面から中途部までが埋められた前記貫通孔の内周面からニッケルを含む第2の金属層をコンフォーマル成長させて、前記第2の金属層の頂面を前記他方の端面から突出させる工程と、
前記第2の金属層の頂面に第3の金属層を形成する工程と、
前記第3の金属層をマスクとして前記シード膜をエッチングする工程と、
前記第3の金属層を熱溶融させて成形する工程と
を含むことを特徴とする半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013056586A JP5826782B2 (ja) | 2013-03-19 | 2013-03-19 | 半導体装置の製造方法 |
TW102129164A TWI529854B (zh) | 2013-03-19 | 2013-08-14 | Semiconductor device manufacturing method and semiconductor device |
CN201310365786.2A CN104064513B (zh) | 2013-03-19 | 2013-08-21 | 半导体装置的制造方法及半导体装置 |
US14/015,799 US20140284772A1 (en) | 2013-03-19 | 2013-08-30 | Semiconductor device manufacturing method and semiconductor device thereof |
US14/883,701 US20160035624A1 (en) | 2013-03-19 | 2015-10-15 | Semiconductor device manufacturing method and semiconductor device thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2013056586A JP5826782B2 (ja) | 2013-03-19 | 2013-03-19 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2014183185A JP2014183185A (ja) | 2014-09-29 |
JP5826782B2 true JP5826782B2 (ja) | 2015-12-02 |
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Application Number | Title | Priority Date | Filing Date |
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JP2013056586A Active JP5826782B2 (ja) | 2013-03-19 | 2013-03-19 | 半導体装置の製造方法 |
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US (2) | US20140284772A1 (ja) |
JP (1) | JP5826782B2 (ja) |
CN (1) | CN104064513B (ja) |
TW (1) | TWI529854B (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10256142B2 (en) | 2009-08-04 | 2019-04-09 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
US11437269B2 (en) | 2012-03-27 | 2022-09-06 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
US10083893B2 (en) * | 2014-01-30 | 2018-09-25 | Toshiba Memory Corporation | Semiconductor device and semiconductor device manufacturing method |
JP6113679B2 (ja) * | 2014-03-14 | 2017-04-12 | 株式会社東芝 | 半導体装置 |
US9997405B2 (en) | 2014-09-30 | 2018-06-12 | Lam Research Corporation | Feature fill with nucleation inhibition |
JP6561635B2 (ja) * | 2015-07-09 | 2019-08-21 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法 |
TWI680535B (zh) * | 2016-06-14 | 2019-12-21 | 美商應用材料股份有限公司 | 金屬及含金屬化合物之氧化體積膨脹 |
US10573522B2 (en) | 2016-08-16 | 2020-02-25 | Lam Research Corporation | Method for preventing line bending during metal fill process |
JP6963396B2 (ja) | 2017-02-28 | 2021-11-10 | キヤノン株式会社 | 電子部品の製造方法 |
US11043558B2 (en) | 2018-10-31 | 2021-06-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source/drain metal contact and formation thereof |
US11978666B2 (en) | 2018-12-05 | 2024-05-07 | Lam Research Corporation | Void free low stress fill |
CN110767604B (zh) * | 2019-10-31 | 2022-03-18 | 厦门市三安集成电路有限公司 | 化合物半导体器件和化合物半导体器件的背面铜制程方法 |
CN110808229B (zh) * | 2019-11-15 | 2022-02-01 | 北京航空航天大学 | 一种硅基上高深宽比微纳通孔的填充方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3018050B2 (ja) * | 1991-11-15 | 2000-03-13 | ローム株式会社 | 半導体装置およびその製造方法 |
JP3951091B2 (ja) * | 2000-08-04 | 2007-08-01 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
US6599778B2 (en) * | 2001-12-19 | 2003-07-29 | International Business Machines Corporation | Chip and wafer integration process using vertical connections |
JP2003318178A (ja) * | 2002-04-24 | 2003-11-07 | Seiko Epson Corp | 半導体装置及びその製造方法、回路基板並びに電子機器 |
JP2004095849A (ja) * | 2002-08-30 | 2004-03-25 | Fujikura Ltd | 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法 |
US7060601B2 (en) * | 2003-12-17 | 2006-06-13 | Tru-Si Technologies, Inc. | Packaging substrates for integrated circuits and soldering methods |
US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
JP4937842B2 (ja) * | 2007-06-06 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5089336B2 (ja) * | 2007-10-29 | 2012-12-05 | 新光電気工業株式会社 | パッケージ用シリコン基板 |
US8784636B2 (en) * | 2007-12-04 | 2014-07-22 | Ebara Corporation | Plating apparatus and plating method |
US8138577B2 (en) * | 2008-03-27 | 2012-03-20 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | Pulse-laser bonding method for through-silicon-via based stacking of electronic components |
JP5308145B2 (ja) * | 2008-12-19 | 2013-10-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2011014728A (ja) * | 2009-07-02 | 2011-01-20 | Casio Computer Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP5730654B2 (ja) * | 2010-06-24 | 2015-06-10 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
JP2012231096A (ja) * | 2011-04-27 | 2012-11-22 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US9646942B2 (en) * | 2012-02-23 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for controlling bump height variation |
KR20140011137A (ko) * | 2012-07-17 | 2014-01-28 | 삼성전자주식회사 | Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법 |
US8940631B1 (en) * | 2013-03-15 | 2015-01-27 | Maxim Integrated Products, Inc. | Methods of forming coaxial feedthroughs for 3D integrated circuits |
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- 2013-08-14 TW TW102129164A patent/TWI529854B/zh active
- 2013-08-21 CN CN201310365786.2A patent/CN104064513B/zh active Active
- 2013-08-30 US US14/015,799 patent/US20140284772A1/en not_active Abandoned
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TW201438145A (zh) | 2014-10-01 |
JP2014183185A (ja) | 2014-09-29 |
US20160035624A1 (en) | 2016-02-04 |
CN104064513A (zh) | 2014-09-24 |
US20140284772A1 (en) | 2014-09-25 |
TWI529854B (zh) | 2016-04-11 |
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