TWI731947B - 半導體元件及其製造方法 - Google Patents

半導體元件及其製造方法 Download PDF

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TWI731947B
TWI731947B TW106107860A TW106107860A TWI731947B TW I731947 B TWI731947 B TW I731947B TW 106107860 A TW106107860 A TW 106107860A TW 106107860 A TW106107860 A TW 106107860A TW I731947 B TWI731947 B TW I731947B
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Taiwan
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copper layer
layer
copper
semiconductor device
pad
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TW106107860A
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TW201810579A (zh
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崔朱逸
金孝柱
文光辰
朴秀晶
徐柱斌
李來寅
李鎬珍
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南韓商三星電子股份有限公司
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Publication of TW201810579A publication Critical patent/TW201810579A/zh
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    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item

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Abstract

本發明提供一種半導體元件及其製造方法。所述半導體元 件的構件如下所述。墊安置於基板上。凸塊結構安置於所述墊上且電性連接至所述墊。所述凸塊結構包括：第一銅層及第二銅層，依序堆疊於所述墊上；以及焊料球，位於所述第二銅層上。所述第一銅層的(111)平面對(200)平面的第一X射線繞射(XRD)峰值強度比率大於所述第二銅層的(111)平面對(200)平面的第二X射線繞射峰值強度比率。

Description

半導體元件及其製造方法 [相關申請案的交叉參考]
本申請案根據35 U.S.C.§119主張於2016年6月14日在韓國智慧財產局提出申請的韓國專利申請案第10-2016-0073958號的優先權，所述韓國專利申請案的揭露內容全文併入本案供參考。
本發明概念是有關於一種半導體元件及其製造方法。
半導體元件包括提供通往其他半導體元件或印刷電路板的電連接路徑的電連接結構(例如焊料球或焊料凸塊)。
根據本發明概念的示例性實施例，提供如下一種半導體元件。墊安置於基板上。凸塊結構安置於所述墊上且電性連接至所述墊。所述凸塊結構包括：第一銅層及第二銅層，依序堆疊於所述 墊上；以及焊料球，位於所述第二銅層上。所述第一銅層的(111)平面對(200)平面的第一X射線繞射(X-ray diffraction，XRD)峰值強度比率大於所述第二銅層的(111)平面對(200)平面的第二X射線繞射峰值強度比率。
根據本發明概念的示例性實施例，提供如下一種半導體元件。墊安置於基板上。凸塊結構安置於所述墊上且電性連接至所述墊。所述凸塊結構包括：第一銅層及第二銅層，依序堆疊於所述墊上；以及焊料球，位於所述第二銅層上。所述第一銅層中的孿晶界密度(twin boundary density)大於所述第二銅層中的孿晶界密度。
根據本發明概念的示例性實施例，提供如下一種製造半導體元件的方法。在基板上形成墊。形成電性連接至所述墊的凸塊下層。在所述凸塊下層上形成具有開口的遮罩圖案。在所述開口中依序形成第一銅層、第二銅層及焊料層。移除所述遮罩圖案。執行濕蝕刻製程以蝕刻所述凸塊下層的一部分。所述第一銅層是使用脈波式鍍覆製程(pulse-plating process)形成。所述第二銅層是使用直流鍍覆製程(DC plating process)形成。
根據本發明概念的示例性實施例，提供如下一種製造半導體元件的方法。在基板上形成墊。在所述墊上形成凸塊下層。藉由在所述凸塊下層上以第一生長速率電鍍第一銅層而形成所述第一銅層。藉由在所述第一銅層上以第二生長速率電鍍第二銅層而形成所述第二銅層。所述第二生長速率大於所述第一生長速率。所 述第二銅層上有焊料層。對所述凸塊下層執行濕蝕刻製程。蝕刻所述凸塊下層以形成凸塊下圖案。
10、11、12:電連接部
100:半導體元件/第一半導體元件
101:半導體元件/第二半導體元件
110:基板
112:墊
114:絕緣層
116:附加墊
120:凸塊下圖案
120L:凸塊下層
122:障壁圖案
122L:障壁層
122_W、124_W、132_W、134_W、136_W、138_W、UC_W:寬度
124:晶種圖案
124L:晶種層
130:凸塊結構
132:第一銅層
132_S1:第一側壁
132_S2:第二側壁
132_TH、134_TH、136_TH、138_TH:厚度
134:第二銅層
136:鎳層
138:第三銅層
200:半導體封裝
201:半導體封裝
210:封裝基板
212:連接墊
214:外墊
216:外端子
220:模具層
A、B:部分
CD1:第一電流密度
CD2:第二電流密度
MP:遮罩圖案
MP_O:開口
SDB:焊料球
SDL:焊料層
Toff:斷開階段的持續時間
Ton:接通階段的持續時間
TSV:貫穿式電極
UC:底切區
UC_D:深度
藉由參照附圖來詳細闡述本發明概念的示例性實施例，本發明概念的該些及其他特徵將變得更顯而易見，在附圖中：圖1A是說明根據本發明概念示例性實施例的半導體元件的一部分的剖視圖。
圖1B是圖1A所示一部分‘A’的放大圖。
圖2及圖3是說明根據本發明概念示例性實施例的半導體元件的一部分的剖視圖。
圖4A是說明根據本發明概念示例性實施例的半導體元件的剖視圖。
圖4B及圖4C是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。
圖5A至圖5D是說明根據本發明概念示例性實施例的製造半導體元件的方法的剖視圖。
圖5E是圖5A所示一部分‘B’的放大圖。
圖6A是示出在用於形成第一銅層的脈波式鍍覆製程中電流密度隨時間變化的曲線圖。
圖6B是示出在用於形成第二銅層的直流鍍覆製程中電流密度隨時間變化的曲線圖。
圖7A至圖7B是說明根據本發明概念示例性實施例的製造半導體元件的方法的剖視圖。
圖8A至圖8B是說明根據本發明概念示例性實施例的製造半導體元件的方法的剖視圖。
圖9A是示出藉由傳統製程而形成的銅層的底切區(under-cut region)的影像。
圖9B是示出藉由根據本發明概念示例性實施例的方法而形成的銅層的底切區的影像。
圖1A是說明根據本發明概念示例性實施例的半導體元件的一部分的剖視圖。圖1B是圖1A所示一部分‘A’的放大圖。
參照圖1A及圖1B，半導體元件可包括安置於基板110上的電連接部10。基板110可為或可包括半導體基板(例如矽晶圓或鍺晶圓)。墊112可安置於基板110的表面上。絕緣層114可安置於墊112上。絕緣層114可具有開口，墊112通過所述開口而被暴露出。墊112可例如由鋁形成或例如包含鋁。絕緣層114可例如由氧化矽、氮化矽或氮氧化矽形成或例如包含氧化矽、氮化矽或氮氧化矽。記憶體電路或邏輯電路中的至少一者可形成於基板110上並電性連接至墊112。
電連接部10可包括安置於墊112上的凸塊結構130及安置於墊112與凸塊結構130之間的凸塊下圖案120。凸塊結構130 可藉由凸塊下圖案120而電性連接至墊112。
凸塊下圖案120可被安置成具有單層結構或多層結構。在示例性實施例中，如圖1B中所示，凸塊下圖案120可為依序堆疊有障壁圖案122及晶種圖案124的多層結構。障壁圖案122可防止或抑制凸塊結構130中的金屬原子擴散至墊112中。舉例而言，障壁圖案122可由鉭、鈦、氮化鉭或氮化鈦形成或包含鉭、鈦、氮化鉭或氮化鈦。晶種圖案124可在形成第一銅層132的製程中用作晶種層且可由銅形成或包含銅。障壁圖案122的寬度122_W可大於晶種圖案124的寬度124_W。在示例性實施例中，凸塊下圖案120可為導電的。
凸塊結構130可包括第一銅層132、第二銅層134及焊料球SDB。第一銅層132及第二銅層134可依序堆疊於凸塊下圖案120上，且焊料球SDB可安置於第二銅層134上。在示例性實施例中，第一銅層132可接觸第二銅層134。
第一銅層132可包括第一側壁132_S1及第二側壁132_S2。第一側壁132S1及障壁圖案122可界定底切區UC。底切區UC可為在側向上自第二側壁132_S2向內凹陷的區。底切區UC可被形成為鄰近於凸塊下圖案120。如圖1A及圖1B中所示，第一銅層132所具有厚度132_TH可使得底切區UC可局部地形成於第一銅層132的第一側壁132S1下方的情形。本發明概念並非僅限於此。在示例性實施例中，底切區UC的形成可因第一銅層132的蝕刻速率低於第二銅層134的蝕刻速率而被抑制。不同於圖1A及圖 1B中所示者，若第一銅層132的厚度132_TH為小的，則底切區UC可被形成為貫穿第一銅層132的側壁。
重新參照圖1B，底切區UC的深度UC_D可在側向上自第二側壁132_S2的延伸線至第一側壁132_S1量測。
在示例性實施例中，深度UC_D可自障壁圖案122的上表面向上減小。舉例而言，深度UC_D的最大深度可介於約0.2微米(μm)至約0.6微米範圍內。
在示例性實施例中，第一銅層132的寬度UC_W可自晶種圖案124的上表面向上增大。與底切區UC接觸的第一銅層132的寬度UC_W可小於凸塊下圖案120的寬度(例如障壁圖案122的寬度122_W)。
第一銅層132的厚度132_TH可小於第二銅層134的厚度134_TH。在示例性實施例中，第一銅層132的厚度132_TH可小於第二銅層134的厚度134_TH的約0.2倍。舉例而言，第一銅層132的厚度132_TH可介於約0.5微米至約3微米範圍內，且第二銅層134的厚度134_TH可介於10微米至30微米範圍內。
第一銅層132及第二銅層134中的每一者可具有多晶結構。舉例而言，第一銅層132及第二銅層134中的每一者可包括(111)平面及(200)平面。第一銅層132中的(111)平面對(200)平面的X射線繞射(XRD)峰值強度比率可大於第二銅層134中的(111)平面對(200)平面的X射線繞射峰值強度比率。此可乃因如下所述：第一銅層132是使用脈波式鍍覆製程形成，而第 二銅層134則是使用直流鍍覆製程形成。在示例性實施例中，第一銅層132中的(111)平面對(200)平面的X射線繞射峰值強度比率可大於第二銅層134中的(111)平面對(200)平面的X射線繞射峰值強度比率的二倍。在示例性實施例中，第一銅層132中的(111)平面對(200)平面的X射線繞射峰值強度比率可小於第二銅層134中的(111)平面對(200)平面的X射線繞射峰值強度比率的100倍。在每一銅層中，(111)平面對(200)平面的X射線繞射峰值強度比率可藉由自每一銅層的(111)平面及(200)平面量測X射線繞射強度並將其進行比較來獲得。
第一銅層132中的孿晶界密度可高於所述第二銅層134中的孿晶界密度。孿晶界密度可被定義為每單位面積中孿晶界的面積、長度或數目。
當使用濕蝕刻溶液時，第一銅層132中的銅可以較第二銅層134中的銅的蝕刻速率低的蝕刻速率被蝕刻。此可乃因第一銅層132中的(111)平面對(200)平面的X射線繞射峰值強度比率可大於第二銅層134中的(111)平面對(200)平面的X射線繞射峰值強度比率。此可乃因第一銅層132中的孿晶界密度可高於第二銅層134中的孿晶界密度。在示例性實施例中，當使用含有過氧化氫(H2O2)及磷酸(H3PO4)的濕蝕刻溶液或含有過氧化氫(H2O2)及檸檬酸(C6H8O7)的濕蝕刻溶液來蝕刻第一銅層132及第二銅層134時，第一銅層132的銅蝕刻速率可低於第二銅層134的銅蝕刻速率的0.5倍。將參照圖9A及圖9B來對此予以 更詳細闡述。
焊料球SDB可安置於第二銅層134上。焊料球SDB可例如由錫、銀、銅、鋅、鉛或其合金中的至少一者形成或例如包含錫、銀、銅、鋅、鉛或其合金中的至少一者。在示例性實施例中，焊料球SDB可接觸第二銅層134。
圖2是說明根據本發明概念示例性實施例的半導體元件的一部分的剖視圖。
參照圖2，半導體元件可包括安置於基板110上的電連接部11。為說明簡潔起見，可藉由相似的或相同的參考編號來辨識先前參照圖1A及圖1B所述的組件，而不再對其予以贅述。因此，以下說明著重於凸塊結構130。
凸塊結構130可包括第一銅層132、第二銅層134、焊料球SDB及鎳層136。第一銅層132、第二銅層134及焊料球SDB可與參照圖1A及圖1B所述者相同。
鎳層136可安置於第二銅層134與焊料球SDB之間。鎳層136的厚度136_TH可小於第二銅層134的厚度(例如圖1A所示的134_TH)。舉例而言，鎳層136的厚度136_TH可為約3微米。鎳層136的寬度136_W可大於第一銅層132的寬度132_W及第二銅層134的寬度134_W。在示例性實施例中，鎳層136、第一銅層132及第二銅層134可為實質上同心的。
圖3是說明根據本發明概念示例性實施例的半導體元件的一部分的剖視圖。
參照圖3，半導體元件可包括安置於基板110上的電連接部12。為說明簡潔起見，可藉由相似的或相同的參考編號來辨識先前參照圖1A、圖1B及圖2所述的組件，而不再對其予以贅述。以下說明著重於凸塊結構130。
凸塊結構130可包括第一銅層132、第二銅層134、鎳層136、焊料球SDB及第三銅層138。第一銅層132、第二銅層134、鎳層136及焊料球SDB可被配置成具有與參照圖1A、圖1B及圖2所述者相同的要件。
第三銅層138可安置於鎳層136與焊料球SDB之間。第三銅層138的厚度138_TH可小於鎳層136的厚度136_TH。舉例而言，第三銅層138的厚度138_TH可小於1微米。
第三銅層138可被安置成具有與第二銅層134的材料特性相似的材料特性。第三銅層138中的(111)平面對(200)平面的X射線繞射峰值強度比率可小於第一銅層132中的(111)平面對(200)平面的X射線繞射峰值強度比率。在示例性實施例中，第三銅層138中的(111)平面對(200)平面的X射線繞射峰值強度比率可小於第一銅層132中的(111)平面對(200)平面的X射線繞射峰值強度比率的約0.5倍。第三銅層138中的孿晶界密度可小於第一銅層132中的孿晶界密度。
當使用濕蝕刻溶液時，第三銅層138的銅蝕刻速率可高於第一銅層132的銅蝕刻速率。此可乃因第三銅層138中的(111)平面對(200)平面的X射線繞射峰值強度比率可小於第一銅層 132中的X射線繞射峰值強度比率。此乃因第三銅層138中的孿晶界密度可小於第一銅層132中的孿晶界密度。在示例性實施例中，當使用含有過氧化氫(H2O2)及磷酸(H3PO4)的濕蝕刻溶液或含有過氧化氫(H2O2)及檸檬酸(C6H8O7)的濕蝕刻溶液來蝕刻第三銅層138及第一銅層132時，第三銅層138的銅蝕刻速率可高於第一銅層132的銅蝕刻速率的二倍。
圖4A是說明根據本發明概念示例性實施例的半導體元件的剖視圖。
參照圖4A，半導體元件100可包括基板110及電連接部10。
基板110可包括安置於基板110的表面上的多個墊112及被圖案化以暴露出墊112的絕緣層114。在示例性實施例中，如圖4A中所示，墊112可均勻地安置於基板110的整個頂表面上。在某些實施例中，不同於圖4A中所示，墊112可安置於基板110的邊緣或中心區上。記憶體電路或邏輯電路中的至少一者可形成於基板110上且可電性連接至墊112。在示例性實施例中，墊112可埋置於基板中，使得墊112的上表面與基板110的上表面實質上共面。
各電連接部10可分別安置於各墊112上。電連接部10中的每一者可包括安置於墊112上的凸塊結構及安置於墊112與所述凸塊結構之間的凸塊下圖案。在示例性實施例中，如圖4A中所示，電連接部10中的每一者可與圖1A及圖1B所示電連接部 10相同。在示例性實施例中，電連接部10中的每一者可與圖2所示電連接部11或圖3所示電連接部12相同。
圖4B是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。
參照圖4B，半導體封裝200可包括封裝基板210及安裝於封裝基板210上的半導體元件100。半導體元件100可與參照圖4A所述者相同。
封裝基板210可包括安置於封裝基板210的頂表面上的連接墊212及安置於封裝基板210的底表面上的外墊214。外墊214上可安置有外端子216。
半導體元件100可以倒裝晶片結合(flip-chip bonding)方式安裝於封裝基板210上。半導體元件100可以使得電連接部10面對封裝基板210的頂表面的方式對準，且電連接部10可耦合至連接墊212。舉例而言，可執行焊接製程(soldering process)以對位於連接墊212上的電連接部10中的每一者中的焊料球(例如圖1A中的SDB)進行焊接，且因此，半導體元件100可安裝於封裝基板210上。舉例而言，焊料球SDB可使用所述焊接製程而附接至連接墊212。
電連接部10中的每一者可與圖2所示電連接部11或圖3所示電連接部12相同。
模具層220可安置於封裝基板210的頂表面上以覆蓋半導體元件100。舉例而言，模具層220可由環氧樹脂模製化合物 (epoxy molding compound)形成或包含環氧樹脂模製化合物。在示例性實施例中，底部填充層(圖中未示出)可進一步安置於半導體元件100與封裝基板210之間。
圖4C是說明根據本發明概念示例性實施例的半導體封裝的剖視圖。
參照圖4C，半導體封裝201可包括封裝基板210及安裝於封裝基板210上的半導體元件100及半導體元件101。
封裝基板210可與參照圖4B所述者相同。將不再對封裝基板210予以贅述。
半導體元件100及半導體元件101可安裝於封裝基板210的頂表面上。舉例而言，第一半導體元件100可安置於封裝基板210的頂表面上，且第二半導體元件101可安置於第一半導體元件100與封裝基板210之間。第一半導體元件100可與參照圖4A所述半導體元件100實質上相同。第二半導體元件101中的每一者可更包括穿透基板110的貫穿式電極(through electrode)TSV及面對墊112且連接至所述貫穿式電極TSV的附加墊116，且除該些構件以外，第二半導體元件101中的每一者可與參照圖4A所述半導體元件100相同。
第一半導體元件100可電性連接至位於其之下的第二半導體元件101。舉例而言，第一半導體元件100的電連接部10可耦合至位於其之下的第二半導體元件101的附加墊116。
第二半導體元件101中的每一者可電性連接至位於其之 下的第二半導體元件101或電性連接至封裝基板210。舉例而言，第二半導體元件101中位於最下側的第二半導體元件的電連接部10可耦合至封裝基板210的連接墊212，且第二半導體元件101中的其他第二半導體元件的電連接部10可耦合至位於其之下的第二半導體元件101的附加墊116。
電連接部10中的每一者可與圖2所示電連接部11或圖3所示電連接部12實質上相同。
模具層220可安置於封裝基板210的頂表面上以覆蓋半導體元件100及半導體元件101。在示例性實施例中，底部填充層(圖中未示出)可進一步安置於半導體元件100與半導體元件101之間以及第二半導體元件101中位於最下側的第二半導體元件與封裝基板210之間。
圖5A至圖5D說明根據本發明概念示例性實施例的製造半導體元件的方法的剖視圖。圖5E是圖5A所示一部分‘B’的放大圖。圖6A是示出在用於形成第一銅層的脈波式鍍覆製程中電流密度隨時間變化的曲線圖。圖6B是示出在用於形成第二銅層的直流鍍覆製程中電流密度隨時間變化的曲線圖。
參照圖5A，可設置基板110。基板110可為或可包括半導體基板(例如矽晶圓或鍺晶圓)。基板110可包括安置於基板110的表面上的墊112及被圖案化以暴露出墊112的絕緣層114。可在基板110上形成記憶體電路或邏輯電路中的至少一者且所述至少一者可電性連接至墊112。
可在基板110的表面上形成凸塊下層120L。可將凸塊下層120L形成為覆蓋被絕緣層114暴露出的墊112且被形成為延伸成覆蓋絕緣層114。在示例性實施例中，如圖5E中所示，形成凸塊下層120L可包括依序沈積障壁層122L及晶種層124L。舉例而言，障壁層122L可由鉭、鈦、氮化鉭或氮化鈦形成或包含鉭、鈦、氮化鉭或氮化鈦，且晶種層124L可由銅形成或包含銅。凸塊下層120L可例如使用物理氣相沈積(physical vapor deposition，PVD)製程形成。
參照圖5B，可在凸塊下層120L上形成具有開口MP_O的遮罩圖案MP。當在平面圖中觀察時，開口MP_O可與墊112重疊且可將開口MP_O形成為暴露出凸塊下層120L。在示例性實施例中，形成遮罩圖案MP可包括塗佈光阻劑層(圖中未示出)並使用光刻製程(photolithography process)將所述光阻劑層圖案化。
參照圖5C，可在開口MP_O中依序形成第一銅層132、第二銅層134及焊料層SDL。
參照圖5C及圖6A，可在凸塊下層120L上形成第一銅層132。可使用脈波式鍍覆製程來形成第一銅層132。舉例而言，如圖6A中所示，可藉由使用脈波電流的鍍覆製程來形成第一銅層132。可在脈波式鍍覆製程中使用晶種層124L作為晶種。脈波式鍍覆製程可包括多個接通階段及多個斷開階段，在所述多個接通階段中將電流供應至鍍覆系統，在所述多個斷開階段中將電流中斷，且可在所述脈波式鍍覆製程中交替地且重複地執行所述接通 階段及斷開階段。脈波式鍍覆製程的負載循環可介於約5%至約50%範圍內。此處，參照圖6A，負載循環可由方程式(Ton)/(Ton+Toff)給出，其中Ton為接通階段的持續時間且Toff是斷開階段的持續時間。在脈波式鍍覆製程的接通階段期間，所供應電流可具有第一電流密度CD1。第一銅層132的厚度可大於欲參照圖5D闡述的底切區UC的深度。此外，第一銅層132的厚度可小於欲在以下闡述的第二銅層134的厚度的約0.2倍。在示例性實施例中，可將第一銅層132形成為具有為約0.5微米至約3微米的厚度。
參照圖5C及圖6B，可在第一銅層132上形成第二銅層134。可使用直流鍍覆製程來形成第二銅層134。舉例而言，如圖6B中所示，可藉由使用直流電流的鍍覆製程來形成第二銅層134。舉例而言，可供應為第二電流密度CD2的直流電流以形成第二銅層134。在示例性實施例中，第二電流密度CD2可小於第一電流密度CD1。舉例而言，第二電流密度CD2可介於第一電流密度CD1的約5%至約50%範圍內。在示例性實施例中，用於形成第二銅層134的直流鍍覆製程中的第二電流密度CD2可與用於形成第一銅層132的脈波式鍍覆製程中的平均電流密度(即，(CD1*Ton)/(Ton+Toff))實質上相同。可將第二銅層134形成為具有較第一銅層132的厚度大的厚度。舉例而言，可將第二銅層134形成為具有為10微米至30微米的厚度。
如上所述，可使用脈波式鍍覆製程來形成第一銅層132，而可使用直流鍍覆製程來形成第二銅層134。此可使得第一銅層 132能夠相較於第二銅層134而言具有更高的(111)平面對(200)平面的X射線繞射峰值強度比率及更高的孿晶界密度。此外，此可使得第一銅層132的耐蝕性具有較第二銅層134的耐蝕性(corrosion resistance)高。舉例而言，在使用含有過氧化氫(H2O2)及磷酸(H3PO4)的濕蝕刻溶液或含有過氧化氫(H2O2)及檸檬酸(C6H8O7)的濕蝕刻溶液來執行蝕刻製程的情形中，第一銅層132的銅蝕刻速率可低於第二銅層134的銅蝕刻速率的約0.5倍。第一銅層132的生長速率(每單位時間)可小於第二銅層134的生長速率。
參照圖5C，可在第二銅層134上形成焊料層SDL。可使用直流鍍覆製程來形成焊料層SDL。在示例性實施例中，可以原位(in-situ)方式執行用於形成第一銅層132、第二銅層134及焊料層SDL的鍍覆製程。本發明概念並非僅限於此。焊料層SDL可例如由錫、銀、銅、鋅、鉛或其合金形成或例如包含錫、銀、銅、鋅、鉛或其合金。
參照圖5D，可移除遮罩圖案MP。作為移除遮罩圖案MP的結果，凸塊下層120L、第一銅層132及第二銅層134可被暴露出。可使用剝除製程(strip process)來執行移除遮罩圖案MP。
參照圖5D及圖1B，可蝕刻凸塊下層120L以形成凸塊下圖案120。形成凸塊下圖案120可包括對凸塊下層120L執行濕蝕刻製程。在濕蝕刻製程中，晶種層124L的蝕刻速率可因存在電蝕效應(Galvanic corrosion effect)而大於障壁層122L的蝕刻速率。 因此，障壁圖案122的寬度122_W可大於晶種圖案124的寬度124_W。可使用例如含有過氧化氫(H2O2)及磷酸(H3PO4)的濕蝕刻溶液或含有過氧化氫(H2O2)及檸檬酸(C6H8O7)的濕蝕刻溶液來執行所述濕蝕刻製程。
可在濕蝕刻製程期間部分地蝕刻第一銅層132及第二銅層134。因此，第一銅層132的寬度132_W及第二銅層134的寬度134_W可減小。
如上所述，第一銅層132的耐蝕性可較第二銅層134的耐蝕性高。然而，由於存在電蝕效應，因此與凸塊下層120L(或凸塊下圖案120)鄰近的第一銅層132的一部分(例如下部部分)可在濕蝕刻製程期間表現出較第二銅層134的蝕刻速率高的蝕刻速率。因此，可在第一銅層132的側壁上形成底切區UC。如圖5D及圖1B中所示，第一銅層132的厚度132_TH足夠大進而使得可在第一銅層132的下側壁中局部地形成底切區UC。藉由對比，不同於圖5D及圖1B中所示者，若第一銅層132的厚度132_TH為薄的，則可將底切區UC形成為貫穿第一銅層132的側壁。可在側向上自第一銅層132的及第二銅層134的未凹陷的側表面量測底切區UC的深度UC_D。在示例性實施例中，底切區UC的深度UC_D可介於約0.2微米至約0.6微米範圍內。第一銅層132的與底切區UC位於同一水平高度的一部分的寬度UC_W可較障壁圖案122的寬度122_W小。
參照圖1A，可對焊料層SDL執行回焊製程(reflow process)，且如此一來，可形成焊料球SDB。在回焊製程期間，可將第二銅層134中的某些銅原子擴散至焊料球SDB中。
在凸塊下層上形成銅層的情形中，可因在後續濕蝕刻製程中存在電蝕效應而在所述銅層的下部部分中形成底切區。底切區可能導致半導體元件出現故障，且因此，減小所述底切區的大小(例如深度)可為必要的。
根據本發明概念的示例性實施例，可使用脈波式鍍覆製程來形成與凸塊下層120L鄰近的第一銅層132，且此可使得第一銅層132能夠具有較堆疊於第一銅層132上的其他銅層(例如第二銅層134)高的耐蝕性。可使用直流鍍覆製程來形成其他銅層。此外，可將第一銅層132形成為具有較底切區UC的深度UC_D大的厚度。因此，可減小可形成於與凸塊下層120L鄰近的銅層的一部分中的底切區UC的大小。根據本發明概念的示例性實施例，可製造具有提高的可靠性的半導體元件。
當使用脈波式鍍覆製程時的銅層的生長速率可低於當使用直流鍍覆製程時的銅層的生長速率。
根據本發明概念的示例性實施例，可使用直流鍍覆製程來形成所述銅層的除第一銅層132以外的其餘部分(即，第二銅層134)。舉例而言，第一銅層132的厚度132_TH可小於第二銅層134的厚度134_TH的約0.2倍。因此，其可減小因引入脈波式鍍覆製程而增大的總製程時間。
圖7A至圖7B是說明根據本發明概念示例性實施例的製 造半導體元件的方法的剖視圖。可對圖5B所示所得結構執行欲參照圖7A及圖7B闡述的製程。
參照圖7A，可在開口MP_O中依序形成第一銅層132、第二銅層134、鎳層136及焊料層SDL。可藉由與參照圖5C、圖6A及圖6B所述方法相同的方法來形成第一銅層132及第二銅層134，且將不再對其予以贅述。
可在第二銅層134上形成鎳層136。可使用直流鍍覆製程來形成鎳層136。可將鎳層136形成為具有為例如約3微米的厚度。
可在鎳層136上形成焊料層SDL。可使用直流鍍覆製程來形成焊料層SDL。在示例性實施例中，可以原位方式執行用於形成第一銅層132、第二銅層134、鎳層136及焊料層SDL的鍍覆製程。但本發明概念並非僅限於此。
參照圖7B，可移除遮罩圖案MP。作為移除遮罩圖案MP的結果，凸塊下層120L、第一銅層132、第二銅層134及鎳層136可被暴露出。可使用剝除製程來執行移除遮罩圖案MP。
可蝕刻凸塊下層120L以形成凸塊下圖案120。形成凸塊下圖案120可包括對凸塊下層120L執行濕蝕刻製程。如參照圖5D及圖1B所述，可執行濕蝕刻製程以部分地蝕刻凸塊下層120L、第一銅層132及第二銅層134。
在濕蝕刻製程中，鎳層136的蝕刻速率可小於第一銅層132的蝕刻速率及第二銅層134的蝕刻速率。因此，在濕蝕刻製程 之後，如圖7B中所示，鎳層136的寬度136_W可大於第一銅層132的寬度132_W及第二銅層134的寬度134_W。
重新參照圖2，可對焊料層SDL執行回焊製程，且如此一來，可形成焊料球SDB。
圖8A至圖8B是說明根據本發明概念示例性實施例的製造半導體元件的方法的剖視圖。可對圖5B所示所得結構執行欲參照圖8A及圖8B闡述的製程。
參照圖8A，可在開口MP_O中依序形成第一銅層132、第二銅層134、鎳層136、第三銅層138及焊料層SDL。可藉由與參照圖7A所述方法相同的方法來形成第一銅層132、第二銅層134及鎳層136，且將不再對其予以贅述。
可在鎳層136上形成第三銅層138。可使用直流鍍覆製程來形成第三銅層138。可將第三銅層138形成為具有為例如約2微米的厚度。
可在第三銅層138上形成焊料層SDL。可使用直流鍍覆製程來形成焊料層SDL。在示例性實施例中，可以原位方式執行用於形成第一銅層132、第二銅層134、鎳層136、第三銅層138及焊料層SDL的鍍覆製程。但本發明概念並非僅限於此。
參照圖8B，可移除遮罩圖案MP。作為移除遮罩圖案MP的結果，凸塊下層120L、第一銅層132、第二銅層134、鎳層136及第三銅層138可被暴露出。
可蝕刻凸塊下層120L以形成凸塊下圖案120。形成凸塊 下圖案120可包括對凸塊下層120L執行濕蝕刻製程。如參照圖5D及圖1B所述，可執行濕蝕刻製程以部分地蝕刻凸塊下層120L、第一銅層132及第二銅層134。另外，可執行濕蝕刻製程以部分地蝕刻第三銅層138。
在濕蝕刻製程中，鎳層136的蝕刻速率可小於第一銅層、第二銅層134及第三銅層138的蝕刻速率。因此，在濕蝕刻製程之後，鎳層136的寬度136_W可大於第一銅層132的寬度132_W、第二銅層134的寬度134_W及第三銅層138的寬度138_W。
在濕蝕刻製程之後，可對焊料層SDL執行回焊製程，且如此一來，可形成焊料球SDB。在回焊製程期間，可將第三銅層138中所含有的至少一部分銅原子擴散至焊料球SDB中。
在示例性實施例中，可將第三銅層138中所含有的大多數銅原子擴散至焊料球SDB中。在此種情形中，如圖2中所示，第三銅層138無需在回焊製程之後餘留於鎳層136上。
在示例性實施例中，可將第三銅層138中所含有的僅一小部分銅原子擴散至焊料球SDB中。在此種情形中，如圖3中所示，第三銅層138可在回焊製程之後餘留於鎳層136上。
圖9A是示出藉由傳統製程而形成的銅層的底切區的影像。舉例而言，執行了直流鍍覆製程以在凸塊下層上形成銅層及鎳層。此後，使用含有過氧化氫及磷酸的蝕刻溶液執行了為期一分鐘的濕蝕刻製程。如此一來，如圖9A中所示，形成了具有為約1.2微米的深度的底切區。
圖9B是示出藉由根據本發明概念示例性實施例的方法而形成的銅層的底切區的影像。舉例而言，執行了脈波式鍍覆製程以在凸塊下層上形成第一銅層，並接著執行了直流鍍覆製程以形成第二銅層及鎳層。脈波式鍍覆製程中的負載循環為約10%。此後，使用含有過氧化氫及磷酸的蝕刻溶液執行了為期一分鐘的濕蝕刻製程。如此一來，如圖9B中所示，形成了具有為約0.43微米的深度的底切區。
此示出形成於銅層的下部部分處的底切區UC的大小可藉由使用根據本發明概念示例性實施例的方法而得到減小。
根據本發明概念的示例性實施例，與凸塊下層鄰近的銅層的下部部分可使用脈波式鍍覆製程形成，進而使得所述銅層的下部部分能夠具有較使用直流鍍覆製程形成的銅層高的耐蝕性。因此，底切區的大小得到減小或抑制，所述底切區形成於與凸塊下層鄰近的銅層的下部部分中。
根據本發明概念的示例性實施例，堆疊於與凸塊下層鄰近的第一銅層上的其他銅層可使用直流鍍覆製程形成。此可使得能夠減小因引入脈波式鍍覆製程而增大的總製程時間。
儘管已參照本發明概念的示例性實施例示出並闡述了本發明概念，然而對於此項技術中具有通常知識者而言應顯而易見，在不背離如由以下申請專利範圍所界定的本發明概念的精神及範圍的條件下可作出形式及細節上的各種變化。
10:電連接部
110:基板
112:墊
114:絕緣層
120:凸塊下圖案
130:凸塊結構
132:第一銅層
132_TH、134_TH:厚度
134:第二銅層
A:部分
SDB:焊料球
UC:底切區

Claims (25)

  1. 一種半導體元件，包括： 墊，安置於基板上；以及 凸塊結構，安置於所述墊上且電性連接至所述墊， 其中所述凸塊結構包括： 第一銅層及第二銅層，依序堆疊於所述墊上；以及 焊料球，位於所述第二銅層上， 其中所述第一銅層的（111）平面對所述第一銅層的（200）平面的第一X射線繞射峰值強度比率大於所述第二銅層的（111）平面對所述第二銅層的（200）平面的第二X射線繞射峰值強度比率。
  2. 如申請專利範圍第1項所述的半導體元件，其中所述第一銅層的所述第一X射線繞射峰值強度比率大於所述第二銅層的所述第二X射線繞射峰值強度比率的二倍。
  3. 如申請專利範圍第1項所述的半導體元件，其中所述第一銅層中的孿晶界密度大於所述第二銅層中的孿晶界密度。
  4. 如申請專利範圍第1項所述的半導體元件，其中所述第一銅層的厚度小於所述第二銅層的厚度的約0.2倍。
  5. 如申請專利範圍第1項所述的半導體元件，其中所述第一銅層具有介於約0.5微米至約3微米範圍內的厚度。
  6. 如申請專利範圍第1項所述的半導體元件，其中當使用含有過氧化氫及磷酸的蝕刻溶液或含有過氧化氫及檸檬酸的蝕刻溶液時，所述第一銅層的銅蝕刻速率低於所述第二銅層的銅蝕刻速率的一半。
  7. 如申請專利範圍第1項所述的半導體元件，更包括： 底切區，形成於所述第一銅層的側壁上， 其中所述底切區的深度介於約0.2微米至約0.6微米範圍內。
  8. 如申請專利範圍第7項所述的半導體元件，其中所述第一銅層的厚度大於所述底切區的所述深度。
  9. 如申請專利範圍第7項所述的半導體元件，更包括： 凸塊下圖案，位於所述墊與所述第一銅層之間， 其中所述第一銅層的與所述底切區位於同一水平高度的一部分的寬度較所述凸塊下圖案的寬度小。
  10. 如申請專利範圍第9項所述的半導體元件，其中所述凸塊下圖案包括： 依序堆疊的障壁圖案及晶種圖案，且 其中所述晶種圖案的寬度小於所述障壁圖案的寬度。
  11. 如申請專利範圍第1項所述的半導體元件，其中所述凸塊結構更包括： 鎳層，夾置於所述第二銅層與所述焊料球之間，且 其中所述鎳層的寬度大於所述第一銅層的寬度及所述第二銅層的寬度。
  12. 如申請專利範圍第11項所述的半導體元件，其中所述凸塊結構更包括： 第三銅層，夾置於所述鎳層與所述焊料球之間，且 其中所述第一銅層的（111）平面對所述第一銅層的（200）平面的所述第一X射線繞射峰值強度比率大於所述第三銅層的（111）平面對所述第三銅層的（200）平面的第三X射線繞射峰值強度比率。
  13. 一種半導體元件，包括： 墊，安置於基板上；以及 凸塊結構，安置於所述墊上且電性連接至所述墊， 其中所述凸塊結構包括： 第一銅層及第二銅層，依序堆疊於所述墊上；以及 焊料球，位於所述第二銅層上，且 其中所述第一銅層中的孿晶界密度大於所述第二銅層中的孿晶界密度。
  14. 如申請專利範圍第13項所述的半導體元件，其中所述第一銅層的厚度小於所述第二銅層的厚度的約0.2倍。
  15. 如申請專利範圍第13項所述的半導體元件，其中所述第一銅層的厚度介於約0.5微米至約3微米範圍內。
  16. 如申請專利範圍第13項所述的半導體元件，更包括： 底切區，形成於所述第一銅層的側壁上，且 其中所述底切區的深度介於約0.2微米至約0.5微米範圍內。
  17. 一種製造半導體元件的方法，包括： 在基板上形成墊； 形成電性連接至所述墊的凸塊下層； 在所述凸塊下層上形成具有開口的遮罩圖案； 在所述開口中依序形成第一銅層、第二銅層及焊料層； 移除所述遮罩圖案；以及 執行濕蝕刻製程以蝕刻所述凸塊下層的一部分， 其中所述第一銅層是使用脈波式鍍覆製程形成，且 所述第二銅層是使用直流鍍覆製程形成。
  18. 如申請專利範圍第17項所述的製造半導體元件的方法，其中所述第一銅層的厚度被形成為小於所述第二銅層的厚度的約0.2倍。
  19. 如申請專利範圍第17項所述的製造半導體元件的方法，其中所述第一銅層被形成為具有約0.5微米至約3微米的厚度。
  20. 如申請專利範圍第17項所述的製造半導體元件的方法，其中在執行所述濕蝕刻製程以蝕刻所述凸塊下層的所述一部分時，在所述第一銅層的側壁中形成底切區。
  21. 如申請專利範圍第20項所述的製造半導體元件的方法，其中所述底切區被形成為具有約0.2微米至約0.6微米的深度。
  22. 如申請專利範圍第17項所述的製造半導體元件的方法，其中形成所述凸塊下層包括： 依序形成障壁層及晶種層， 其中執行所述濕蝕刻製程為部分地蝕刻所述障壁層及所述晶種層，以形成障壁圖案及晶種圖案，且 其中所述晶種圖案的寬度小於所述障壁圖案的寬度。
  23. 如申請專利範圍第17項所述的製造半導體元件的方法，其中所述脈波式鍍覆製程是使用負載循環介於約5%至約50%範圍內的脈波電流來執行。
  24. 如申請專利範圍第17項所述的製造半導體元件的方法，更包括： 在形成所述焊料層之前，在所述第二銅層上形成鎳層， 其中在所述濕蝕刻製程中，所述第一銅層的蝕刻速率大於所述鎳層的蝕刻速率，且 其中在所述濕蝕刻製程中，所述第二銅層的蝕刻速率大於所述鎳層的蝕刻速率。
  25. 如申請專利範圍第17項所述的製造半導體元件的方法，更包括對所述焊料層執行回焊製程以形成焊料球。
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