TWI529854B - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

Info

Publication number
TWI529854B
TWI529854B TW102129164A TW102129164A TWI529854B TW I529854 B TWI529854 B TW I529854B TW 102129164 A TW102129164 A TW 102129164A TW 102129164 A TW102129164 A TW 102129164A TW I529854 B TWI529854 B TW I529854B
Authority
TW
Taiwan
Prior art keywords
metal layer
hole
semiconductor device
plating
substrate
Prior art date
Application number
TW102129164A
Other languages
English (en)
Other versions
TW201438145A (zh
Inventor
Koji Ogiso
Soichi Yamashita
Kazuhiro Murakami
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of TW201438145A publication Critical patent/TW201438145A/zh
Application granted granted Critical
Publication of TWI529854B publication Critical patent/TWI529854B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)

Description

半導體裝置之製造方法及半導體裝置 [相關申請案]
本申請案享受以日本專利申請案2013-56586號(申請日：2013年3月19日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之所有內容。
本發明之實施形態係關於一種半導體裝置之製造方法及半導體裝置。
先前，有藉由在基板上多段地積層形成有半導體元件或積體電路之晶片而減少半導體裝置之專有面積之技術。被積層之各晶片彼此係藉由貫通基板之貫通電極而連接。貫通電極係藉由例如利用電解電鍍於貫通基板之正背面之貫通孔埋入金屬而形成。
於利用電解電鍍於貫通孔埋入金屬而形成貫通電極之步驟中，有於貫通電極之內部產生稱為孔隙(void)之空隙之情況。此種孔隙成為使貫通電極之導通特性降低之原因之一。
本發明之一實施形態之目的在於提供一種可抑制於貫通電極之內部產生孔隙之半導體裝置之製造方法及半導體裝置。
根據本發明之一實施形態，提供一種半導體裝置之製造方法。 於半導體裝置之製造方法中，於基板之背面形成導電膜。形成貫通上述基板之正背面且到達上述導電膜之貫通孔。於上述貫通孔之內壁面、上述導電膜之自上述貫通孔露出之面及上述基板之表面形成包含銅之籽晶膜。使用電解電鍍法，使包含銅之第1金屬層自貫通上述基板之正背面之貫通孔之一端面朝向另一端面自下而上成長，留出距上述另一端面為上述貫通孔之半徑以下之深度而填埋上述貫通孔。使用電解電鍍法，使包含鎳之第2金屬層自藉由上述第1金屬層而自上述一端面填埋至中途部之上述貫通孔之內周面進行保形成長(conformal growth)，且使上述第2金屬層之頂面自上述另一端面突出。於上述第2金屬層之頂面形成第3金屬層。將上述第3金屬層作為遮罩而蝕刻上述籽晶膜。使上述第3金屬層熱熔融而成形。
1‧‧‧貫通電極
2‧‧‧基板
3‧‧‧通孔
4‧‧‧第1金屬層
5‧‧‧第2金屬層
6‧‧‧凸塊
6a‧‧‧第3金屬層
7‧‧‧電極
8‧‧‧絕緣膜
9‧‧‧銅膜
10‧‧‧抗蝕劑
11‧‧‧覆蓋層
12‧‧‧孔隙
D‧‧‧深度
H‧‧‧高度
R‧‧‧半徑
圖1係表示實施形態之半導體裝置之說明圖。
圖2(a)~(c)係表示實施形態之半導體裝置之製造步驟之說明圖。
圖3(a)、(b)係表示實施形態之半導體裝置之製造步驟之說明圖。
圖4(a)、(b)係表示實施形態之半導體裝置之製造步驟之說明圖。
圖5(a)、(b)係表示實施形態之半導體裝置之製造步驟之說明圖。
以下，參照隨附圖式，對實施形態之半導體裝置之製造方法及半導體裝置詳細地進行說明。再者，本發明並不由該實施形態限定。圖1係表示實施形態之半導體裝置之說明圖。再者，圖1中，模式性地表示半導體裝置中之貫通基板2之正背面之貫通電極1之部分剖面。
如圖1所示，實施形態之半導體裝置包括貫通基板2之正背面之貫通電極1。具體而言，貫通電極1例如包括第1金屬層4，該第1金屬層4自貫通矽晶圓等基板2之正背面之貫通孔(以下，記作「通孔3」)之一端面(此處為下表面)填埋至到另一端面(此處為上表面)之中途 部。
進而，貫通電極1包括：第2金屬層5，其自通孔3之中途部填埋至通孔3之上部端面，並且頂面自通孔3之上部端面突出；及凸塊6，其具有設置於第2金屬層5之頂面且藉由熱熔融而成形之第3金屬層。再者，於通孔3之內周面與貫通電極1之間設置有絕緣膜8及銅膜9，於貫通電極1之底面設置有電極7。
此種貫通電極1中之第1金屬層4係藉由例如使銅自通孔3之底面朝向上方析出而形成。藉此，可防止於第1金屬層4之內部產生孔隙。
另一方面，第2金屬層5係藉由例如使鎳自藉由第1金屬層4而填埋至中途部之通孔3之底面及周面析出而形成。藉此，可抑制第2金屬層5之內部之孔隙之產生，並且可高精度地控制第2金屬層5之頂面之高度。
以下，參照圖2~圖5，對形成此種貫通電極1之製造步驟之一例具體地進行說明。圖2~圖5係表示實施形態之半導體裝置之製造方法之說明圖。再者，圖2~圖5中，選擇性地表示形成貫通電極1之區域之模式性之剖面，關於其他部分，省略圖示。
如圖2之(a)所示，於實施形態之半導體裝置之製造方法中，例如，準備形成有半導體記憶體等半導體元件之矽晶圓等基板2。而且，於基板2之一主面(此處為下表面)之特定位置，例如設置將金等導電膜圖案化而形成之電極7。
接著，如圖2之(b)所示，形成自基板2之另一主面(此處為上表面)朝向一主面貫通基板2之正背面之通孔3，使電極7之上表面露出。然後，如圖2(c)所示，於通孔3之內周面及基板2之上表面，例如藉由濺鍍法而形成氧化矽膜等絕緣膜8。
其後，藉由去除形成於電極7之上表面之絕緣膜8而使電極7之上表面再次露出，之後，於絕緣膜8之表面，例如藉由濺鍍法而形成成 為電解電鍍之籽晶膜之銅膜9。再者，銅膜9為籽晶膜之一例，只要為形成於貫通孔3之內壁面、電極7之自通孔3露出之面及基板2之表面之包含銅之薄膜，則亦可為除銅膜9以外之薄膜。
接著，如圖3之(a)所示，於基板2之上表面形成抗蝕劑10之後，選擇性地去除通孔3之形成位置之抗蝕劑10。此時，於基板2之上表面，在通孔3之形成位置殘留具有直徑大於通孔3之直徑之孔部之抗蝕劑10。
接著，於內周面由銅膜9被覆之通孔3之內部，藉由電解電鍍而埋入金屬。此處，於通孔3埋入金屬之電解電鍍有自下而上鍍敷、保形鍍敷之2種鍍敷法。
自下而上鍍敷係使金屬層自通孔3之成為底面之一端面朝向成為上部開口之另一端面依序成長而將金屬埋入通孔3之鍍敷法。於自下而上鍍敷中，藉由將包含抑制鍍敷金屬附著於通孔3之內側面之界面活性劑之添加劑添加至鍍敷中所使用之電解液，而使金屬層自通孔3之底面側成長。
根據此種自下而上鍍敷，可抑制貫通電極1之內部之孔隙之產生。但是，於藉由自下而上鍍敷而填埋整個通孔3之情形時，如圖3之(a)中一點鏈線所示，金屬層自通孔3之上部開口朝向上方呈弓形隆起，形成覆蓋層(overburden)11。
於藉由自下而上鍍敷而同時填埋複數個通孔3之情形時，形成於各通孔3之上部開口之覆蓋層11根據通孔3不同而高度H不同。又，以覆蓋層11之高度H變得均勻之方式進行控制非常困難。
因此，於藉由自下而上鍍敷而同時填埋複數個通孔3之情形時，形成於填埋通孔3之金屬層上之各凸塊6(參照圖1)之高度變得不均勻，因而有於之後積層之晶片與凸塊6之間產生連接不良之虞。又，自下而上鍍敷與保形鍍敷相比，亦有將金屬層埋入通孔3耗費時間之 問題。
另一方面，保形鍍敷係使金屬層自通孔3之包含底面之整個內周面成長而將金屬埋入至通孔3之鍍敷法。根據保形鍍敷，相較於自下而上鍍敷，可於較短時間內完成將金屬層埋入通孔3。
於此種保形鍍敷中，因電場集中於通孔3之上部開口之角部，故相較於通孔3之內側面，金屬層更早於上部開口之部分成長。因此，於藉由保形鍍敷而填埋整個通孔3之情形時，於通孔3之內部被金屬層填埋之前，通孔3之上部開口由金屬層堵塞，如圖3之(a)中兩點鏈線所示，有於通孔3內部產生孔隙12之情況。
因此，於本實施形態中，如圖3之(a)所示，首先，藉由自下而上鍍敷而自通孔3之底面開始第1金屬層4之自下而上成長。此處，第1金屬層4係藉由例如使包含銅之金屬層成長而形成。其後，藉由第1金屬層4而自通孔3之底面填埋至中途部，結束自下而上鍍敷。
具體而言，如圖3之(b)所示，留出距通孔3之上部開口端面為通孔3之半徑R以下之深度D，藉由第1金屬層4而自通孔3之底面填埋至中途部，結束自下而上鍍敷。
接著，如圖4之(a)所示，開始保形鍍敷，使第2金屬層5自藉由第1金屬層4而填埋至中途部之通孔3之內周面進行保形成長。此處，第2金屬層5係藉由例如使包含鎳之金屬層成長而形成。
此時，藉由保形鍍敷而填埋之通孔3之深度D係如上所述為通孔3之半徑R以下。因此，即便第2金屬層5早於通孔3之內側面於通孔3之上部開口之角部進行保形成長，亦於由第2金屬層5堵塞通孔3之上部開口以前填埋通孔3，故可抑制孔隙之產生。再者，藉由保形鍍敷而填埋之通孔3之深度D只要為可抑制第2金屬層5中之孔隙之產生之深度，則亦可深於通孔3之半徑R。
又，如此，藉由保形鍍敷而填埋利用自下而上鍍敷填埋至中途 部之通孔3之剩餘部分，故與藉由自下而上鍍敷填埋整個通孔3之情形相比，可於短時間內完成通孔3之埋入。
其後，繼續保形鍍敷，如圖4之(b)所示，使第2金屬層5之頂面突出至距通孔3之上部開口端面特定之高度，結束保形鍍敷。如此，藉由保形鍍敷而使第2金屬層5之頂面自通孔3之上部開口端面突出，故與自下而上鍍敷相比，可高精度地控制第2金屬層5頂面之高度。
接著，如圖5之(a)所示，於第2金屬層5上形成第3金屬層6a。此處，第3金屬層6a為可藉由熱熔融而成形之金屬層，例如藉由錫而形成。
其後，如圖5之(b)所示，於去除抗蝕劑10之後，以自通孔3之上部開口端面突出之第2金屬層5及第3金屬層6a為遮罩進行濕式蝕刻，藉此去除形成於基板2上之銅膜9。
於此處之濕式蝕刻中，使用可熔融銅且無法熔融鎳之藥液。藉此，可防止成為第3金屬層6a之基座(POST)之第2金屬層5被蝕刻。因此，可防止因第2金屬層5之直徑小徑化所致之導通特性或機械強度之降低。
最後，實施回焊處理，使第3金屬層6a熔融而成形為大致半球形狀，藉此形成凸塊6(參照圖1)。藉此，製造圖1所示之半導體裝置。
如上所述，於本實施形態中，藉由利用自下而上鍍敷形成之第1金屬層而自貫通基板之正背面之貫通孔之底面填埋至中途部。藉此，可防止於填埋至貫通孔之中途部之第1金屬層之內部產生孔隙。
又，於本實施形態中，藉由利用保形鍍敷形成之第2金屬層而填埋藉由第1金屬層自底面填埋至中途部之貫通孔，進而，使第2金屬層之頂面自貫通孔突出。藉此，可抑制於第2金屬層之內部產生孔隙，並且可高精度地控制第2金屬層之頂面之高度。
又，於本實施形態中，於第2金屬層之頂面形成使第3金屬層熱 熔融而成形之凸塊。藉此，僅藉由積層並加熱實施形態之半導體裝置，便可容易地將所積層之半導體彼此連接。
又，藉由使用先前以來通常使用之銅作為貫通電極之材料形成第1金屬層，而不大幅變更先前之製造步驟便可形成第1金屬層。又，藉由使用鎳作為第2金屬層之材料，而於藉由濕式蝕刻去除殘存於基板表面之銅膜之步驟中，可防止第2金屬膜之側面被蝕刻。因此，可防止第2金屬層之導通特性或機械強度之降低。
又，於形成第1金屬層之步驟中，留出距貫通孔之上部開口端面為貫通孔之半徑以下之深度，藉由第1金屬層而自貫通孔之底面填埋至中途部。藉此，於藉由利用保形鍍敷形成之第2金屬層而填埋藉由第1金屬層填埋至中途部之貫通孔之情形時，可更加確實地抑制第2金屬層內部之孔隙之產生。
再者，於本實施形態中，將鍍敷之籽晶膜設為包括銅膜9之單層構造，但亦可於被覆通孔3之內周面之絕緣膜8之表面例如依序形成鈦膜及銅膜而設為多層構造。又，關於被覆通孔3之內周面之絕緣膜8，例如亦可依序形成氮化矽膜及氧化矽膜而設為多層構造。又，於本實施形態中，於形成電極7之後形成貫通電極1，但亦可於形成貫通電極1之後形成電極7。
對本發明之數個實施形態進行了說明，但該等實施形態係作為示例而提出，並不意圖限定發明之範圍。該等新穎之實施形態可以其他各種形態實施，且可於不脫離發明之主旨之範圍內進行各種省略、置換、變更。該等實施形態及其變形包含於發明之範圍或主旨內，並且包含於申請專利範圍中所記載之發明及其均等之範圍內。
1‧‧‧貫通電極
2‧‧‧基板
3‧‧‧通孔
4‧‧‧第1金屬層
5‧‧‧第2金屬層
6‧‧‧凸塊
7‧‧‧電極
8‧‧‧絕緣膜
9‧‧‧銅膜

Claims (1)

  1. 一種半導體裝置之製造方法，其特徵在於包含以下步驟：於基板之背面形成導電膜；形成貫通上述基板之正背面且到達上述導電膜之貫通孔；於上述貫通孔之內壁面、上述導電膜之自上述貫通孔露出之面及上述基板之表面形成包含銅之籽晶膜；使用電解電鍍法，使包含銅之第1金屬層自貫通上述基板之正背面之上述貫通孔之一端面朝向另一端面自下而上成長，留出距上述另一端面為上述貫通孔之半徑以下之深度而填埋上述貫通孔；使用電解電鍍法，使包含鎳之第2金屬層自藉由上述第1金屬層而自上述一端面填埋至中途部之上述貫通孔之內周面進行保形成長，且使上述第2金屬層之頂面自上述另一端面突出；於上述第2金屬層之頂面形成第3金屬層；將上述第3金屬層作為遮罩而蝕刻上述籽晶膜；及使上述第3金屬層熱熔融而成形。
TW102129164A 2013-03-19 2013-08-14 Semiconductor device manufacturing method and semiconductor device TWI529854B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013056586A JP5826782B2 (ja) 2013-03-19 2013-03-19 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201438145A TW201438145A (zh) 2014-10-01
TWI529854B true TWI529854B (zh) 2016-04-11

Family

ID=51552165

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102129164A TWI529854B (zh) 2013-03-19 2013-08-14 Semiconductor device manufacturing method and semiconductor device

Country Status (4)

Country Link
US (2) US20140284772A1 (zh)
JP (1) JP5826782B2 (zh)
CN (1) CN104064513B (zh)
TW (1) TWI529854B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US11437269B2 (en) 2012-03-27 2022-09-06 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10083893B2 (en) * 2014-01-30 2018-09-25 Toshiba Memory Corporation Semiconductor device and semiconductor device manufacturing method
JP6113679B2 (ja) * 2014-03-14 2017-04-12 株式会社東芝 半導体装置
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
JP6561635B2 (ja) * 2015-07-09 2019-08-21 大日本印刷株式会社 貫通電極基板及びその製造方法
TWI729457B (zh) * 2016-06-14 2021-06-01 美商應用材料股份有限公司 金屬及含金屬化合物之氧化體積膨脹
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
JP6963396B2 (ja) 2017-02-28 2021-11-10 キヤノン株式会社 電子部品の製造方法
US11043558B2 (en) 2018-10-31 2021-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain metal contact and formation thereof
WO2020118100A1 (en) * 2018-12-05 2020-06-11 Lam Research Corporation Void free low stress fill
CN110767604B (zh) * 2019-10-31 2022-03-18 厦门市三安集成电路有限公司 化合物半导体器件和化合物半导体器件的背面铜制程方法
CN110808229B (zh) * 2019-11-15 2022-02-01 北京航空航天大学 一种硅基上高深宽比微纳通孔的填充方法
CN112420645B (zh) * 2020-11-16 2024-05-10 武汉新芯集成电路制造有限公司 半导体器件及其制作方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3018050B2 (ja) * 1991-11-15 2000-03-13 ローム株式会社 半導体装置およびその製造方法
JP3951091B2 (ja) * 2000-08-04 2007-08-01 セイコーエプソン株式会社 半導体装置の製造方法
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
JP2003318178A (ja) * 2002-04-24 2003-11-07 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
JP4937842B2 (ja) * 2007-06-06 2012-05-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5089336B2 (ja) * 2007-10-29 2012-12-05 新光電気工業株式会社 パッケージ用シリコン基板
US8784636B2 (en) * 2007-12-04 2014-07-22 Ebara Corporation Plating apparatus and plating method
US8138577B2 (en) * 2008-03-27 2012-03-20 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Pulse-laser bonding method for through-silicon-via based stacking of electronic components
JP5308145B2 (ja) * 2008-12-19 2013-10-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2011014728A (ja) * 2009-07-02 2011-01-20 Casio Computer Co Ltd 半導体装置及び半導体装置の製造方法
JP5730654B2 (ja) * 2010-06-24 2015-06-10 新光電気工業株式会社 配線基板及びその製造方法
JP2012231096A (ja) * 2011-04-27 2012-11-22 Elpida Memory Inc 半導体装置及びその製造方法
US9646942B2 (en) * 2012-02-23 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for controlling bump height variation
KR20140011137A (ko) * 2012-07-17 2014-01-28 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
US8940631B1 (en) * 2013-03-15 2015-01-27 Maxim Integrated Products, Inc. Methods of forming coaxial feedthroughs for 3D integrated circuits

Also Published As

Publication number Publication date
CN104064513A (zh) 2014-09-24
US20160035624A1 (en) 2016-02-04
US20140284772A1 (en) 2014-09-25
JP2014183185A (ja) 2014-09-29
CN104064513B (zh) 2017-05-03
TW201438145A (zh) 2014-10-01
JP5826782B2 (ja) 2015-12-02

Similar Documents

Publication Publication Date Title
TWI529854B (zh) Semiconductor device manufacturing method and semiconductor device
US8455357B2 (en) Method of plating through wafer vias in a wafer for 3D packaging
JP6568994B2 (ja) 半導体装置及びその製造方法
JP4581864B2 (ja) 半導体基板への貫通配線の形成方法
JP2009164481A5 (zh)
CN102325431B (zh) 在电路板上制作铜柱的方法和具有表面铜柱的电路板
JP2010258213A5 (ja) 半導体装置
JP2007005404A (ja) 半導体基板への貫通配線の形成方法
JP2010232590A (ja) 回路基板の製造方法
JP4552770B2 (ja) 半導体基板への貫通配線の形成方法
JP2015002299A (ja) 漏斗状の貫通電極およびその製造方法
US8980738B2 (en) Integrated circuit chip and fabrication method
JP2012190900A (ja) 半導体装置及びその製造方法
JP2013106015A (ja) 半導体装置、及びその製造方法
CN101853804A (zh) 半导体装置的制造方法
TWI739275B (zh) 半導體記憶裝置及其製造方法
JP2004207728A (ja) トレンチを用いた金属構造物の製造方法
TWI550800B (zh) 具強固型晶背凸塊之矽穿孔結構
JP2012169669A (ja) 半導体装置
KR20110126994A (ko) 반도체 소자 및 반도체 소자의 형성방법
JP4400408B2 (ja) 貫通電極の形成方法
JP6269175B2 (ja) 半導体装置の製造方法
JP2017208368A (ja) 貫通電極付基板
JP2008066328A (ja) 配線膜の形成方法
KR101052876B1 (ko) 반도체 패키지의 제조 방법