TWI680535B - 金屬及含金屬化合物之氧化體積膨脹 - Google Patents

金屬及含金屬化合物之氧化體積膨脹 Download PDF

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TWI680535B
TWI680535B TW106119157A TW106119157A TWI680535B TW I680535 B TWI680535 B TW I680535B TW 106119157 A TW106119157 A TW 106119157A TW 106119157 A TW106119157 A TW 106119157A TW I680535 B TWI680535 B TW I680535B
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film
feature
substrate surface
substrate
metal
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蘇史密辛哈 羅伊
Susmit Singha ROY
陳一宏
Yihong Chen
勁文 陳
Kelvin Chan
亞伯希吉特巴蘇 馬禮克
Abhijit Basu Mallick
史林尼維斯 干德可塔
Srinivas Gandikota
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美商應用材料股份有限公司
Applied Materials, Inc.
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Abstract

闡明包括在基板表面之至少一特徵上形成一膜的方法。此膜被膨脹以填充至少一特徵並造成此膜從至少一特徵的成長。也闡明形成自我對準通孔的方法。

Description

金屬及含金屬化合物之氧化體積膨脹
本申請案主張2016年6月14日提出申請之美國臨時申請案第62/349,879號之優先權權益，其全部內容在此以引用之方式併入本文。
本發明大體上關於沉積與處理薄膜的方法。更明確地，本發明關於填充基板中狹窄溝槽的處理。
半導體工業是快速發展的具有越來越小電晶體尺寸的晶片，以獲得每單位面積更多的功能性。由於裝置的尺寸持續縮小，裝置間的間隙/空間也是持續縮小，增加將裝置與另一裝置實體上隔離的困難度。在裝置之間的高深寬比溝槽/空間/間隙(通常是不規則形狀)中，填充高品質介電材料，以現存方法來實施(包括間隙填充、硬遮罩與間隔物應用)已經越來越有挑戰性。
在此領域中有著用於具有更小臨界尺寸的晶片設計之新方法的需求。此外，有著對於硬遮罩與間隔物應用的高品質金屬氧化物膜及在基板上形成圖案化薄膜的方法的持續需求。
本發明的一或更多具體例關於處理方法。提供其上具有至少一特徵的基板。此至少一特徵從基板表面延伸一深度至底表面且具有藉由第一側壁與第二側壁所界定的一寬度。一膜是此至少一特徵的底表面。此膜被膨脹以填充此至少一特徵。
本發明額外的具體例關於處理方法，包含提供其上具有至少一特徵的基板表面。此至少一特徵從基板表面延伸一深度至底表面且有由第一側壁與第二側壁所界定的一寬度。一金屬膜形成在基板表面與此至少一特徵的第一側壁、第二側壁及底表面之上。此金屬膜被膨脹以填充此至少一特徵，使得此膜的頂部分包含金屬氧化物、金屬氮化物、金屬矽化物及/或金屬-鍺物種，且此膜的底部分包含此金屬膜。
本發明進一步的具體例關於處理方法，包含提供其上具有至少一特徵的基板表面。此至少一特徵從基板表面延伸一深度至底表面，且具有由第一側壁與第二側壁所界定的一寬度。基板表面包括一膜，此膜填充此至少一特徵並在基板表面上延伸。在基板表面上方的膜被移除，以留下基板表面與暴露的特徵中的膜。特徵中的膜被膨脹以造成此膜的直上成長，以形成從此至少一特徵延伸之此膜的柱子。材料層形成在基板表面上，且此膜的柱子被移除，以留下其上具有材料層的此至少一特徵。
在說明本發明的數個範例具體例之前，將理解到本發明並不侷限於接下來的說明書中所說明的架構或處理步驟的細節。本發明能為其他具體例且可以各種方式實行或執行。
本文中使用「基板」指稱任何基板或形成在基板上的材料表面，在其上於製造處理期間執行膜處理。例如，在其上可執行處理的基板表面包括材料，諸如矽、氧化矽、應變矽、絕緣體上矽(SOI)、碳摻雜氧化矽、非晶矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石、及其他材料，諸如金屬、金屬氮化物、金屬合金、與其他傳導材料，取決於應用。基板包括而沒有限制於半導體晶圓。基板可暴露至預處理製程以拋光、蝕刻、還原、氧化、羥基化、退火、UV固化、電子束固化及/或烘烤基板表面。除了直接在基板本身表面上的膜處理，在本發明中，揭示的任何膜處理步驟也可執行在形成於基板上的下方層之上，如之後更詳細地揭示，且用語「基板表面」是意指包括如文中所指示的此下方層。因此例如，在膜/層或部分膜/層已經被沉積在基板表面上的地方，新沉積膜/層的暴露表面成為基板表面。
本發明的一或更多具體例關於沉積金屬氧化物膜的方法，用於任何共形、非共形及/或低至高深寬比間隙/溝槽/孔隙填充應用。本發明的具體例有利地提供在小尺寸的高深寬比(AR)結構中沉積膜(例如金屬氧化物膜)的方法。本發明的某些具體例有利地提供填充間隙的方法，而不在間隙中形成接縫。本發明的一或更多具體例有利地提供形成自我對準通孔的方法。
圖1顯示具有特徵110的基板100的部分剖面視圖。圖式顯示出具有單一特徵的基板以用於說明目的；然而，此領域的熟習技藝者將理解到可以有著超過一個特徵。特徵110的形狀可為任何合適形狀，包括但不限於溝槽與圓柱通孔。在特定具體例中，特徵110是溝槽。在此使用上，用語「特徵」意味任何有意的表面不規則性。特徵的合適例子包括但不限於具有頂部、兩側壁與底部的溝槽、具有頂部與從表面向上延伸的兩側壁的尖峰、及具有從帶有開放底部的表面向下延伸的側壁的通孔。特徵或溝槽可具有任何合適深寬比(特徵的深度對於特徵的寬度的比例)。在某些具體例中，此深寬比是大於或等於約5：1、10：1、15：1、20：1、25：1、30：1、35：1或40：1。
基板100具有基板表面120。至少一特徵110在基板表面120中形成開口。特徵110從基板表面120延伸一深度D至底表面112。特徵110具有第一側壁114與第二側壁116，此兩者界定出特徵110的一寬度W。藉由側壁與底部所形成的開放區域也被指稱為間隙。
參照圖2A到圖2B，基板100被提供用於處理。在此使用上，用語「被提供」意味此基板被放置進入一位置或環境，以用於進一步處理。
膜130形成在基板表面120上與特徵110的壁及底部上。膜130可為任何合適的膜，藉由任何合適的處理而形成，包括但不限於化學氣相沉積、電漿增強化學氣相沉積、原子層沉積、電漿增強原子層沉積及/或物理氣相沉積。在某些具體例中，膜130藉由原子層沉積或電漿增強原子層沉積而形成。
在某些具體例中，膜130是金屬膜或含金屬膜。合適的金屬膜包括但不限於包括Co、Mo、W、Ta、Ti、Ru、Rh、Cu、Fe、Mn、V、Nb、Hf、Zr、Y、Al、Sn、Cr、Os、U及/或La中的一者或多者的膜。在某些具體例中，金屬膜包含鎢。在某些特定具體例中，金屬膜排除鎢。在某些具體例中，金屬膜排除Co、Mo、W、Ta、Ti、Ru、Rh、Cu、Fe、Mn、V、Nb、Hf、Zr、Y、Al、Sn、Cr、Os、U及/或La中的一者或多者。合適的含金屬膜包括金屬膜的衍生物。合適的金屬膜的衍生物包括但不限於氮化物、硼化物、碳化物、氮氧化物、硼氧化物、碳氧化物、氮碳化物、碳化硼、氮化硼、硼碳氮化物、硼氧碳氮化物、碳氮氧化物、硼氧碳化物及硼氮氧化物。此領域的熟習技藝者將理解到沉積的金屬膜可具有非化學計量數量的原子與金屬膜。例如，被稱為WN的膜可具有不同數量的鎢與氮。此WN膜可例如為90原子%鎢。使用WN以描述氮化鎢膜意味此膜包含鎢與氮原子且不應限制此膜於特定組成。在某些具體例中，此膜基本上是由指明的原子所構成。例如，基本上由WN構成的膜意指此膜的組成為大於或等於約95%、98%或99%的鎢與氮原子。在某些具體例中，膜130包含鎢。在某些具體例中，膜130基本上由鎢所構成。在一或更多具體例中，此膜包含鈦。在某些具體例中，此膜基本上由鈦或氮化鈦所構成。
在某些具體例中，膜130共形地形成在至少一特徵110上。當使用在本文中，用語「共形」或「共形地」指稱黏附於並均勻地覆蓋暴露表面的層，帶有相對於此膜的平均厚度具有少於1%的變化的厚度。例如，1000 Å厚的膜可具有小於10 Å的厚度變化。此厚度與變化包括凹部的邊緣、角落、側邊及底部。例如，本發明的各種具體例中藉由ALD沉積的共形層可提供覆蓋於複雜表面上基本上均勻厚度的沉積區上方。
在某些具體例中，膜130是連續膜。當使用在本文中，用語「連續」指稱覆蓋整個暴露表面的層，而沒有顯現出在沉積層下方的材料的間隙或裸露凸點(bare spot)。連續層可具有間隙或裸露凸點於小於約1%的膜的總表面區域的表面區域。
在某些具體例中，膜130可實質上無接縫地形成在特徵110內。在某些具體例中，接縫115可形成在特徵110的寬度W之內。接縫115可為形成在特徵110的壁114、116之間的任何間隙、空間或孔隙。
膜130可接著被膨脹以造成體積膨脹以填充特徵並容許膜130從特徵延伸。如圖2B所示，膨脹此膜造成原始膜130的體積膨脹以填充特徵。膜130的膨脹可在範圍為約10%至約1000%、或在範圍為約50%至約800%、或在範圍為約100%至約700%。在某些具體例中，膜130膨脹的量大於或等於約150%、200%、250%、300%或350%。在某些具體例中，膜130膨脹的量在範圍為約300%至約400%。如圖2B所示，膜130的膨脹使得接縫115被填充。
在某些具體例中，膨脹膜130是藉由暴露至氧化劑或氧化狀況，以將金屬或含金屬膜轉化為金屬氧化物膜。氧化劑可為任何合適的氧化劑，包括但不限於O2 、O3 、N2 O、H2 O、H2 O2 、CO、CO2 、NH3 、N2 /Ar、N2 /He、N2 /Ar/He及前述物的組合。在某些具體例中，氧化狀況包含熱氧化、電漿增強氧化、遠端電漿氧化、微波與射頻(例如ICP、CCP)。
在某些具體例中，膨脹膜130是藉由暴露至氮化劑或氮化狀況，以將金屬或含金屬膜轉化為金屬氮化物膜。氮化劑可為任何合適的氮化劑，包括但不限於氨、聯氨、NO2 、N2 /Ar電漿、N2 /He電漿、N2 /Ar/He電漿及前述物的組合。在某些具體例中，氮化狀況包含熱氮化、電漿增強氮化、遠端電漿氮化、微波與射頻(例如ICP、CCP)。
在某些具體例中，膨脹膜130是藉由暴露至矽化劑或矽化狀況，以將金屬或含金屬膜轉化為金屬矽化物膜。矽化劑可為任何合適的矽化劑，包括但不限於矽烷、二矽烷、三矽烷、四矽烷、五矽烷、六矽烷、三甲基矽烷、具有三甲基矽基取代基的化合物及前述物的組合。在某些具體例中，矽化狀況包含熱矽化、電漿增強矽化、遠端電漿矽化、微波與射頻(例如ICP、CCP)。
在某些具體例中，膨脹膜130是藉由暴露至鍺試劑或鍺化狀況，以將金屬或含金屬膜轉化為金屬鍺化物膜。鍺化劑可為任何合適的鍺化劑，包括但不限於鍺烷、二鍺烷、三鍺烷、四鍺烷、五鍺烷、六鍺烷、三甲基鍺、具有三甲基鍺烷基取代基的化合物及前述物的組合。在某些具體例中，鍺化狀況包含熱鍺化、電漿增強鍺化、遠端電漿鍺化、微波與射頻(例如ICP、CCP)。
處理此膜或膜130的膨脹可發生在任何合適溫度，取決於例如膜的組成及膨脹劑。在某些具體例中，此膜膨脹發生於溫度在範圍為約25℃至約1100℃。在某些具體例中，膨脹發生於溫度大於或等於約250℃、300℃、350℃、400℃、450℃、500℃或550℃。
在某些具體例中，膜130沉積於厚度在範圍為約25 Å至約200 Å、或在範圍為約50 Å至約150 Å。在一或更多具體例中，膜130沉積於厚度為約50 Å且實質上無接縫形成在膜中。接縫形成發生在靠近於特徵110的頂部分上的膜的厚度，於特徵被膜填充之前。在某些具體例中，基板表面具有膜，帶有在至少一特徵之側壁之間的接縫。在此使用上，用語「之間」意指在接縫的任一側上有著某些膜於接縫與特徵的側壁之間。此接縫不限於正好在側壁的中心中。
在藉由例如氧化的膜130的膨脹期間，間隙140形成在基板表面120的頂上。間隙140可具有匹配於氧化環境的內容物或可為不同的組成物。例如，使用氮電漿的氧化環境可形成帶有氮環境的間隙140。膨脹劑可具有效力於間隙140的尺寸及內容物。例如，若使用氮化劑以膨脹此膜，間隙140可包括氮。
如圖3所示，在膨脹期間，特徵形狀的保真度被維特在特徵的頂部上，使得膜130從特徵110直上地成長。在此使用上，「直上地」意指此膜形成圍繞間隙140的表面144，而鄰近於特徵側壁114的表面144的部分是與側壁114實質上共面。表面144與側壁114共面，其中形成於側壁114與表面144的接合處的角度是±10°。此種膨脹被預期以等向性地成長以形成菇形頂部。膜130的膨脹以形成直線片段142是非預期的。
在某些具體例中，在膨脹之前以摻雜劑摻雜膜130。此摻雜劑可被併入膜130中，於形成膜130的相同時間或於連續於膜沉積的一分開處理中。例如，沉積膜130可發生，之後隨著在一分開處理中以摻雜劑摻雜膜130，於相同處理腔室或不同處理腔室的任一者。在某些具體例中，發生膜130的沉積及摻雜步驟在單一處理中。例如，膜前驅物與摻雜劑可共流進入處理腔室中以形成膜130。
某些具體例包括可選處理製程。此處理製程處理膜130以改善此膜的某些參數。在某些具體例中，處理製程包含退火此膜。在某些具體例中，可藉由在使用於沉積及/或還原的相同處理腔室中的原位退火而執行處理。合適的退火製程包括但不限於快速熱處理(RTP)或快速熱退火(RTA)、尖波退火(spike anneal)、或UV固化、或電子束固化及/或雷射退火。退火溫度可在範圍為約500℃至900℃。在退火期間，環境的組成可包括H2 、Ar、He、N2 、NH3 、SiH4 、等等的一者或多者。在退火期間的壓力可在範圍為約100毫托至約760托(1 atm)。
儘管這些處理可以是參照氧化，此領域的熟習技藝者將理解到本發明並不侷限於氧化反應以膨脹此膜。使用氧化反應以說明各種具體例僅是為了方便，且不限制本發明的範疇。參照圖4，在某些具體例中，相較於在特徵110的底部分131，在頂部分(直線片段142)有著較大量的氧化。在某些具體例中，有著較小或沒有膜130的氧化於特徵110的底部分131。圖5A到圖5C顯示在特徵110m(例如溝槽)的底部中沉積膜的方法。膜130藉由任何合適技術沉積。例如，在圖5A中，藉由原子層沉積可在基板上沉積鎢膜。在圖5B中的膜130已經被氧化並膨脹以填充特徵110。膜130的頂部分142包含沉積金屬的氧化物(例如氧化鎢)而膜130的底部分131維持未氧化(例如鎢金屬)。頂部分142與底部分131間的不同可用於從基板選擇性蝕刻材料。如圖5C所示，若膜130被沉積於對於氧化物為選擇性的蝕刻處理，在頂部分142的氧化物膜會被移除，留下在底部分131的金屬膜。
圖6A至圖6C顯示本發明的另一具體例。在圖6A中，顯示出具有至少一特徵110(例如溝槽)的基板100。金屬膜130沉積在特徵110的底部中，如圖6B所示。在圖6C中，膜130可被氧化，使得此膜膨脹以填充特徵110。
圖7A到7D顯示本發明的另一具體例，其中形成自我對準通孔。在圖7A中，提供具有氧化膜130的基板。可執行拋光或蝕刻處理以從基板100的表面120移除膜130的頂部，如圖7B所示。膜130維持在特徵110之內並填充特徵110。如圖7C所示，膜130可接著被氧化以造成膜130的向上成長。膜130的側邊維持與特徵110的側邊實質上共面，使得有著從特徵110延伸的柱子。材料層160沉積在基板100的表面120上。如圖7D所示，膜130可被移除(例如藉由蝕刻)，以留下具有材料層160的特徵110，材料層160對準於特徵110的頂部上。
圖4至圖7D所示的具體例的氧化反應可為氮化反應、矽化反應或鍺化反應。此領域的熟習技藝者將理解到可使用其他處理與反應以膨脹在特徵內的膜或造成膜的直上成長。
根據一或更多具體例，在形成此層之前及/或之後，基板受到處理。此處理可執行在相同腔室或在一或更多分開處理腔室中。在某些具體例中，基板從第一腔室移動到分開的第二腔室以進行其他處理。基板可直接從第一腔室移動至分開的處理腔室，或可從第一腔室移動到一或更多移送腔室，然後移動到分開的處理腔室。因此，處理設備可包含以移送站連通的多個腔室。這種設備可被指稱為「叢集工具」、「叢集系統」及類似物。
大體上，叢集工具是模組系統，包含多個腔室，其執行各種功能，包括基板中心找尋與定向、除氣、退火、沉積及/或蝕刻。根據一或更多具體例，叢集工具包括至少一第一腔室與一中央移送腔室。中央移送腔室可容納機器人，其可在處理腔室與裝載閘腔室之間與之中搬運基板。移送腔室通常維持在真空狀況並提供中間階段以從一腔室搬運基板至另一腔室及/或至定位在叢集工具前端的裝載閘腔室。可被採用於本發明的兩種廣為人知的叢集工具是Centura®與Endura®，兩者皆可從加州聖克拉拉的應用材料公司取得。然而，腔室確切的佈置與組合可由於執行本文所述處理的特定步驟而改變。可使用的其他處理腔室包括但不限於，週期層沉積(cyclical layer deposition, CLD)、原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、蝕刻、預清洗、化學清洗、諸如RTP的熱處理、電漿氮化、除氣、定向、羥化及其他基板處理。藉由執行叢集工具上腔室中的處理，可避免有大氣雜質的基板的表面污染，而不用在沉積後續膜之前的氧化。
根據一或更多具體例，基板連續地處於真空或「裝載閘」狀況，且當從一腔室移動到下一個腔室時，不暴露至周圍空氣。移送腔室因此在真空下且被「抽氣」於真空壓力下。惰性氣體可存在於處理腔室或移送腔室中。在某些具體例中，惰性氣體用於作為淨化氣體，以移除某些或全部的反應物。根據一或更多具體例，淨化氣體被注射於沉積腔室的出口，以避免反應物從沉積腔室移動至移送腔室及/或額外處理腔室。因此，惰性氣體的流動形成簾幕於腔室的出口。
可在單一基板沉積腔室中處理基板，其中在處理另一個基板之前，單一基板被載入、處理及載出。基板也可以連續方式處理，類似於輸送系統，其中多個基板被獨立地載入腔室的第一部分，移動經過腔室並從腔室的第二部分載出。腔室與相關輸送系統的外形可形成直線路徑或彎曲路徑。此外，處理腔室可為旋轉料架，其中多個基板繞著中心軸移動並貫穿旋轉料架路徑暴露至沉積、蝕刻、退火、清洗、等等的處理。
在處理期間，基板可被加熱或冷卻。此加熱或冷卻可藉由任何合適方式而完成，包括但不限於，改變基板支撐件的溫度及流動加熱的或冷卻的氣體到基板表面。在某些具體例中，基板支撐件包括加熱器/冷卻器，其可被控制以傳導地改變基板溫度。在一或更多具體例中，所利用的氣體(反應氣體或惰性氣體任一者)被加熱或冷卻，以局部地改變基板溫度。在某些具體例中，加熱器/冷卻器定位在腔室內，鄰近於基板表面以對流地改變基板溫度。
在處理期間，基板也可為固定的或被旋轉。旋轉的基板可被連續地旋轉或以分離階段旋轉。例如，基板可被旋轉貫穿整個處理，或基板可被小量地旋轉於暴露至不同反應氣體或淨化氣體之間。在處理期間旋轉基板(連續地或階段地任一者)可助於產生更均勻的沉積或蝕刻，藉由最小化例如氣流幾何形狀中局部變化的效應。
貫穿本說明書的參照「一具體例(one embodiment)」、「某些具體例」、「一或更多具體例」或「一具體例(an embodiment)」意味著以此具體例敘述的特定特徵、結構、材料、或性質是包括在本發明的至少一個具體例中。因此，出現於本說明書的各種地方的片語，諸如「在一或更多具體例中」、「在某些具體例中」、「在一具體例中(in one embodiment)」或「在一具體例中(in an embodiment)」不必然指稱本發明的同一個具體例。再者，特定特徵、結構、材料、或性質可以任何合適方式組合於一或更多具體例中。
雖然在此已經參照特定具體例而描述本發明，將理解到這些具體例僅為本發明的原理與應用的說明。在不悖離本發明的精神與範疇，可對本發明的方法與設備進行各種修改與變化，其對於此領域的熟習技藝者而言是顯而易見的。因此，意於本發明包括在隨附申請專利範圍及其等效物的範疇中的修改與變化。
100‧‧‧基板
110‧‧‧特徵
112‧‧‧底表面
114‧‧‧側壁
115‧‧‧接縫
116‧‧‧側壁
120‧‧‧基板表面
130‧‧‧膜
131‧‧‧底部分
140‧‧‧間隙
142‧‧‧頂部分
144‧‧‧表面
160‧‧‧材料層
藉由參照具體例，其一部分繪示於隨附圖式中，可獲得簡短總結於上的本發明的更明確的說明，以此方式本發明上述的特徵可被詳細理解。然而，將注意到隨附圖式僅繪示本發明的典型具體例，且因而不被當作限制本發明的範疇，由於本發明可容許其他等效具體例。
圖1顯示根據本發明的一或更多具體例的基板特徵的剖面視圖；
圖2A與圖2B顯示根據本發明的一或更多具體例的間隙填充處理的剖面示意圖；
圖3顯示根據本發明的一或更多具體例的氧化膜的剖面視圖；
圖4顯示根據本發明的一或更多具體例的氧化膜的剖面視圖；
圖5A到圖5C顯示根據本發明的一或更多具體例的處理的剖面示意圖；
圖6A到圖6C顯示根據本發明的一或更多具體例的處理的剖面示意圖；以及
圖7A到圖7D顯示根據本發明的一或更多具體例的處理的剖面示意圖。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無

Claims (18)

  1. 一種處理方法，包含以下步驟：提供一基板表面，該基板表面中具有至少一特徵，該至少一特徵從該基板表面延伸一深度至一底表面，該至少一特徵具有一寬度，該寬度藉由一第一側壁與一第二側壁所界定；在該基板表面上與該至少一特徵的該第一側壁、該第二側壁及該底表面上，形成一膜；以及膨脹該膜以填充該至少一特徵及使得該膜從該至少一特徵直上地膨脹並在該基板表面與該膜之間形成一間隙。
  2. 如請求項1所述之方法，其中該膜包含Co、Mo、W、Ta、Ti、Ru、Rh、Cu、Fe、Mn、V、Nb、Hf、Zr、Y、Al、Sn、Cr或La中的一者或多者。
  3. 如請求項2所述之方法，其中膨脹該膜的步驟包含：將該膜暴露至一氧化劑、一氮化劑、一矽化劑、及/或包含鍺的一化合物，該氧化劑包含O2、O3、N2O、H2O、H2O2、CO、CO2、NH3、N2/Ar、N2/He或N2/Ar/He中的一者或多者，該氮化劑包含氨、聯氨、NO2或氮電漿中的一者或多者，該矽化劑包含三甲基矽烷、矽烷、二矽烷中的一者或多者。
  4. 如請求項1所述之方法，其中膨脹該膜的步驟發生在大於或等於約300℃的一溫度。
  5. 如請求項1所述之方法，其中該沉積的膜是共形的。
  6. 如請求項1所述之方法，其中該特徵具有大於或等於10：1的一深寬比。
  7. 如請求項1所述之方法，進一步包含以一摻雜劑摻雜該膜。
  8. 如請求項6所述之方法，其中摻雜該膜的步驟發生於該膜的形成。
  9. 如請求項6所述之方法，其中摻雜該膜的步驟是與該膜的形成連續地執行。
  10. 如請求項1所述之方法，進一步包含處理該膜。
  11. 如請求項10所述之方法，其中處理該膜的步驟包含退火該膜。
  12. 如請求項1所述之方法，其中形成該膜的步驟不在該至少一特徵中形成一接縫。
  13. 一種處理方法，包含以下步驟：提供一基板表面，其上具有至少一特徵，該至少一特徵從該基板表面延伸一深度至一底表面，該至少一特徵具有一寬度，該寬度藉由一第一側壁與一第二側壁所界定；在該基板表面上與該至少一特徵的該第一側壁、該第二側壁及該底表面上，形成一金屬膜；以及膨脹該金屬膜以填充該至少一特徵，使得該膜的一頂部分包含一金屬氧化物、金屬氮化物、金屬矽化物及/或金屬-鍺物種，及該膜的該底部分包含該金屬膜。
  14. 如請求項13所述之方法，進一步包含：將該基板暴露至一蝕刻劑，以移除該金屬氧化物膜，留下在該至少一特徵的該底部分中的該金屬膜。
  15. 如請求項13所述之方法，其中膨脹該金屬膜的步驟發生在小於約400℃的一溫度。
  16. 如請求項13所述之方法，其中該基板包含氮化矽，該金屬膜包含鎢且該金屬氧化物膜包含氧化鎢。
  17. 如請求項13所述之方法，其中膨脹該膜的步驟發生在小於約350℃的一溫度。
  18. 一種處理方法，包含以下步驟：提供一基板表面，其上具有至少一特徵，該至少一特徵從該基板表面延伸一深度至一底表面，該至少一特徵具有一寬度，該寬度藉由一第一側壁與一第二側壁所界定，該基板表面包括一膜，該膜填充該至少一特徵且在該基板表面上方延伸；移除該基板表面上方的該膜，以留下該基板表面與在暴露的該等特徵中的膜；膨脹該等特徵中的該膜以造成該膜直上地成長，以形成從該至少一特徵延伸的該膜的多個柱子；在該基板表面上形成一材料層；以及移除該膜的該等柱子，以留下該至少一特徵及在該至少一特徵上的該材料層。
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Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI729457B (zh) 2016-06-14 2021-06-01 美商應用材料股份有限公司 金屬及含金屬化合物之氧化體積膨脹
TWI719262B (zh) * 2016-11-03 2021-02-21 美商應用材料股份有限公司 用於圖案化之薄膜的沉積與處理
US10224224B2 (en) 2017-03-10 2019-03-05 Micromaterials, LLC High pressure wafer processing systems and related methods
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US10847360B2 (en) 2017-05-25 2020-11-24 Applied Materials, Inc. High pressure treatment of silicon nitride film
KR102574914B1 (ko) 2017-06-02 2023-09-04 어플라이드 머티어리얼스, 인코포레이티드 보론 카바이드 하드마스크의 건식 스트리핑
TWI760540B (zh) * 2017-08-13 2022-04-11 美商應用材料股份有限公司 自對準高深寬比結構及製作方法
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
JP6947914B2 (ja) 2017-08-18 2021-10-13 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 高圧高温下のアニールチャンバ
WO2019055415A1 (en) 2017-09-12 2019-03-21 Applied Materials, Inc. APPARATUS AND METHODS FOR MANUFACTURING SEMICONDUCTOR STRUCTURES USING A PROTECTIVE BARRIER LAYER
TWI723282B (zh) * 2017-09-16 2021-04-01 美商應用材料股份有限公司 藉由矽化法之含金屬薄膜體積膨脹
US10643867B2 (en) 2017-11-03 2020-05-05 Applied Materials, Inc. Annealing system and method
KR102585074B1 (ko) 2017-11-11 2023-10-04 마이크로머티어리얼즈 엘엘씨 고압 프로세싱 챔버를 위한 가스 전달 시스템
KR102622303B1 (ko) 2017-11-16 2024-01-05 어플라이드 머티어리얼스, 인코포레이티드 고압 스팀 어닐링 프로세싱 장치
JP2021503714A (ja) 2017-11-17 2021-02-12 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 高圧処理システムのためのコンデンサシステム
TW202321493A (zh) * 2017-12-20 2023-06-01 美商應用材料股份有限公司 金屬薄膜之高壓氧化
CN111699549A (zh) 2018-01-24 2020-09-22 应用材料公司 使用高压退火的接缝弥合
TW201939628A (zh) * 2018-03-02 2019-10-01 美商微材料有限責任公司 移除金屬氧化物的方法
TWI751406B (zh) 2018-03-06 2022-01-01 美商應用材料股份有限公司 形成金屬硫系化物柱體之方法
SG11202008256WA (en) 2018-03-09 2020-09-29 Applied Materials Inc High pressure annealing process for metal containing materials
US10714331B2 (en) 2018-04-04 2020-07-14 Applied Materials, Inc. Method to fabricate thermally stable low K-FinFET spacer
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US10566188B2 (en) 2018-05-17 2020-02-18 Applied Materials, Inc. Method to improve film stability
US10704141B2 (en) 2018-06-01 2020-07-07 Applied Materials, Inc. In-situ CVD and ALD coating of chamber to control metal contamination
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
US10675581B2 (en) 2018-08-06 2020-06-09 Applied Materials, Inc. Gas abatement apparatus
WO2020092002A1 (en) 2018-10-30 2020-05-07 Applied Materials, Inc. Methods for etching a structure for semiconductor applications
KR20210077779A (ko) 2018-11-16 2021-06-25 어플라이드 머티어리얼스, 인코포레이티드 강화된 확산 프로세스를 사용한 막 증착
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
EP3816100A1 (en) 2019-10-28 2021-05-05 Murata Manufacturing Co., Ltd. Mems element with increased density
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film
US11101128B1 (en) * 2020-03-12 2021-08-24 Applied Materials, Inc. Methods for gapfill in substrates

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030143862A1 (en) * 1996-02-12 2003-07-31 Ravi Iyer Planarization using plasma oxidized amorphous silicon
US20050121768A1 (en) * 2003-12-05 2005-06-09 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US20080160783A1 (en) * 2004-03-16 2008-07-03 Ishikawajima-Harima Heavy Industries Co., Ltd. Method For Manufacturing Semiconductor Device

Family Cites Families (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4671970A (en) 1986-02-05 1987-06-09 Ncr Corporation Trench filling and planarization process
DE69031903T2 (de) * 1989-11-30 1998-04-16 Sgs Thomson Microelectronics Verfahren zum Herstellen von Zwischenschicht-Kontakten
JPH08288407A (ja) * 1995-04-12 1996-11-01 Sony Corp 半導体メモリ装置およびその製造方法
KR0165813B1 (ko) 1995-04-12 1999-02-01 문정환 접속홀의 플러그 형성 방법
KR100223334B1 (ko) 1996-06-29 1999-10-15 김영환 반도체소자의 금속배선형성방법
US6143653A (en) 1998-10-04 2000-11-07 Promos Technologies, Inc. Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss
KR20000026588A (ko) 1998-10-21 2000-05-15 윤종용 콘택홀을 갖는 반도체 장치 및 그 제조방법
US6130151A (en) 1999-05-07 2000-10-10 Taiwan Semiconductor Manufacturing Company Method of manufacturing air gap in multilevel interconnection
JP2001015479A (ja) 1999-06-29 2001-01-19 Toshiba Corp 半導体装置の製造方法
WO2001013426A1 (en) 1999-08-18 2001-02-22 Steag Rtp Systems, Inc. Method of producing copper features on semiconductor wafers
US6576113B1 (en) 1999-10-29 2003-06-10 California Institute Of Technology Method of electroplating of high aspect ratio metal structures into semiconductors
US6373087B1 (en) 2000-08-31 2002-04-16 Agere Systems Guardian Corp. Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses
US7192803B1 (en) 2000-10-13 2007-03-20 Bridge Semiconductor Corporation Method of making a semiconductor chip assembly with simultaneously formed interconnect and connection joint
US6653200B2 (en) 2001-01-26 2003-11-25 Applied Materials, Inc. Trench fill process for reducing stress in shallow trench isolation
JP2002252281A (ja) 2001-02-27 2002-09-06 Sony Corp 半導体装置およびその製造方法
US6528884B1 (en) 2001-06-01 2003-03-04 Advanced Micro Devices, Inc. Conformal atomic liner layer in an integrated circuit interconnect
US7279119B2 (en) 2001-06-14 2007-10-09 Ppg Industries Ohio, Inc. Silica and silica-based slurry
CN100360710C (zh) 2002-03-28 2008-01-09 哈佛学院院长等 二氧化硅纳米层压材料的气相沉积
US8298933B2 (en) 2003-04-11 2012-10-30 Novellus Systems, Inc. Conformal films on semiconductor substrates
US7211844B2 (en) 2004-01-29 2007-05-01 International Business Machines Corporation Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage
US7521378B2 (en) 2004-07-01 2009-04-21 Micron Technology, Inc. Low temperature process for polysilazane oxidation/densification
US7820020B2 (en) 2005-02-03 2010-10-26 Applied Materials, Inc. Apparatus for plasma-enhanced physical vapor deposition of copper with RF source power applied through the workpiece with a lighter-than-copper carrier gas
US7915533B2 (en) * 2005-04-28 2011-03-29 Hitachi Metals, Ltd. Silicon nitride substrate, a manufacturing method of the silicon nitride substrate, a silicon nitride wiring board using the silicon nitride substrate, and semiconductor module
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
JP2007005381A (ja) 2005-06-21 2007-01-11 Matsushita Electric Ind Co Ltd プラズマエッチング方法、及びプラズマエッチング装置
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
US7351648B2 (en) 2006-01-19 2008-04-01 International Business Machines Corporation Methods for forming uniform lithographic features
US7368394B2 (en) 2006-02-27 2008-05-06 Applied Materials, Inc. Etch methods to form anisotropic features for high aspect ratio applications
US7432195B2 (en) * 2006-03-29 2008-10-07 Tokyo Electron Limited Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features
US7288463B1 (en) 2006-04-28 2007-10-30 Novellus Systems, Inc. Pulsed deposition layer gap fill with expansion material
US7956465B2 (en) 2006-05-08 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing resistivity in interconnect structures of integrated circuits
US7625820B1 (en) * 2006-06-21 2009-12-01 Novellus Systems, Inc. Method of selective coverage of high aspect ratio structures with a conformal film
JP2008108757A (ja) 2006-10-23 2008-05-08 Matsushita Electric Works Ltd 化合物半導体発光素子およびそれを用いる照明装置ならびに化合物半導体素子の製造方法
US7598170B2 (en) 2007-01-26 2009-10-06 Asm America, Inc. Plasma-enhanced ALD of tantalum nitride films
US20080242097A1 (en) 2007-03-28 2008-10-02 Tim Boescke Selective deposition method
US20090017631A1 (en) 2007-06-01 2009-01-15 Bencher Christopher D Self-aligned pillar patterning using multiple spacer masks
WO2008153674A1 (en) 2007-06-09 2008-12-18 Boris Kobrin Method and apparatus for anisotropic etching
US20090072409A1 (en) 2007-09-14 2009-03-19 International Business Machines Corporation Interconnect Structures Incorporating Air-Gap Spacers
US7541297B2 (en) 2007-10-22 2009-06-02 Applied Materials, Inc. Method and system for improving dielectric film quality for void free gap fill
US20100330805A1 (en) 2007-11-02 2010-12-30 Kenny Linh Doan Methods for forming high aspect ratio features on a substrate
US7985977B2 (en) 2007-12-11 2011-07-26 Hvvi Semiconductors, Inc. Sacrificial pillar dielectric platform
KR101477661B1 (ko) 2008-07-17 2014-12-31 삼성전자주식회사 텅스텐 재성장을 통한 심 없는 텅스텐 패턴 및 그 패턴형성 방법
US8169031B2 (en) 2008-08-26 2012-05-01 International Business Machines Corporation Continuous metal semiconductor alloy via for interconnects
US8101456B2 (en) 2008-10-01 2012-01-24 International Business Machines Corporation Method to reduce a via area in a phase change memory cell
KR101026486B1 (ko) 2008-10-22 2011-04-01 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
JP5133852B2 (ja) 2008-11-13 2013-01-30 ルネサスエレクトロニクス株式会社 半導体装置の製造方法及び半導体装置
KR101534678B1 (ko) 2009-02-12 2015-07-08 삼성전자주식회사 텅스텐 콘택 플러그를 산소 분위기에서 ｒｔａ 처리하고, ｒｔｏ 처리된 텅스텐 플러그를 수소 분위기에서 환원시키는 반도체 소자의 제조방법
US8435830B2 (en) 2009-03-18 2013-05-07 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices
US8575753B2 (en) * 2009-05-27 2013-11-05 Samsung Electronics Co., Ltd. Semiconductor device having a conductive structure including oxide and non oxide portions
JP2011060803A (ja) 2009-09-07 2011-03-24 Toshiba Corp 半導体装置
US8531033B2 (en) * 2009-09-07 2013-09-10 Advanced Interconnect Materials, Llc Contact plug structure, semiconductor device, and method for forming contact plug
US8274065B2 (en) 2009-10-19 2012-09-25 Macronix International Co., Ltd. Memory and method of fabricating the same
US8778749B2 (en) 2011-01-12 2014-07-15 Sandisk Technologies Inc. Air isolation in high density non-volatile memory
US8900988B2 (en) 2011-04-15 2014-12-02 International Business Machines Corporation Method for forming self-aligned airgap interconnect structures
JP2011233922A (ja) 2011-07-20 2011-11-17 Ihi Corp 素子間分離領域の形成方法
US8946082B2 (en) 2011-09-16 2015-02-03 GlobalFoundries, Inc. Methods for forming semiconductor devices
KR20130046664A (ko) 2011-10-28 2013-05-08 삼성전자주식회사 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법
KR102131581B1 (ko) 2012-03-27 2020-07-08 노벨러스 시스템즈, 인코포레이티드 텅스텐 피처 충진
US9330939B2 (en) * 2012-03-28 2016-05-03 Applied Materials, Inc. Method of enabling seamless cobalt gap-fill
US8860001B2 (en) 2012-04-09 2014-10-14 Freescale Semiconductor, Inc. ReRAM device structure
US20140029181A1 (en) 2012-07-27 2014-01-30 Florian Gstrein Interlayer interconnects and associated techniques and configurations
US9245987B2 (en) 2012-11-29 2016-01-26 Micron Technology, Inc. Semiconductor devices and fabrication methods
US8901607B2 (en) 2013-01-14 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
US9312220B2 (en) 2013-03-12 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for a low-K dielectric with pillar-type air-gaps
US9178011B2 (en) 2013-03-13 2015-11-03 Intermolecular, Inc. Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate
JP5826782B2 (ja) * 2013-03-19 2015-12-02 株式会社東芝 半導体装置の製造方法
US9012322B2 (en) 2013-04-05 2015-04-21 Intermolecular, Inc. Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition
US9040421B2 (en) 2013-05-03 2015-05-26 GlobalFoundries, Inc. Methods for fabricating integrated circuits with improved contact structures
US9219007B2 (en) 2013-06-10 2015-12-22 International Business Machines Corporation Double self aligned via patterning
SG11201601323XA (en) 2013-09-27 2016-03-30 Intel Corp Previous layer self-aligned via and plug patterning for back end of line (beol) interconnects
EP3796371A3 (en) 2013-09-27 2021-10-06 INTEL Corporation Self-aligned via and plug patterning for back end of line (beol) interconnects
US20150111374A1 (en) 2013-10-18 2015-04-23 International Business Machines Corporation Surface treatment in a dep-etch-dep process
US8951429B1 (en) 2013-10-29 2015-02-10 Applied Materials, Inc. Tungsten oxide processing
US9362413B2 (en) 2013-11-15 2016-06-07 Cbrite Inc. MOTFT with un-patterned etch-stop
US9312168B2 (en) 2013-12-16 2016-04-12 Applied Materials, Inc. Air gap structure integration using a processing system
US9236292B2 (en) 2013-12-18 2016-01-12 Intel Corporation Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
US9219033B2 (en) * 2014-03-21 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Via pre-fill on back-end-of-the-line interconnect layer
JP6297884B2 (ja) 2014-03-28 2018-03-20 東京エレクトロン株式会社 タングステン膜の成膜方法
KR102377372B1 (ko) 2014-04-02 2022-03-21 어플라이드 머티어리얼스, 인코포레이티드 인터커넥트들을 형성하기 위한 방법
US9368395B1 (en) 2014-05-06 2016-06-14 Globalfoundries Inc. Self-aligned via and air gap
US9299745B2 (en) 2014-05-08 2016-03-29 GlobalFoundries, Inc. Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same
US9281382B2 (en) 2014-06-04 2016-03-08 Stmicroelectronics, Inc. Method for making semiconductor device with isolation pillars between adjacent semiconductor fins
US9627318B2 (en) 2014-06-16 2017-04-18 Taiwan Semiconductor Manufacturing Company Ltd. Interconnect structure with footing region
US9679852B2 (en) 2014-07-01 2017-06-13 Micron Technology, Inc. Semiconductor constructions
US9754935B2 (en) * 2014-08-07 2017-09-05 International Business Machines Corporation Raised metal semiconductor alloy for self-aligned middle-of-line contact
US9324650B2 (en) 2014-08-15 2016-04-26 International Business Machines Corporation Interconnect structures with fully aligned vias
US9356047B2 (en) 2014-08-18 2016-05-31 Globalfoundries Inc. Integrated circuits with self aligned contact structures for improved windows and fabrication methods
US9508642B2 (en) 2014-08-20 2016-11-29 Globalfoundries Inc. Self-aligned back end of line cut
US9349637B2 (en) 2014-08-21 2016-05-24 Lam Research Corporation Method for void-free cobalt gap fill
US9735030B2 (en) 2014-09-05 2017-08-15 Fujifilm Planar Solutions, LLC Polishing compositions and methods for polishing cobalt films
US9515085B2 (en) 2014-09-26 2016-12-06 Sandisk Technologies Llc Vertical memory device with bit line air gap
US20160111342A1 (en) 2014-10-17 2016-04-21 Lam Research Corporation Method and apparatus for characterizing metal oxide reduction
US10727122B2 (en) 2014-12-08 2020-07-28 International Business Machines Corporation Self-aligned via interconnect structures
KR102310834B1 (ko) 2014-12-22 2021-10-07 도쿄엘렉트론가부시키가이샤 그래프팅 중합체 물질의 사용으로 기판의 패턴화
US20160260779A1 (en) 2015-03-06 2016-09-08 Kabushiki Kaisha Toshiba Non-volatile resistive random access memory device
US9362165B1 (en) 2015-05-08 2016-06-07 Globalfoundries Inc. 2D self-aligned via first process flow
US9543148B1 (en) 2015-09-01 2017-01-10 Lam Research Corporation Mask shrink layer for high aspect ratio dielectric etch
US9716065B2 (en) 2015-09-14 2017-07-25 International Business Machines Corporation Via bottom structure and methods of forming
US9721888B2 (en) 2015-12-08 2017-08-01 International Business Machines Corporation Trench silicide with self-aligned contact vias
US10163704B2 (en) 2015-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
TWI621180B (zh) 2016-02-02 2018-04-11 東京威力科創股份有限公司 使用選擇性沉積之金屬與介層洞的自行對準
US11127629B2 (en) 2016-05-17 2021-09-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
TWI729457B (zh) 2016-06-14 2021-06-01 美商應用材料股份有限公司 金屬及含金屬化合物之氧化體積膨脹
KR20190047139A (ko) 2016-09-30 2019-05-07 어플라이드 머티어리얼스, 인코포레이티드 자가-정렬 비아들을 형성하는 방법들
TWI719262B (zh) 2016-11-03 2021-02-21 美商應用材料股份有限公司 用於圖案化之薄膜的沉積與處理
TW201833991A (zh) 2016-11-08 2018-09-16 美商應用材料股份有限公司 自對準圖案化之方法
US10403542B2 (en) 2017-06-10 2019-09-03 Applied Materials, Inc. Methods of forming self-aligned vias and air gaps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030143862A1 (en) * 1996-02-12 2003-07-31 Ravi Iyer Planarization using plasma oxidized amorphous silicon
US20050121768A1 (en) * 2003-12-05 2005-06-09 International Business Machines Corporation Silicon chip carrier with conductive through-vias and method for fabricating same
US20080160783A1 (en) * 2004-03-16 2008-07-03 Ishikawajima-Harima Heavy Industries Co., Ltd. Method For Manufacturing Semiconductor Device

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