CN109314079A - 金属及含金属化合物的氧化体积膨胀 - Google Patents
金属及含金属化合物的氧化体积膨胀 Download PDFInfo
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- 229910052721 tungsten Inorganic materials 0.000 claims description 14
- 229910052732 germanium Inorganic materials 0.000 claims description 11
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- 229910052703 rhodium Inorganic materials 0.000 claims description 3
- 229910052707 ruthenium Inorganic materials 0.000 claims description 3
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- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 claims description 2
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- 229910052746 lanthanum Inorganic materials 0.000 claims 1
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- 239000012495 reaction gas Substances 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
描述了包括在基板表面的至少一个特征上形成膜的方法。所述膜被膨胀以填充所述至少一个特征并造成所述膜从至少一个特征的生长。也描述了形成自我对准通孔的方法。
Description
技术领域
本发明大体上关于沉积与处理薄膜的方法。更具体地,本发明关于填充基板中狭窄沟槽的处理。
背景技术
半导体工业正在快速发展具有越来越小晶体管尺寸的芯片,以获得每单位面积更多的功能性。由于装置的尺寸持续缩小,装置间的间隙/空间也是持续缩小,增加将装置与另一装置实体上隔离的困难度。在装置之间的高深宽比沟槽/空间/间隙(通常是不规则形状)中,填充高质量介电材料,对于以现存方法来实施(包括间隙填充、硬掩模与间隔物应用)已经越来越有挑战性。
在此领域中有着用于具有更小临界尺寸的芯片设计的新方法的需求。此外,有着对于用于硬掩模与间隔物应用的高质量金属氧化物膜以及在基板上形成图案化薄膜的方法的持续需求。
发明内容
本发明的一个或更多实施例关于处理方法。提供其上具有至少一个特征的基板。至少一个特征从基板表面延伸一深度至底表面且具有由第一侧壁与第二侧壁所限定的宽度。膜是至少一个特征的底表面。膜被膨胀以填充此至少一个特征。
本发明额外的实施例关于处理方法,包含提供其上具有至少一个特征的基板表面。至少一个特征从基板表面延伸一深度至底表面且有由第一侧壁与第二侧壁所限定的宽度。金属膜形成在基板表面与至少一个特征的第一侧壁、第二侧壁和底表面上。金属膜被膨胀以填充至少一个特征,使得膜的顶部分包含金属氧化物、金属氮化物、金属硅化物和/或金属-锗物种,且膜的底部分包含此金属膜。
本发明进一步的实施例关于处理方法,包含提供其上具有至少一个特征的基板表面。至少一个特征从基板表面延伸一深度至底表面,且具有由第一侧壁与第二侧壁所限定的宽度。基板表面包括膜,膜填充至少一个特征并在基板表面上延伸。在基板表面上方的膜被移除,以留下基板表面与暴露的特征中的膜。特征中的膜被膨胀以造成膜的直上生长,以形成从至少一个特征延伸的膜的柱子。材料层形成在基板表面上,且膜的柱子被移除,以留下其上具有材料层的至少一个特征。
附图说明
为了本公开的上述特征可以被详细理解,通过参照实施例,其一部分在附图中示出,可获得在上文中简短总结的本发明的更明确的说明。然而,将注意到附图仅绘示本发明的典型实施例,且因而不被当作限制本发明的范围,由于本发明可允许其他等效实施例。
图1示出根据本发明的一个或更多实施例的基板特征的横截面视图;
图2A与图2B示出根据本发明的一个或更多实施例的间隙填充处理的横截面示意图;
图3示出根据本发明的一个或更多实施例的氧化膜的横截面视图;
图4示出根据本发明的一个或更多实施例的氧化膜的横截面视图;
图5A至图5C显示根据本发明的一个或更多实施例的处理的横截面示意图;
图6A至图6C示出根据本发明的一个或更多实施例的处理的横截面示意图;以及
图7A至图7D示出根据本发明的一个或更多实施例的处理的横截面示意图。
具体实施方式
在说明本发明的数个示例实施例之前,将理解到本公开并不局限于接下来的说明书中所说明的架构或处理步骤的细节。本发明能够是其他实施例且可以各种方式实行或执行。
本文中使用“基板”指称任何基板或形成在基板上的材料表面,在其上于制造处理期间执行膜处理。例如,在其上可执行处理的基板表面包括材料,诸如硅、氧化硅、应变硅、绝缘体上硅(SOI)、碳掺杂氧化硅、非晶硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石,及其他材料,诸如金属、金属氮化物、金属合金、与其他传导材料,取决于应用。基板包括而没有限制于半导体晶片。基板可暴露至预处理工艺以抛光、蚀刻、还原、氧化、羟基化、退火、UV固化、电子束固化和/或烘烤基板表面。除了直接在基板本身表面上的膜处理,在本发明中,公开的任何膜处理步骤也在形成于基板上的下方层之上执行,如之后更详细地公开,且术语“基板表面”是意指包括如文中所指示的此下方层。因此例如,在膜/层或部分膜/层已经被沉积在基板表面上的地方,新沉积的膜/层的暴露表面成为基板表面。
本发明的一个或更多实施例关于沉积金属氧化物膜的方法,用于任何共形、非共形和/或低至高深宽比间隙/沟槽/孔隙填充应用。本发明的实施例有利地提供在小尺寸的高深宽比(AR)结构中沉积膜(例如金属氧化物膜)的方法。本发明的某些实施例有利地提供填充间隙的方法,而不在间隙中形成接缝。本发明的一个或更多实施例有利地提供形成自我对准通孔的方法。
图1示出具有特征110的基板100的部分横截面视图。附图示出具有单一特征的基板以用于说明目的;然而,本领域技术人员将理解到可以有超过一个特征。特征110的形状可以是任何合适形状,包括但不限于沟槽与圆柱通孔。在特定实施例中,特征110是沟槽。如在此使用的,术语“特征”意味任何有意的表面不规则性。特征的合适例子包括但不限于具有顶部、两侧壁与底部的沟槽、具有顶部与从表面向上延伸的两侧壁的尖峰、及具有从带有开放底部的表面向下延伸的侧壁的通孔。特征或沟槽可具有任何合适深宽比(特征的深度对于特征的宽度的比例)。在某些实施例中,此深宽比是大于或等于约5:1、10:1、15:1、20:1、25:1、30:1、35:1或40:1。
基板100具有基板表面120。至少一个特征110在基板表面120中形成开口。特征110从基板表面120延伸一深度D至底表面112。特征110具有第一侧壁114与第二侧壁116,第一侧壁114与第二侧壁116限定特征110的宽度W。通过侧壁与底部所形成的开放区域也称为间隙。
参照图2A至图2B,基板100被提供用于处理。如在此使用的,术语“被提供”意味基板被放置进入用于进一步处理的位置或环境。
膜130形成在基板表面120上与特征110的壁及底部上。膜130可以是通过任何合适的处理而形成的任何合适的膜,处理包括但不限于化学气相沉积、等离子体增强化学气相沉积、原子层沉积、等离子体增强原子层沉积和/或物理气相沉积。在某些实施例中,膜130通过原子层沉积或等离子体增强原子层沉积形成。
在某些实施例中,膜130是金属膜或含金属膜。合适的金属膜包括但不限于包括Co、Mo、W、Ta、Ti、Ru、Rh、Cu、Fe、Mn、V、Nb、Hf、Zr、Y、Al、Sn、Cr、Os、U和/或La中的一个或多个的膜。在某些实施例中,金属膜包含钨。在某些特定实施例中,金属膜排除钨。在某些实施例中,金属膜排除Co、Mo、W、Ta、Ti、Ru、Rh、Cu、Fe、Mn、V、Nb、Hf、Zr、Y、Al、Sn、Cr、Os、U和/或La中的一个或多个。合适的含金属膜包括金属膜的衍生物。合适的金属膜的衍生物包括但不限于氮化物、硼化物、碳化物、氮氧化物、硼氧化物、碳氧化物、氮碳化物、碳化硼、氮化硼、硼碳氮化物、硼氧碳氮化物、碳氮氧化物、硼氧碳化物及硼氮氧化物。本领域技术人员将理解到沉积的金属膜可具有非化学计量数量的原子与金属膜。例如,被称为WN的膜可具有不同数量的钨与氮。WN膜可以是例如90原子%钨。使用WN以描述氮化钨膜意味着膜包含钨与氮原子且不应视为限制此膜于特定组成。在某些实施例中,膜基本上是由指明的原子所构成。例如,基本上由WN构成的膜意味着膜的组成为大于或等于约95%、98%或99%的钨与氮原子。在某些实施例中,膜130包含钨。在某些实施例中,膜130基本上由钨所构成。在一个或更多实施例中,膜包含钛。在某些实施例中,膜基本上由钛或氮化钛所构成。
在某些实施例中,膜130共形地形成在至少一个特征110上。如在本文中使用的,术语“共形”或“共形地”指黏附于暴露表面并均匀地覆盖暴露表面的层,其厚度相对于此膜的平均厚度具有少于1%的变化。例如,厚的膜可具有小于的厚度变化。此厚度与变化包括凹部的边缘、角落、侧边和底部。例如,本发明的各种实施例中通过ALD沉积的共形层可在沉积区上方提供在复杂表面上基本上均匀厚度的覆盖。
在某些实施例中,膜130是连续膜。如在本文中使用的,术语“连续”指覆盖整个暴露表面,而没有显现出在沉积层下方的材料的间隙或裸露凸点(bare spot)的层。连续层可具有表面面积小于膜的总表面面积的约1%的间隙或裸露凸点。
在某些实施例中,膜130可实质上无接缝地形成在特征110内。在某些实施例中,接缝115可形成在特征110的宽度W之内。接缝115可以是形成在特征110的壁114、116之间的任何间隙、空间或孔隙。
膜130可接着被膨胀以造成体积膨胀以填充特征并允许膜130从特征延伸。如图2B所示,膨胀此膜造成原始膜130的体积膨胀以填充特征。膜130的膨胀可在约10%至约1000%的范围内、或在约50%至约800%的范围内、或在约100%至约700%的范围内。在某些实施例中,膜130膨胀的量大于或等于约150%、200%、250%、300%或350%。在某些实施例中,膜130膨胀的量在约300%至约400%的范围内。如图2B所示,膜130的膨胀使得接缝115被填充。
在某些实施例中,通过将膜130暴露至氧化剂或氧化条件以将金属或含金属膜转化为金属氧化物膜来膨胀膜130。氧化剂可以是任何合适的氧化剂,包括但不限于O2、O3、N2O、H2O、H2O2、CO、CO2、NH3、N2/Ar、N2/He、N2/Ar/He及其组合。在某些实施例中,氧化条件包含热氧化、等离子体增强氧化、远程等离子体氧化、微波与射频(例如ICP、CCP)。
在某些实施例中,通过将膜130暴露至氮化剂或氮化条件,以将金属或含金属膜转化为金属氮化物膜来膨胀膜130。氮化剂可以是任何合适的氮化剂,包括但不限于氨、联氨、NO2、N2/Ar等离子体、N2/He等离子体、N2/Ar/He等离子体及其组合。在某些实施例中,氮化条件包含热氮化、等离子体增强氮化、远程等离子体氮化、微波与射频(例如ICP、CCP)。
在某些实施例中,通过将膜130暴露至硅化剂或硅化条件,以将金属或含金属膜转化为金属硅化物膜来膨胀膜130。硅化剂可以是任何合适的硅化剂,包括但不限于硅烷、二硅烷、三硅烷、四硅烷、五硅烷、六硅烷、三甲基硅烷、具有三甲基硅基取代基的化合物及其组合。在某些实施例中,硅化条件包含热硅化、等离子体增强硅化、远程等离子体硅化、微波与射频(例如ICP、CCP)。
在某些实施例中,通过将膜130暴露至锗试剂或锗化条件,以将金属或含金属膜转化为金属锗化物膜来膨胀膜130。锗化剂可以是任何合适的锗化剂,包括但不限于锗烷、二锗烷、三锗烷、四锗烷、五锗烷、六锗烷、三甲基锗、具有三甲基锗烷基取代基的化合物及其组合。在某些实施例中,锗化条件包含热锗化、等离子体增强锗化、远程等离子体锗化、微波与射频(例如ICP、CCP)。
处理膜或膜130的膨胀可发生在任何合适温度,取决于例如膜的组成和膨胀剂。在某些实施例中,膜膨胀在约25℃至约1100℃的范围内的温度发生。在某些实施例中,膨胀在大于或等于约250℃、300℃、350℃、400℃、450℃、500℃或550℃的温度下发生。
在某些实施例中,膜130沉积为在约至约的范围内的厚度、或在约至约的范围内的厚度。在一个或更多实施例中,膜130沉积为约的厚度且实质上在膜中不形成接缝。接缝的形成发生在膜的厚度在特征110的顶部部分上闭合处,于特征被膜填充之前。在某些实施例中,基板表面具有膜,带有在至少一个特征的侧壁之间的接缝。如在此使用的,术语“之间”意味着在接缝的任一侧上在接缝与特征的侧壁之间有一些膜。此接缝不限于正好在侧壁的中心中。
在膜130通过例如氧化膨胀期间,在基板表面120的顶上形成膜间隙140。间隙140可具有与氧化环境匹配的内容物或可以是不同的组成物。例如,使用氮等离子体的氧化环境可形成带有氮环境的间隙140。膨胀剂可影响间隙140的尺寸和内容物。例如,如果使用氮化剂以膨胀膜,间隙140可包括氮。
如图3所示,在膨胀期间,特征形状的保真度被维特在特征的顶部上,使得膜130从特征110直上地成长。如在此使用的,“直上地”意味着膜在间隙140周围形成表面144,而邻近于特征侧壁114的表面144的部分与侧壁114实质上共面。表面144与侧壁114共面,其中在侧壁114与表面144的接合处形成的角度是±10°。这种膨胀被预期以等向性地生长以形成蘑菇形顶部。膜130的膨胀以形成直线段142是非预期的。
在某些实施例中,在膨胀之前以掺杂剂掺杂膜130。掺杂剂可以在形成膜130的同时并入膜130中或在与膜沉积循序的单独的处理中并入膜130中。例如,沉积膜130可发生,之后在单独的处理中在相同的处理腔室或不同的处理腔室中以掺杂剂掺杂膜130。在某些实施例中,膜130的沉积与掺杂步骤发生在单一处理中。例如,膜前驱物与掺杂剂可共流进入处理腔室中以形成膜130。
某些实施例包括可选处理工艺。此处理工艺处理膜130以改善此膜的某些参数。在某些实施例中,处理工艺包含退火膜。在某些实施例中,可通过在用于沉积和/或还原的相同处理腔室中的原位退火而执行处理。合适的退火工艺包括但不限于快速热处理(RTP)或快速热退火(RTA)、尖波退火(spike anneal)、或UV固化、或电子束固化和/或激光退火。退火温度可在约500℃至900℃的范围内。在退火期间,环境的组成可包括H2、Ar、He、N2、NH3、SiH4等等的一个或多个。在退火期间的压力可在约100毫托至约760托(1atm)的范围内。
尽管这些处理可以被称为氧化,本领域技术人员将理解到本发明并不限于氧化反应以膨胀膜。使用氧化反应以说明各种实施例仅是为了方便,且不限制本发明的范围。参照图4,在某些实施例中,相较于在特征110的底部分131,在顶部分(直线段142)有着较大量的氧化。在某些实施例中,在特征110的底部分131几乎没有或没有膜130的氧化。图5A至图5C显示在特征110m(例如沟槽)的底部中沉积膜的方法。通过任何合适的技术沉积膜130。例如,在图5A中,可以通过原子层沉积在基板上沉积钨膜。在图5B中的膜130已经被氧化并膨胀以填充特征110。膜130的顶部分142包含沉积金属的氧化物(例如氧化钨)而膜130的底部分131维持未氧化(例如钨金属)。顶部分142与底部分131间的不同可用于从基板选择性蚀刻材料。如图5C所示,如果膜130被沉积于对于氧化物为选择性的蚀刻处理,在顶部分142的氧化物膜会被移除,留下在底部分131的金属膜。
图6A至图6C显示本公开的另一实施例。在图6A中,示出具有至少一个特征110(例如沟槽)的基板100。金属膜130沉积在特征110的底部中,如图6B所示。在图6C中,膜130可被氧化,使得膜膨胀以填充特征110。
图7A至7D显示本公开的另一实施例,其中形成自我对准通孔。在图7A中,提供具有氧化膜130的基板。可执行抛光或蚀刻处理以从基板100的表面120移除膜130的顶部,如图7B所示。膜130维持在特征110之内并填充特征110。如图7C所示,膜130可接着被氧化以造成膜130的向上成长。膜130的侧边维持与特征110的侧边实质上共面,使得有着从特征110延伸的柱子。材料层160沉积在基板100的表面120上。如图7D所示,膜130可被移除(例如通过蚀刻),以留下具有材料层160的特征110,材料层160对准于特征110的顶部上。
图4至图7D所示的实施例的氧化反应可以是氮化反应、硅化反应或锗化反应。本领域技术人员将理解可使用其他处理与反应以膨胀在特征内的膜或造成膜的直上生长。
根据一个或更多实施例,在形成此层之前和/或之后,基板受到处理。此处理可在相同腔室或在一个或更多分开的处理腔室中执行。在某些实施例中,基板从第一腔室移动到分开的第二腔室以进行其他处理。基板可直接从第一腔室移动至分开的处理腔室,或可从第一腔室移动到一个或更多移送腔室,然后移动到分开的处理腔室。因此,处理设备可包含以移送站连通的多个腔室。这种设备可被称为“群集工具”、“群集系统”等。
大体上,群集工具是模块系统,包含多个腔室,其执行各种功能,包括基板中心找寻与定向、除气、退火、沉积和/或蚀刻。根据一个或更多实施例,群集工具包括至少第一腔室与中央移送腔室。中央移送腔室可容纳机器人,其可在处理腔室之间与处理腔室中与装载闸腔室之间与装载闸腔室中搬运基板。移送腔室通常维持在真空状态并提供中间阶段以将基板从一个腔室搬运至另一个腔室和/或至定位在群集工具前端的装载闸腔室。可被适用于本发明的两种熟知的群集工具是与两者皆可从加利福尼亚州圣克拉拉市的应用材料公司取得。然而,腔室确切的布置与组合可为了执行本文所述处理的特定步骤而改变。可使用的其他处理腔室包括但不限于,周期层沉积(CLD)、原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、蚀刻、预清洗、化学清洗、诸如RTP的热处理、等离子体氮化、除气、定向、羟化及其他基板处理。通过执行群集工具上腔室中的处理,可避免大气杂质污染基板的表面,而不用在沉积后续膜之前氧化。
根据一个或更多实施例,基板连续地处于真空或“装载闸”状态,且当从一个腔室移动到下一个腔室时,不暴露至周围空气。移送腔室因此在真空下且被“抽气”于真空压力下。惰性气体可存在于处理腔室或移送腔室中。在某些实施例中,惰性气体用作净化气体,以移除某些或全部的反应物。根据一个或更多实施例,净化气体被注射于沉积腔室的出口,以避免反应物从沉积腔室移动至移送腔室和/或额外处理腔室。因此,惰性气体的流动在腔室的出口形成帘幕。
可在单一基板沉积腔室中处理基板,其中在处理另一个基板之前,单一基板被装载、处理及卸载。也可以与输送系统相似的连续方式处理基板,其中多个基板被独立地装载进腔室的第一部分,移动经过腔室并从腔室的第二部分卸载。腔室与相关输送系统的外形可形成直线路径或弯曲路径。此外,处理腔室可以是转盘,其中多个基板绕着中心轴移动并贯穿转盘路径暴露至沉积、蚀刻、退火、清洗、等等的处理。
在处理期间,基板可被加热或冷却。此加热或冷却可通过任何合适方式完成,包括但不限于,改变基板支撑件的温度及流动加热的或冷却的气体到基板表面。在某些实施例中,基板支撑件包括加热器/冷却器,其可被控制以传导地改变基板温度。在一个或更多实施例中,所使用的气体(反应气体或惰性气体)被加热或冷却,以局部地改变基板温度。在某些实施例中,加热器/冷却器定位在腔室内,邻近于基板表面以对流地改变基板温度。
在处理期间,基板也可以是固定的或被旋转。旋转的基板可被连续地旋转或以分离阶段旋转。例如,基板可被旋转贯穿整个处理,或基板可被小量地旋转以暴露至不同反应气体或净化气体之间。在处理期间旋转基板(连续地或阶段地)可通过最小化例如气流几何形状中局部可变性的影响而有助于产生更均匀的沉积或蚀刻。
贯穿本说明书的参照“一个实施例”、“某些实施例”、“一个或更多实施例”或“实施例”意味着接合实施例叙述的特定特征、结构、材料、或性质是包括在本公开的至少一个实施例中。因此,出现于本说明书的各种地方的诸如“在一个或更多实施例中”、“在某些实施例中”、“在一个实施例中”或“在实施例中”的词组不必指代本公开的同一个实施例。此外,特定特征、结构、材料、或性质可以任何合适方式组合于一个或更多实施例中。
虽然在本文已经参照特定实施例而描述本公开,将理解到这些实施例仅为本公开的原理与应用的说明。对于本领域技术人员将显而易见的是,在不悖离本公开的精神与范围的情况下,可对本公开的方法与设备进行各种修改与变化。因此,本发明旨在包括在所附权利要求及其等效物的范围内的修改与变化。
Claims (15)
1.一种处理方法,包含:
提供基板表面,所述基板表面上具有至少一个特征,所述至少一个特征从所述基板表面延伸一深度至底表面,所述至少一个特征具有宽度,所述宽度由第一侧壁与第二侧壁所限定;
在所述基板表面上与所述至少一个特征的所述第一侧壁、所述第二侧壁及所述底表面上形成膜;以及
膨胀所述膜以填充所述至少一个特征。
2.如权利要求1所述的方法,其中膨胀所述膜使得所述膜从所述至少一个特征直上地膨胀。
3.如权利要求2所述的方法,其中膨胀所述膜使得间隙形成在所述基板表面与所述膜之间。
4.如权利要求3所述的方法,其中所述膜包含Co、Mo、W、Ta、Ti、Ru、Rh、Cu、Fe、Mn、V、Nb、Hf、Zr、Y、Al、Sn、Cr或La中的一个或多个。
5.如权利要求4所述的方法,其中膨胀所述膜包含:将所述膜暴露至氧化剂、氮化剂、硅化剂、和/或包含锗的化合物,所述氧化剂包含O2、O3、N2O、H2O、H2O2、CO、CO2、NH3、N2/Ar、N2/He或N2/Ar/He中的一个或多个,所述氮化剂包含氨、联氨、NO2或氮等离子体中的一个或多个,所述硅化剂包含三甲基硅烷、硅烷、二硅烷中的一个或多个。
6.如权利要求1所述的方法,其中膨胀所述膜发生在大于约300℃的温度下。
7.如权利要求1所述的方法,其中沉积的膜是共形的。
8.如权利要求1所述的方法,其中所述特征具有大于或等于10:1的深宽比。
9.如权利要求1所述的方法,进一步包含用掺杂剂掺杂所述膜。
10.如权利要求8所述的方法,其中掺杂所述膜与所述膜的形成一起发生。
11.如权利要求8所述的方法,其中掺杂所述膜与所述膜的形成循序地执行。
12.如权利要求1所述的方法,进一步包含处理所述膜。
13.如权利要求11所述的方法,其中处理所述膜包含退火所述膜。
14.如权利要求1所述的方法,其中形成所述膜不在所述至少一个特征中形成接缝。
15.一种处理方法,包含:
提供基板表面,所述基板表面上具有至少一个特征,所述至少一个特征从所述基板表面延伸一深度至底表面,所述至少一个特征具有宽度,所述宽度由第一侧壁与第二侧壁所限定,所述基板表面包括膜,所述膜填充所述至少一个特征且在所述基板表面上方延伸;
移除所述基板表面上方的所述膜,以使所述基板表面与在所述特征中的膜暴露;
膨胀所述特征中的所述膜以造成所述膜的直上的生长,以形成所述膜的从所述至少一个特征延伸的柱子;
在所述基板表面上形成材料层;以及
移除所述膜的所述柱子,以留下所述至少一个特征及在所述基板表面上的所述材料层。
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PCT/US2017/037141 WO2017218462A1 (en) | 2016-06-14 | 2017-06-13 | Oxidative volumetric expansion of metals and metal containing compounds |
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Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI680535B (zh) | 2016-06-14 | 2019-12-21 | 美商應用材料股份有限公司 | 金屬及含金屬化合物之氧化體積膨脹 |
TWI719262B (zh) | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | 用於圖案化之薄膜的沉積與處理 |
US10224224B2 (en) | 2017-03-10 | 2019-03-05 | Micromaterials, LLC | High pressure wafer processing systems and related methods |
US10622214B2 (en) | 2017-05-25 | 2020-04-14 | Applied Materials, Inc. | Tungsten defluorination by high pressure treatment |
US10847360B2 (en) | 2017-05-25 | 2020-11-24 | Applied Materials, Inc. | High pressure treatment of silicon nitride film |
JP7190450B2 (ja) | 2017-06-02 | 2022-12-15 | アプライド マテリアルズ インコーポレイテッド | 炭化ホウ素ハードマスクのドライストリッピング |
TWI760540B (zh) * | 2017-08-13 | 2022-04-11 | 美商應用材料股份有限公司 | 自對準高深寬比結構及製作方法 |
WO2019036157A1 (en) | 2017-08-18 | 2019-02-21 | Applied Materials, Inc. | HIGH PRESSURE AND HIGH TEMPERATURE RECOVERY CHAMBER |
US10276411B2 (en) | 2017-08-18 | 2019-04-30 | Applied Materials, Inc. | High pressure and high temperature anneal chamber |
JP7274461B2 (ja) | 2017-09-12 | 2023-05-16 | アプライド マテリアルズ インコーポレイテッド | 保護バリア層を使用して半導体構造を製造する装置および方法 |
TWI723282B (zh) * | 2017-09-16 | 2021-04-01 | 美商應用材料股份有限公司 | 藉由矽化法之含金屬薄膜體積膨脹 |
US10643867B2 (en) | 2017-11-03 | 2020-05-05 | Applied Materials, Inc. | Annealing system and method |
KR102396319B1 (ko) | 2017-11-11 | 2022-05-09 | 마이크로머티어리얼즈 엘엘씨 | 고압 프로세싱 챔버를 위한 가스 전달 시스템 |
WO2019099125A1 (en) | 2017-11-16 | 2019-05-23 | Applied Materials, Inc. | High pressure steam anneal processing apparatus |
JP2021503714A (ja) | 2017-11-17 | 2021-02-12 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | 高圧処理システムのためのコンデンサシステム |
TWI794363B (zh) * | 2017-12-20 | 2023-03-01 | 美商應用材料股份有限公司 | 金屬薄膜之高壓氧化 |
KR102649241B1 (ko) | 2018-01-24 | 2024-03-18 | 어플라이드 머티어리얼스, 인코포레이티드 | 고압 어닐링을 사용한 심 힐링 |
KR20190104902A (ko) * | 2018-03-02 | 2019-09-11 | 마이크로머티어리얼즈 엘엘씨 | 금속 산화물들을 제거하기 위한 방법들 |
TWI751406B (zh) * | 2018-03-06 | 2022-01-01 | 美商應用材料股份有限公司 | 形成金屬硫系化物柱體之方法 |
KR102536820B1 (ko) | 2018-03-09 | 2023-05-24 | 어플라이드 머티어리얼스, 인코포레이티드 | 금속 함유 재료들을 위한 고압 어닐링 프로세스 |
US10714331B2 (en) | 2018-04-04 | 2020-07-14 | Applied Materials, Inc. | Method to fabricate thermally stable low K-FinFET spacer |
US10950429B2 (en) | 2018-05-08 | 2021-03-16 | Applied Materials, Inc. | Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom |
US10566188B2 (en) | 2018-05-17 | 2020-02-18 | Applied Materials, Inc. | Method to improve film stability |
US10704141B2 (en) | 2018-06-01 | 2020-07-07 | Applied Materials, Inc. | In-situ CVD and ALD coating of chamber to control metal contamination |
US10748783B2 (en) | 2018-07-25 | 2020-08-18 | Applied Materials, Inc. | Gas delivery module |
US10675581B2 (en) | 2018-08-06 | 2020-06-09 | Applied Materials, Inc. | Gas abatement apparatus |
CN112640065A (zh) | 2018-10-30 | 2021-04-09 | 应用材料公司 | 用于蚀刻用于半导体应用的结构的方法 |
WO2020101935A1 (en) | 2018-11-16 | 2020-05-22 | Applied Materials, Inc. | Film deposition using enhanced diffusion process |
WO2020117462A1 (en) | 2018-12-07 | 2020-06-11 | Applied Materials, Inc. | Semiconductor processing system |
EP3816100A1 (en) * | 2019-10-28 | 2021-05-05 | Murata Manufacturing Co., Ltd. | Mems element with increased density |
US11901222B2 (en) | 2020-02-17 | 2024-02-13 | Applied Materials, Inc. | Multi-step process for flowable gap-fill film |
US11101128B1 (en) * | 2020-03-12 | 2021-08-24 | Applied Materials, Inc. | Methods for gapfill in substrates |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08288407A (ja) * | 1995-04-12 | 1996-11-01 | Sony Corp | 半導体メモリ装置およびその製造方法 |
US20030143862A1 (en) * | 1996-02-12 | 2003-07-31 | Ravi Iyer | Planarization using plasma oxidized amorphous silicon |
US20050121768A1 (en) * | 2003-12-05 | 2005-06-09 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
US20070238288A1 (en) * | 2006-03-29 | 2007-10-11 | Tokyo Electron Limited | Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features |
US20080160783A1 (en) * | 2004-03-16 | 2008-07-03 | Ishikawajima-Harima Heavy Industries Co., Ltd. | Method For Manufacturing Semiconductor Device |
US7625820B1 (en) * | 2006-06-21 | 2009-12-01 | Novellus Systems, Inc. | Method of selective coverage of high aspect ratio structures with a conformal film |
US20110057317A1 (en) * | 2009-09-07 | 2011-03-10 | Tohoku University | Contact plug structure, semiconductor device, and method for forming contact plug |
US20130302980A1 (en) * | 2009-08-04 | 2013-11-14 | Anand Chandrashekar | Tungsten feature fill |
US20140284772A1 (en) * | 2013-03-19 | 2014-09-25 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and semiconductor device thereof |
US20150270215A1 (en) * | 2014-03-21 | 2015-09-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via pre-fill on back-end-of-the-line interconnect layer |
US20160043075A1 (en) * | 2014-08-07 | 2016-02-11 | International Business Machines Corporation | Raised metal semiconductor alloy for self-aligned middle-of-line contact |
Family Cites Families (99)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4671970A (en) | 1986-02-05 | 1987-06-09 | Ncr Corporation | Trench filling and planarization process |
EP0430403B1 (en) * | 1989-11-30 | 1998-01-07 | STMicroelectronics, Inc. | Method for fabricating interlevel contacts |
KR0165813B1 (ko) | 1995-04-12 | 1999-02-01 | 문정환 | 접속홀의 플러그 형성 방법 |
KR100223334B1 (ko) | 1996-06-29 | 1999-10-15 | 김영환 | 반도체소자의 금속배선형성방법 |
US6143653A (en) | 1998-10-04 | 2000-11-07 | Promos Technologies, Inc. | Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss |
KR20000026588A (ko) | 1998-10-21 | 2000-05-15 | 윤종용 | 콘택홀을 갖는 반도체 장치 및 그 제조방법 |
US6130151A (en) | 1999-05-07 | 2000-10-10 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing air gap in multilevel interconnection |
JP2001015479A (ja) | 1999-06-29 | 2001-01-19 | Toshiba Corp | 半導体装置の製造方法 |
WO2001013426A1 (en) | 1999-08-18 | 2001-02-22 | Steag Rtp Systems, Inc. | Method of producing copper features on semiconductor wafers |
US6576113B1 (en) | 1999-10-29 | 2003-06-10 | California Institute Of Technology | Method of electroplating of high aspect ratio metal structures into semiconductors |
US6373087B1 (en) | 2000-08-31 | 2002-04-16 | Agere Systems Guardian Corp. | Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses |
US7192803B1 (en) | 2000-10-13 | 2007-03-20 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with simultaneously formed interconnect and connection joint |
US6653200B2 (en) | 2001-01-26 | 2003-11-25 | Applied Materials, Inc. | Trench fill process for reducing stress in shallow trench isolation |
JP2002252281A (ja) | 2001-02-27 | 2002-09-06 | Sony Corp | 半導体装置およびその製造方法 |
US6528884B1 (en) | 2001-06-01 | 2003-03-04 | Advanced Micro Devices, Inc. | Conformal atomic liner layer in an integrated circuit interconnect |
US7279119B2 (en) | 2001-06-14 | 2007-10-09 | Ppg Industries Ohio, Inc. | Silica and silica-based slurry |
JP4959921B2 (ja) | 2002-03-28 | 2012-06-27 | プレジデント アンド フェロウズ オブ ハーバード カレッジ | 二酸化珪素ナノラミネートの蒸着 |
US8298933B2 (en) | 2003-04-11 | 2012-10-30 | Novellus Systems, Inc. | Conformal films on semiconductor substrates |
US7211844B2 (en) | 2004-01-29 | 2007-05-01 | International Business Machines Corporation | Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage |
US7521378B2 (en) | 2004-07-01 | 2009-04-21 | Micron Technology, Inc. | Low temperature process for polysilazane oxidation/densification |
US7244344B2 (en) | 2005-02-03 | 2007-07-17 | Applied Materials, Inc. | Physical vapor deposition plasma reactor with VHF source power applied through the workpiece |
WO2006118003A1 (ja) * | 2005-04-28 | 2006-11-09 | Hitachi Metals, Ltd. | 窒化珪素基板、その製造方法、それを用いた窒化珪素配線基板及び半導体モジュール |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
JP2007005381A (ja) | 2005-06-21 | 2007-01-11 | Matsushita Electric Ind Co Ltd | プラズマエッチング方法、及びプラズマエッチング装置 |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7351648B2 (en) * | 2006-01-19 | 2008-04-01 | International Business Machines Corporation | Methods for forming uniform lithographic features |
US7368394B2 (en) | 2006-02-27 | 2008-05-06 | Applied Materials, Inc. | Etch methods to form anisotropic features for high aspect ratio applications |
US7288463B1 (en) | 2006-04-28 | 2007-10-30 | Novellus Systems, Inc. | Pulsed deposition layer gap fill with expansion material |
US7956465B2 (en) | 2006-05-08 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing resistivity in interconnect structures of integrated circuits |
JP2008108757A (ja) | 2006-10-23 | 2008-05-08 | Matsushita Electric Works Ltd | 化合物半導体発光素子およびそれを用いる照明装置ならびに化合物半導体素子の製造方法 |
US7598170B2 (en) | 2007-01-26 | 2009-10-06 | Asm America, Inc. | Plasma-enhanced ALD of tantalum nitride films |
US20080242097A1 (en) | 2007-03-28 | 2008-10-02 | Tim Boescke | Selective deposition method |
US20090017631A1 (en) | 2007-06-01 | 2009-01-15 | Bencher Christopher D | Self-aligned pillar patterning using multiple spacer masks |
WO2008153674A1 (en) | 2007-06-09 | 2008-12-18 | Boris Kobrin | Method and apparatus for anisotropic etching |
US20090072409A1 (en) | 2007-09-14 | 2009-03-19 | International Business Machines Corporation | Interconnect Structures Incorporating Air-Gap Spacers |
US7541297B2 (en) | 2007-10-22 | 2009-06-02 | Applied Materials, Inc. | Method and system for improving dielectric film quality for void free gap fill |
US20100330805A1 (en) | 2007-11-02 | 2010-12-30 | Kenny Linh Doan | Methods for forming high aspect ratio features on a substrate |
US7985977B2 (en) | 2007-12-11 | 2011-07-26 | Hvvi Semiconductors, Inc. | Sacrificial pillar dielectric platform |
KR101477661B1 (ko) | 2008-07-17 | 2014-12-31 | 삼성전자주식회사 | 텅스텐 재성장을 통한 심 없는 텅스텐 패턴 및 그 패턴형성 방법 |
US8169031B2 (en) | 2008-08-26 | 2012-05-01 | International Business Machines Corporation | Continuous metal semiconductor alloy via for interconnects |
US8101456B2 (en) | 2008-10-01 | 2012-01-24 | International Business Machines Corporation | Method to reduce a via area in a phase change memory cell |
KR101026486B1 (ko) | 2008-10-22 | 2011-04-01 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
JP5133852B2 (ja) | 2008-11-13 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法及び半導体装置 |
KR101534678B1 (ko) | 2009-02-12 | 2015-07-08 | 삼성전자주식회사 | 텅스텐 콘택 플러그를 산소 분위기에서 rta 처리하고, rto 처리된 텅스텐 플러그를 수소 분위기에서 환원시키는 반도체 소자의 제조방법 |
US8435830B2 (en) | 2009-03-18 | 2013-05-07 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices |
US8575753B2 (en) * | 2009-05-27 | 2013-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a conductive structure including oxide and non oxide portions |
JP2011060803A (ja) | 2009-09-07 | 2011-03-24 | Toshiba Corp | 半導体装置 |
US8274065B2 (en) | 2009-10-19 | 2012-09-25 | Macronix International Co., Ltd. | Memory and method of fabricating the same |
US8778749B2 (en) | 2011-01-12 | 2014-07-15 | Sandisk Technologies Inc. | Air isolation in high density non-volatile memory |
US8900988B2 (en) | 2011-04-15 | 2014-12-02 | International Business Machines Corporation | Method for forming self-aligned airgap interconnect structures |
JP2011233922A (ja) | 2011-07-20 | 2011-11-17 | Ihi Corp | 素子間分離領域の形成方法 |
US8946082B2 (en) | 2011-09-16 | 2015-02-03 | GlobalFoundries, Inc. | Methods for forming semiconductor devices |
KR20130046664A (ko) | 2011-10-28 | 2013-05-08 | 삼성전자주식회사 | 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법 |
US9330939B2 (en) * | 2012-03-28 | 2016-05-03 | Applied Materials, Inc. | Method of enabling seamless cobalt gap-fill |
US8860001B2 (en) | 2012-04-09 | 2014-10-14 | Freescale Semiconductor, Inc. | ReRAM device structure |
US20140029181A1 (en) | 2012-07-27 | 2014-01-30 | Florian Gstrein | Interlayer interconnects and associated techniques and configurations |
US9245987B2 (en) | 2012-11-29 | 2016-01-26 | Micron Technology, Inc. | Semiconductor devices and fabrication methods |
US8901607B2 (en) | 2013-01-14 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating the same |
US9312220B2 (en) | 2013-03-12 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for a low-K dielectric with pillar-type air-gaps |
US9178011B2 (en) | 2013-03-13 | 2015-11-03 | Intermolecular, Inc. | Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate |
US9012322B2 (en) | 2013-04-05 | 2015-04-21 | Intermolecular, Inc. | Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition |
US9040421B2 (en) | 2013-05-03 | 2015-05-26 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits with improved contact structures |
US9219007B2 (en) | 2013-06-10 | 2015-12-22 | International Business Machines Corporation | Double self aligned via patterning |
US9793159B2 (en) | 2013-09-27 | 2017-10-17 | Intel Corporation | Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects |
CN110060972B (zh) | 2013-09-27 | 2024-02-23 | 英特尔公司 | 用于后段(beol)互连的自对准过孔及插塞图案化 |
US20150111374A1 (en) | 2013-10-18 | 2015-04-23 | International Business Machines Corporation | Surface treatment in a dep-etch-dep process |
US8951429B1 (en) | 2013-10-29 | 2015-02-10 | Applied Materials, Inc. | Tungsten oxide processing |
US9362413B2 (en) | 2013-11-15 | 2016-06-07 | Cbrite Inc. | MOTFT with un-patterned etch-stop |
US9312168B2 (en) | 2013-12-16 | 2016-04-12 | Applied Materials, Inc. | Air gap structure integration using a processing system |
US9236292B2 (en) | 2013-12-18 | 2016-01-12 | Intel Corporation | Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) |
JP6297884B2 (ja) | 2014-03-28 | 2018-03-20 | 東京エレクトロン株式会社 | タングステン膜の成膜方法 |
KR102377372B1 (ko) | 2014-04-02 | 2022-03-21 | 어플라이드 머티어리얼스, 인코포레이티드 | 인터커넥트들을 형성하기 위한 방법 |
US9368395B1 (en) | 2014-05-06 | 2016-06-14 | Globalfoundries Inc. | Self-aligned via and air gap |
US9299745B2 (en) | 2014-05-08 | 2016-03-29 | GlobalFoundries, Inc. | Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same |
US9281382B2 (en) | 2014-06-04 | 2016-03-08 | Stmicroelectronics, Inc. | Method for making semiconductor device with isolation pillars between adjacent semiconductor fins |
US9627318B2 (en) | 2014-06-16 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Interconnect structure with footing region |
US9679852B2 (en) | 2014-07-01 | 2017-06-13 | Micron Technology, Inc. | Semiconductor constructions |
US9324650B2 (en) | 2014-08-15 | 2016-04-26 | International Business Machines Corporation | Interconnect structures with fully aligned vias |
US9356047B2 (en) | 2014-08-18 | 2016-05-31 | Globalfoundries Inc. | Integrated circuits with self aligned contact structures for improved windows and fabrication methods |
US9508642B2 (en) | 2014-08-20 | 2016-11-29 | Globalfoundries Inc. | Self-aligned back end of line cut |
US9349637B2 (en) | 2014-08-21 | 2016-05-24 | Lam Research Corporation | Method for void-free cobalt gap fill |
US9735030B2 (en) | 2014-09-05 | 2017-08-15 | Fujifilm Planar Solutions, LLC | Polishing compositions and methods for polishing cobalt films |
US9515085B2 (en) | 2014-09-26 | 2016-12-06 | Sandisk Technologies Llc | Vertical memory device with bit line air gap |
US20160111342A1 (en) | 2014-10-17 | 2016-04-21 | Lam Research Corporation | Method and apparatus for characterizing metal oxide reduction |
US10727122B2 (en) | 2014-12-08 | 2020-07-28 | International Business Machines Corporation | Self-aligned via interconnect structures |
US9595441B2 (en) | 2014-12-22 | 2017-03-14 | Tokyo Electron Limited | Patterning a substrate using grafting polymer material |
US20160260779A1 (en) | 2015-03-06 | 2016-09-08 | Kabushiki Kaisha Toshiba | Non-volatile resistive random access memory device |
US9362165B1 (en) | 2015-05-08 | 2016-06-07 | Globalfoundries Inc. | 2D self-aligned via first process flow |
US9543148B1 (en) | 2015-09-01 | 2017-01-10 | Lam Research Corporation | Mask shrink layer for high aspect ratio dielectric etch |
US9716065B2 (en) | 2015-09-14 | 2017-07-25 | International Business Machines Corporation | Via bottom structure and methods of forming |
US9721888B2 (en) | 2015-12-08 | 2017-08-01 | International Business Machines Corporation | Trench silicide with self-aligned contact vias |
US10163704B2 (en) | 2015-12-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
SG11201806578XA (en) | 2016-02-02 | 2018-09-27 | Tokyo Electron Ltd | Self-alignment of metal and via using selective deposition |
US11127629B2 (en) | 2016-05-17 | 2021-09-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and fabricating method thereof |
TWI680535B (zh) | 2016-06-14 | 2019-12-21 | 美商應用材料股份有限公司 | 金屬及含金屬化合物之氧化體積膨脹 |
KR20190047139A (ko) | 2016-09-30 | 2019-05-07 | 어플라이드 머티어리얼스, 인코포레이티드 | 자가-정렬 비아들을 형성하는 방법들 |
TWI719262B (zh) | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | 用於圖案化之薄膜的沉積與處理 |
TW201833991A (zh) | 2016-11-08 | 2018-09-16 | 美商應用材料股份有限公司 | 自對準圖案化之方法 |
US10403542B2 (en) | 2017-06-10 | 2019-09-03 | Applied Materials, Inc. | Methods of forming self-aligned vias and air gaps |
-
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- 2017-06-09 TW TW106119157A patent/TWI680535B/zh not_active IP Right Cessation
- 2017-06-09 TW TW108129085A patent/TWI729457B/zh not_active IP Right Cessation
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- 2019-04-24 US US16/393,357 patent/US10741435B2/en not_active Expired - Fee Related
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08288407A (ja) * | 1995-04-12 | 1996-11-01 | Sony Corp | 半導体メモリ装置およびその製造方法 |
US20030143862A1 (en) * | 1996-02-12 | 2003-07-31 | Ravi Iyer | Planarization using plasma oxidized amorphous silicon |
US20050121768A1 (en) * | 2003-12-05 | 2005-06-09 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
US20080160783A1 (en) * | 2004-03-16 | 2008-07-03 | Ishikawajima-Harima Heavy Industries Co., Ltd. | Method For Manufacturing Semiconductor Device |
US20070238288A1 (en) * | 2006-03-29 | 2007-10-11 | Tokyo Electron Limited | Method for integrating a conformal ruthenium layer into copper metallization of high aspect ratio features |
US7625820B1 (en) * | 2006-06-21 | 2009-12-01 | Novellus Systems, Inc. | Method of selective coverage of high aspect ratio structures with a conformal film |
US20130302980A1 (en) * | 2009-08-04 | 2013-11-14 | Anand Chandrashekar | Tungsten feature fill |
US20110057317A1 (en) * | 2009-09-07 | 2011-03-10 | Tohoku University | Contact plug structure, semiconductor device, and method for forming contact plug |
US20140284772A1 (en) * | 2013-03-19 | 2014-09-25 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method and semiconductor device thereof |
US20150270215A1 (en) * | 2014-03-21 | 2015-09-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via pre-fill on back-end-of-the-line interconnect layer |
US20160043075A1 (en) * | 2014-08-07 | 2016-02-11 | International Business Machines Corporation | Raised metal semiconductor alloy for self-aligned middle-of-line contact |
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US10319624B2 (en) | 2019-06-11 |
TWI680535B (zh) | 2019-12-21 |
TWI729457B (zh) | 2021-06-01 |
US20170358483A1 (en) | 2017-12-14 |
JP2019521518A (ja) | 2019-07-25 |
WO2017218462A1 (en) | 2017-12-21 |
TW202011519A (zh) | 2020-03-16 |
TW201810530A (zh) | 2018-03-16 |
US20190259652A1 (en) | 2019-08-22 |
US10741435B2 (en) | 2020-08-11 |
KR20190005258A (ko) | 2019-01-15 |
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