CN109923661A - 用于图案化的膜的沉积与处理 - Google Patents
用于图案化的膜的沉积与处理 Download PDFInfo
- Publication number
- CN109923661A CN109923661A CN201780067193.4A CN201780067193A CN109923661A CN 109923661 A CN109923661 A CN 109923661A CN 201780067193 A CN201780067193 A CN 201780067193A CN 109923661 A CN109923661 A CN 109923661A
- Authority
- CN
- China
- Prior art keywords
- film
- group
- initial film
- substrate
- membrane material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008021 deposition Effects 0.000 title abstract description 22
- 238000012545 processing Methods 0.000 title description 34
- 239000000758 substrate Substances 0.000 claims abstract description 97
- 239000000463 material Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 59
- 239000012528 membrane Substances 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 239000002184 metal Substances 0.000 claims description 53
- 238000007254 oxidation reaction Methods 0.000 claims description 22
- 229910052721 tungsten Inorganic materials 0.000 claims description 21
- 230000003647 oxidation Effects 0.000 claims description 20
- 239000003795 chemical substances by application Substances 0.000 claims description 18
- 229910052804 chromium Inorganic materials 0.000 claims description 15
- 239000000203 mixture Substances 0.000 claims description 15
- 229910052758 niobium Inorganic materials 0.000 claims description 15
- 229910052742 iron Inorganic materials 0.000 claims description 14
- 229910052748 manganese Inorganic materials 0.000 claims description 14
- 229910052770 Uranium Inorganic materials 0.000 claims description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 229910052720 vanadium Inorganic materials 0.000 claims description 11
- JKQOBWVOAYFWKG-UHFFFAOYSA-N molybdenum trioxide Chemical compound O=[Mo](=O)=O JKQOBWVOAYFWKG-UHFFFAOYSA-N 0.000 claims description 10
- 238000003672 processing method Methods 0.000 claims description 10
- 230000001590 oxidative effect Effects 0.000 claims description 9
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 claims description 8
- 239000007800 oxidant agent Substances 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- XSXHWVKGUXMUQE-UHFFFAOYSA-N osmium dioxide Inorganic materials O=[Os]=O XSXHWVKGUXMUQE-UHFFFAOYSA-N 0.000 claims description 5
- SZVJSHCCFOBDDC-UHFFFAOYSA-N ferrosoferric oxide Chemical compound O=[Fe]O[Fe]O[Fe]=O SZVJSHCCFOBDDC-UHFFFAOYSA-N 0.000 claims description 4
- NUJOXMJBOLGQSY-UHFFFAOYSA-N manganese dioxide Chemical compound O=[Mn]=O NUJOXMJBOLGQSY-UHFFFAOYSA-N 0.000 claims description 4
- ZKATWMILCYLAPD-UHFFFAOYSA-N niobium pentoxide Chemical compound O=[Nb](=O)O[Nb](=O)=O ZKATWMILCYLAPD-UHFFFAOYSA-N 0.000 claims description 4
- 238000005121 nitriding Methods 0.000 claims description 4
- 229910000069 nitrogen hydride Inorganic materials 0.000 claims description 4
- 229910052762 osmium Inorganic materials 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 3
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 claims description 2
- AMWRITDGCCNYAT-UHFFFAOYSA-L manganese oxide Inorganic materials [Mn].O[Mn]=O.O[Mn]=O AMWRITDGCCNYAT-UHFFFAOYSA-L 0.000 claims description 2
- GEYXPJBPASPPLI-UHFFFAOYSA-N manganese(III) oxide Inorganic materials O=[Mn]O[Mn]=O GEYXPJBPASPPLI-UHFFFAOYSA-N 0.000 claims description 2
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 230000008961 swelling Effects 0.000 abstract description 8
- 238000000151 deposition Methods 0.000 description 22
- 230000008569 process Effects 0.000 description 16
- 239000010937 tungsten Substances 0.000 description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 11
- 238000000137 annealing Methods 0.000 description 10
- 229910052732 germanium Inorganic materials 0.000 description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 230000008859 change Effects 0.000 description 8
- 238000012546 transfer Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000011049 filling Methods 0.000 description 6
- -1 such as Substances 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 229910000078 germane Inorganic materials 0.000 description 5
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 239000011261 inert gas Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000746 purification Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000007872 degassing Methods 0.000 description 2
- 230000000640 hydroxylating effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 239000000376 reactant Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- YLAFGLJNWFUJLU-UHFFFAOYSA-N $l^{2}-germane;$l^{3}-germane Chemical compound [GeH2].[GeH2].[GeH2].[GeH3].[GeH3] YLAFGLJNWFUJLU-UHFFFAOYSA-N 0.000 description 1
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 241000208340 Araliaceae Species 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052580 B4C Inorganic materials 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- DCERHCFNWRGHLK-UHFFFAOYSA-N C[Si](C)C Chemical compound C[Si](C)C DCERHCFNWRGHLK-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JCXJVPUVTGWSNB-UHFFFAOYSA-N Nitrogen dioxide Chemical compound O=[N]=O JCXJVPUVTGWSNB-UHFFFAOYSA-N 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- LUXIMSHPDKSEDK-UHFFFAOYSA-N bis(disilanyl)silane Chemical compound [SiH3][SiH2][SiH2][SiH2][SiH3] LUXIMSHPDKSEDK-UHFFFAOYSA-N 0.000 description 1
- INAHAJYZKVIDIZ-UHFFFAOYSA-N boron carbide Chemical compound B12B3B4C32B41 INAHAJYZKVIDIZ-UHFFFAOYSA-N 0.000 description 1
- 229910052810 boron oxide Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001722 carbon compounds Chemical class 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 210000000262 cochlear duct Anatomy 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- VXGHASBVNMHGDI-UHFFFAOYSA-N digermane Chemical compound [Ge][Ge] VXGHASBVNMHGDI-UHFFFAOYSA-N 0.000 description 1
- LICVGLCXGGVLPA-UHFFFAOYSA-N disilanyl(disilanylsilyl)silane Chemical compound [SiH3][SiH2][SiH2][SiH2][SiH2][SiH3] LICVGLCXGGVLPA-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000006722 reduction reaction Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 125000001424 substituent group Chemical group 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- WLKSSWJSFRCZKL-UHFFFAOYSA-N trimethylgermanium Chemical compound C[Ge](C)C WLKSSWJSFRCZKL-UHFFFAOYSA-N 0.000 description 1
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 1
- 229940094989 trimethylsilane Drugs 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76227—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Vapour Deposition (AREA)
- Formation Of Insulating Films (AREA)
- Physical Vapour Deposition (AREA)
Abstract
描述包含下列步骤的方法:沉积膜材料,以在基板表面中的沟槽中形成初始膜。处理所述膜,以使所述膜膨胀,使所述膜生长超过基板表面。
Description
技术领域
本公开内容大体上涉及沉积和处理薄膜的方法。更具体地,本公开内容涉及用于填充基板中的沟槽的工艺。
背景技术
半导体工业正快速发展具有越来越小晶体管尺寸的芯片,以获得每单位面积更多的功能性。随着装置的尺寸持续缩小,装置间的间隙/空间也持续缩小,增加将装置彼此物理隔离的困难度。以现有方法(包括间隙填充、硬模与间隔件应用)来实施将高质量介电材料填充在装置之间的高深宽比沟槽/空间/间隙(通常是不规则形状)中,变得越来越有挑战性。选择性沉积方法通常包括:在基板上沉积掩模材料,和图案化掩模材料以形成图案化的掩模。在掩模的图案化之后,可透过图案化的掩模暴露基板的区域。可自基板移除图案化的掩模,以暴露基板的未注入的区域,并且可将材料选择性地沉积在基板的选定区域上。
在本领域中需要用于具有更小临界尺寸的芯片设计的新方法。此外,持续需要用于硬模与间隔件(spacer)应用的高质量金属氧化物膜以及用于在基板上形成图案化的膜的方法。
发明内容
本公开内容的一个或多个实施方式针对处理方法。一个实施方式涉及提供基板表面,所述基板表面具有至少一个沟槽,所述至少一个沟槽可从基板表面到底部表面延伸某一深度,所述至少一个沟槽具有由第一侧壁和第二侧壁限定的宽度;选择性地沉积膜材料,以形成初始膜,所述初始膜具有在沟槽中而不在基板表面上的膜材料体积,所述膜材料具有大于2的Pilling-Bedworth比值,并且包含选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U、W和V组成的群组的材料。此一个实施方式的方法可进一步包括:处理初始膜,以使膜材料体积膨胀,以提供膨胀膜,所述膨胀膜延伸超过基板表面。处理初始膜可包括使初始膜暴露于氧化环境或氮化环境。
附图说明
可通过参照实施方式而获得简要概述于上的本公开内容的更具体描述,以此方式可详细理解本公开内容的上述特征,在附图中图示一些实施方式。然而,将注意到附图仅图示本公开内容的典型实施方式,因而不视为本公开内容的范围的限制,因为本公开内容可允许其他等效实施方式。
图1示出根据本公开内容的一个或多个实施方式的基板特征的横截面图;
图2A和图2B示出根据本公开内容的一个或多个实施方式的间隙填充工艺的横截面示意图;
图3示出根据本公开内容的一个或多个实施方式的氧化膜的横截面图;
图4示出根据本公开内容的一个或多个实施方式的氧化膜的横截面图;
图5A至图5C示出根据本公开内容的一个或多个实施方式的工艺的横截面示意图;
图6A至图6C示出根据本公开内容的一个或多个实施方式的工艺的横截面示意图;
图7A至图7D示出根据本公开内容的一个或多个实施方式的工艺的横截面示意图;并且
图8A至图8B示出根据本公开内容的一个或多个实施方式的工艺的横截面示意图。
具体实施方式
在说明本公开内容的若干示例性实施方式之前,应理解本公开内容不限于接下来的说明书中所阐述的架构或处理步骤的细节。本公开内容允许其它实施方式并且能够以各种方式实行或执行。
本文中使用的“基板”表示任何基板或形成在基板上的材料表面,于制造处理期间在所述基板或形成在基板上的材料表面上进行膜处理。例如,取决于应用,基板表面(在所述基板表面上可执行处理)可包括以下材料,诸如,硅、氧化硅、应变硅、绝缘体上硅(SOI)、碳掺杂氧化硅、非晶硅、掺杂硅、锗、砷化镓、玻璃、蓝宝石和任何其它材料(诸如金属、金属氮化物、金属合金和其它导电材料)。基板可包括而不限于半导体晶片。可将基板暴露于预处理工艺,以抛光、蚀刻、还原、氧化、羟基化、退火、UV固化、电子束固化和/或烘烤基板表面。除了直接在基板本身的表面上进行膜处理,在本公开内容中,也可如下文更详细地公开的在形成于基板上的下方层(underlayer)之上进行任何所公开的膜处理步骤,并且术语“基板表面”欲包括如上下文中所指的这样的下方层。因此,举例而言,在膜/层或部分的膜/层已经沉积在基板表面上的情况下,新沉积的膜/层的暴露表面成为基板表面。
本公开内容的一个或多个实施方式针对用于任何共形、非共形和/或低至高深宽比间隙/沟槽/空隙填充应用的沉积金属氧化物膜的方法。本公开内容的实施方式有利地提供在小尺寸的高深宽比(AR)结构中沉积膜(例如,金属氧化物膜)的方法。本公开内容的某些实施方式有利地提供填充间隙的方法,而不在间隙中形成缝。本公开内容的一个或多个实施方式有利地提供形成自对准过孔的方法。
图1示出具有特征110的基板100的部分横截面视图。为了说明的目的,图示出具有单一特征的基板;然而,本领域技术人员将理解可以有多于一个的特征。特征110的形状可为任何合适形状,包括但不限于沟槽和圆柱状过孔。在特定实施方式中,特征110是沟槽。这样使用时,术语“特征”意味着任何有意的表面不规则性(intentional surfaceirregularity)。特征的合适例子包括但不限于:沟槽,所述沟槽具有顶部、两个侧壁和底部;峰,所述峰具有顶部和从表面向上延伸的两个侧壁;和过孔,所述过孔具有侧壁,所述侧壁从带有开放底部的表面向下延伸。特征或沟槽可具有任何合适的深宽比(特征的深度对特征的宽度的比值)。在某些实施方式中,深宽比为大于或等于约5:1、10:1、15:1、20:1、25:1、30:1、35:1或40:1。
基板100具有基板表面120。至少一个特征110在基板表面120中形成开口。特征110从基板表面120到底部表面112延伸达深度D。特征110具有第一侧壁114与第二侧壁116,第一侧壁114与第二侧壁116限定特征110的宽度W。由侧壁与底部形成的开放区域也称为间隙。
参照图2A至图2B,基板100被提供来用于处理。这样使用时,术语“被提供(provided)”意味着基板被放置进入某位置或环境,以用于进一步处理。
膜130形成在基板表面120上和特征110的壁与底部上。膜130可为由任何合适的工艺形成的任何合适的膜,所述合适的工艺包括但不限于:化学气相沉积、等离子体增强化学气相沉积、原子层沉积、等离子体增强原子层沉积和/或物理气相沉积。在某些实施方式中,通过原子层沉积或等离子体增强原子层沉积形成膜130。
在某些实施方式中,膜130是金属膜或含金属膜。合适的金属膜包括但不限于:具有大于2、大于2.25或大于2.5的Pilling-Bedworth比值的金属。Pilling-Bedworth比值指的是:金属氧化物或金属氮化物的基本单元(elementary cell)的体积与对应金属的基本单元的体积的比值,其中所述氧化物或氮化物由所述对应金属形成。Pilling-Bedworth比值定义为V氧化物/V金属或V氮化物/V金属,其中V为体积。为了确定金属氧化物的Pilling-Bedworth比值,V氧化物同等于金属氧化物的分子量乘金属的密度,并且V金属同等于所述氧化物的每一分子的金属原子数量乘所述金属的原子量再乘所述氧化物的密度。为了确定金属氮化物的Pilling-Bedworth比值,V氮化物同等于金属氮化物的分子量乘金属的密度,并且V金属同等于所述氮化物的每一分子的金属原子数量乘所述金属的原子量再乘氮化物的密度。这样的膜的实例包括Co、Mo、W、Ta、Ti、Ru、Rh、Cu、Fe、Mn、V、Nb、Hf、Zr、Y、Al、Sn、Cr、Os、U和/或La中的一种或多种。在某些实施方式中,金属选自由Co、Fe、Mn、Nb、Os、Ta、U和V组成的群组。在某些实施方式中,金属具有大于2.5的Pilling-Bedworth比值,并且选自由Mo、Os和V组成的群组。在某些具体实施方式中,金属膜包含钨。在某些具体实施方式中,金属膜不包括钨。合适的含金属膜包括金属膜的衍生物。金属膜的合适的衍生物包括但不限于:氮化物、硼化物、碳化物、氮氧化物、硼氧化物(oxyboride)、碳氧化物、碳氮化物、硼碳化物、硼氮化物(boronitride)、硼碳氮化物、硼氧碳氮化物、氧碳氮化物、硼氧碳化物和硼氧氮化物。本领域技术人员将理解,沉积的金属膜可具有非化学计量数量的原子与金属膜。例如,被称为WN的膜可具有不同数量的钨与氮。WN膜可例如为90原子百分比的钨。使用WN以描述氮化钨膜意味着所述膜包含钨与氮原子,而不应视为将所述膜限制于特定组成。在某些实施方式中,所述膜基本上是由指定的原子构成。举例而言,基本上由WN构成的膜意指所述膜的组成是大于或等于约95%、98%或99%的钨与氮原子。在某些实施方式中,膜130包含钨。在某些实施方式中,膜130基本上由钨构成。在一个或多个实施方式中,所述膜包含钛。在某些实施方式中,所述膜基本上由钛或氮化钛构成。
在某些实施方式中,膜130共形地形成在至少一个特征110上。如本文中所使用的,术语“共形(conformal)”或“共形地(conformally)”表示粘附于暴露表面并均匀地覆盖暴露表面的层,并且所述层的厚度相对于所述膜的平均厚度具有小于1%的变化。举例而言,厚的膜可具有小于的厚度变化。此厚度和变化包括凹槽的边缘、角落、侧边和底部。举例而言,本公开内容的各种实施方式中通过ALD沉积的共形层会在复杂表面上的沉积区域上方提供基本上均匀厚度的覆盖。
在某些实施方式中,膜130为连续膜。如在本文中所使用的,术语“连续(continuous)”表示覆盖整个暴露表面而没有间隙或裸露点(bare spot)的层,所述间隙或裸露点(bare spot)显现出在沉积层下方的材料。连续层可具有表面积小于膜的总表面积的约1%的间隙或裸露点。
在某些实施方式中,大体上无缝地在特征110内形成膜130。在某些实施方式中,缝115可形成在特征110的宽度W之内。缝115可为形成在特征110的壁114、116之间的任何间隙、空间或空隙。
接着可使膜130膨胀,以造成体积膨胀,以填充特征并允许膜130从特征延伸。如图2B所示,使所述膜膨胀造成初始膜130的体积膨胀以填充特征。膜130的膨胀可在约10%至约1000%的范围内、或在约50%至约800%的范围内、或在约100%至约700%的范围内。在某些实施方式中,膜130膨胀的量大于或等于约150%、200%、250%、300%或350%。在某些实施方式中,膜130膨胀的量在约300%至约400%的范围内。如图2B所示,膜130的膨胀使得缝115被填充。
在某些实施方式中,可通过暴露至氧化剂或氧化条件来将金属或含金属膜转化为金属氧化物膜,而使膜130膨胀。氧化剂可为任何合适的氧化剂,包括但不限于:O2、O3、N2O、H2O、H2O2、CO、CO2、NH3、N2/Ar、N2/He、N2/Ar/He和上述氧化剂的组合。在某些实施方式中,氧化条件包含热氧化、等离子体增强氧化、远程等离子体氧化、微波与射频(例如,ICP、CCP)。
在某些实施方式中,可通过暴露至氮化剂或氮化条件来将金属或含金属膜转化为金属氮化物膜,而使膜130膨胀。氮化剂可为任何合适的氮化剂,包括但不限于:氨、肼、NO2、N2/Ar等离子体、N2/He等离子体、N2/Ar/He等离子体和上述氮化剂的组合。在某些实施方式中,氮化条件包含热氮化、等离子体增强氮化、远程等离子体氮化、微波与射频(例如,ICP、CCP)。
在某些实施方式中,可通过暴露至硅化剂或硅化条件来将金属或含金属膜转化为金属硅化物膜,而使膜130膨胀。硅化剂可为任何合适的硅化剂,包括但不限于:硅烷、乙硅烷、丙硅烷、丁硅烷、戊硅烷、己硅烷、三甲基硅烷、具有三甲基硅基取代基的化合物和上述硅化剂的组合。在某些实施方式中,硅化条件包含热硅化、等离子体增强硅化、远程等离子体硅化、微波与射频(例如,ICP、CCP)。
在某些实施方式中,可通过暴露至锗试剂或锗化条件来将金属或含金属膜转化为金属锗化物膜,而使膜130膨胀。锗化剂可为任何合适的锗化剂,包括但不限于:锗烷(germane)、乙锗烷、丙锗烷、丁锗烷、戊锗烷、己锗烷、三甲基锗、具有三甲基锗烷基取代基的化合物和上述锗化剂的组合。在某些实施方式中,锗化条件包含热锗化、等离子体增强锗化、远程等离子体锗化、微波与射频(例如,ICP、CCP)。
处理膜或膜130的膨胀可发生在任何合适的温度下,例如,取决于膜的组成和膨胀剂。在某些实施方式中,膜膨胀发生在约25℃至约1100℃的范围内的温度下。在某些实施方式中,膨胀发生在大于或等于约250℃、300℃、350℃、400℃、450℃、500℃或550℃的温度下。
在某些实施方式中,将膜130沉积达约至约的范围内的厚度,或达约至约的范围内的厚度。在一个或多个实施方式中,将膜130沉积达约的厚度,并且大体上没有缝形成在膜中。缝的形成可在特征被膜填充之前发生在靠近于特征110的顶部分上的膜的厚度处。在某些实施方式中,基板表面具有膜,而所述膜具有在至少一个特征的侧壁之间的缝。这样使用时,术语“之间(between)”意味着在缝的任一侧上有着某些膜位于缝与特征的侧壁之间。缝不限于正好在侧壁的中心内。
在通过例如氧化而使膜130膨胀期间,间隙140形成在基板表面120的顶上。间隙140可具有与氧化环境匹配的内容物或可为不同的组成。举例而言,使用氮等离子体的氧化环境可形成带有氮环境的间隙140。膨胀剂可影响间隙140的尺寸和内容物。举例而言,如果使用氮化剂来使膜膨胀,那么间隙140可包括氮。
如图3所示,在膨胀期间,在特征的顶部上维持特征形状的保真度(fidelity),使得膜130从特征110直上地生长。这样使用时,“直上地(straightup)”意指膜围绕间隙140形成表面144,并且邻近于特征侧壁114的表面144的部分与侧壁114大体上共面。表面144与侧壁114在形成于侧壁114与表面144的接合处的角度是±10°的情况下共面。以前预期这种膨胀各向同性地生长以形成蘑菇形顶部(mushroom shaped top)。以前未预期到膜130的膨胀形成直的片段142。
在某些实施方式中,在膨胀之前用掺杂剂掺杂膜130。掺杂剂可于形成膜130的相同时间并入膜130中,或在与膜沉积顺序的单独工艺中并入膜130中。举例而言,可在沉积膜130之后在相同工艺腔室或不同工艺腔室中,在单独的工艺中用掺杂剂掺杂膜130。在某些实施方式中,膜130的沉积与掺杂发生在单一工艺中。举例而言,可将膜前驱物与掺杂剂共同流入处理腔室中,以形成膜130。
某些实施方式包括可选的处理工艺。所述处理工艺处理膜130,以改善膜的某些参数。在某些实施方式中,处理工艺包含退火所述膜。在某些实施方式中,可通过在用于沉积和/或还原的相同处理腔室中原位退火来进行处理。合适的退火工艺包括但不限于:快速热处理(RTP)或快速热退火(RTA)、尖峰退火(spike anneal)、或UV固化、或电子束固化和/或激光退火。退火温度可在约500℃至900℃的范围内。在退火期间,环境的组成可包括以下项中的一种或多种:H2、Ar、He、N2、NH3、SiH4等等。退火期间的压力可在约100mTorr至约1atm的范围内。
尽管这些工艺可称为氧化,本领域技术人员将理解到本公开内容不限于以氧化反应来使膜膨胀。使用氧化反应来说明各种实施方式仅是为了方便,并且不限制本公开内容的范围。参照图4,在某些实施方式中,相较于在特征110的底部分131处,在顶部分(直的片段142)有较大量的氧化。在某些实施方式中,在特征110的底部分131有少量或没有膜130的氧化。图5A至图5C图示出在特征110m(例如,沟槽)的底部中沉积膜的方法。通过任何合适的技术来沉积膜130。举例而言,在图5A中,可通过原子层沉积在基板上沉积钨膜。图5B中的膜130已被氧化并膨胀以填充特征110。膜130的顶部分142包含沉积的金属的氧化物(例如,氧化钨),并且膜130的底部分131保持未氧化(例如,钨金属)。顶部分142与底部分131之间的差异可用于从基板选择性地蚀刻材料。如图5C所示,如果膜130沉积到对氧化物具选择性的蚀刻工艺,可移除在顶部分142处的氧化物膜,留下在底部分131处的金属膜。
图6A至图6C示出本公开内容的另一个实施方式。在图6A中示出具有至少一个特征110(例如,沟槽)的基板100。如图6B所示,金属膜130沉积在特征110的底部中。在图6C中,膜130可被氧化,使得膜膨胀以填充特征110。
图7A至图7D示出本公开内容的另一实施方式,其中形成自对准过孔。在图7A中,提供具有经氧化的膜130的基板。可进行抛光或蚀刻工艺,以从基板100的表面120移除膜130的顶部,如图7B所示。膜130保持在特征110内并填充特征110。如图7C所示,膜130可接着被氧化以造成膜130向上生长。膜130的侧边保持与特征110的侧边大体上共面,使得柱状体从特征110延伸。将材料层160沉积在基板100的表面120上。如图7D所示,膜130可被移除(例如,通过蚀刻),以留下具有在特征110的顶部上对准的材料层160的特征110。
现请参照图8A和图8B图,在另一个实施方式中,处理方法包括:提供具有表面110的基板100,表面110包括至少一个特征120,特征120呈沟槽型而从基板表面110朝底部表面112延伸深度“D”。沟槽120具有由第一侧壁114与第二侧壁116限定的宽度“W”。根据所示的实施方式,处理方法包括:选择性地沉积膜材料,以形成初始膜130,初始膜130具有在沟槽120中而不在基板表面110上的膜材料体积,膜材料具有大于2的Pilling-Bedworth比值,并且包含选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U、W和V组成的群组的材料。处理方法进一步包含:处理初始膜130,以使膜材料体积膨胀,以提供膨胀膜140,膨胀膜140延伸超过基板表面110。在一个实施方式中,初始膜130填充沟槽的容积的至少10%。在其它实施方式中,初始膜130填充沟槽的容积的至少15%、20%、25%、30%、35%、40%、45%、50%、55%、60%、65%、70%、75%、80%、85%、90%、95%或100%。在所示的实施方式中,初始膜从第一侧壁114延伸至第二侧壁。在一个或多个实施方式中,处理初始膜造成膜体积增加至少10%、20%、30%、40%、50%、60%、70%、80%、90%、100%、150%、200%、250%、300%、350%或400%。如图8B所示,膨胀膜140可形成从沟槽120延伸的柱状体150。当以具有超过约2的Pilling-Bedworth比值的金属填充多个沟槽120(未示出),并经处理以使初始膜体积膨胀时,可形成多个柱状体150来提供图案,而无需使用掩模。
在具体实施方式中,膜材料可选自由Co、Fe、Mn、Nb、Os、Ta、U和V组成的群组。在一个实施方式中,处理初始膜包含:使初始膜暴露于氧化环境。在处理初始膜包含使初始膜暴露于氧化环境的实施方式中,膨胀膜包含选自由CoO、Fe2O3、Fe3O4、MnO2,Mn2O3、Mn3O4、MoO3、Nb2O5、Ta2O5、OsO2、UO2和V2O5组成的群组的材料。
在某些实施方式中,膜材料具有大于2.5的Pilling-Bedworth比值,并且选自由Mo、Os和V组成的群组。在膜材料具有大于2.5的Pilling-Bedworth比值并且选自由Mo、Os和V组成的群组的某些实施方式中,处理初始膜包含:使初始膜暴露于氧化环境。在这样的实施方式中,膨胀膜包含选自由MoO3、OsO2和V2O5组成的群组的材料。
在某些实施方式中,处理初始膜包含:使初始膜暴露于氮化环境。在使初始膜暴露于氮化环境的实施方式中,膜材料选自由Cr、Mo和Os组成的群组。在这样的实施方式中,膨胀膜包含选自由CrN2、MoN2和OsN2组成的群组的材料。在发生使初始膜氮化的其它实施方式中,Pilling Bedworth比值为大于1.5,并且用于初始膜的膜材料为选自由Cr、Mo、OS、Co、Cu、Nb、NI、Rh、Sr、Ta、Ru和W组成的群组的金属。
在某些实施方式中,处理初始膜包含:使初始膜暴露于氧化剂和/或氮化剂,所述氧化剂包含O2、O3、N2O、H2O、H2O2、CO、CO2、NH3、N2/Ar、N2/He或N2/Ar/He中的一种或多种,所述氮化剂包含氨、肼、NO2或氮等离子体中的一种或多种。
在某些实施方式中,处理初始膜可发生在低于约300℃或低于450℃的温度下。
另一个实施方式涉及处理方法,所述处理方法包含:提供基板表面,所述基板表面具有至少一个沟槽,所述至少一个沟槽从基板表面到底部表面延伸某一深度,所述至少一个沟槽具有由第一侧壁和第二侧壁限定的宽度;选择性地沉积膜材料,以形成初始膜,所述初始膜具有在沟槽中而不在基板表面上的膜材料体积,所述膜材料具有大于2的Pilling-Bedworth比值,并且包含选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U、W和V组成的群组的材料;和处理初始膜,以形成金属的氮化物,以使膜材料体积膨胀,以提供膨胀膜,膨胀膜延伸超过基板表面,所述金属选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U、W或V组成的群组。在具体实施方式中,膜材料包含选自由Cr、Mo和Os组成的群组的金属,并且膨胀膜包含选自由CrN2、MoN2和OsN2组成的群组的材料。
另一个实施方式涉及处理方法,所述处理方法包含:提供基板表面,所述基板表面具有至少一个沟槽,所述至少一个沟槽从基板表面到底部表面延伸某一深度,所述至少一个沟槽具有由第一侧壁和第二侧壁限定的宽度;选择性地沉积膜材料,以形成初始膜,所述初始膜具有在沟槽中而不在基板表面上的膜材料体积,膜材料具有大于2的Pilling-Bedworth比值,并且包含选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U和V组成的群组的材料;和处理初始膜,以形成金属的氧化物,以使膜材料体积膨胀,以提供膨胀膜,所述膨胀膜延伸超过基板表面,所述金属选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U或V组成的群组。在具体实施方式中,膜材料包含选自由Co、Fe、Mn、Nb、Os、Ta、U和V组成的群组的金属,并且膨胀膜包含选自由MoO3、OsO2和V2O5组成的群组的材料。在具体实施方式中,处理初始膜发生在高于约400℃的温度下。在具体实施方式中,处理初始膜发生在高于约350℃的温度下。
图4至图8B所示的实施方式的氧化反应可为氮化反应、硅化反应或锗化反应。本领域技术人员将理解到,可使用其它工艺和反应,以使特征内的膜膨胀或造成膜直上地生长。
根据一个或多个实施方式,在形成层之前和/或之后,基板受到处理。可在相同腔室或在一个或多个分开的处理腔室中进行所述处理。在某些实施方式中,将基板从第一腔室移动到分开的第二腔室以进行另外的处理。可将基板从第一腔室直接移动至分开的处理腔室,或可将基板从第一腔室移动到一个或多个传送腔室,接着移动到分开的处理腔室。因此,处理设备可包含与传送站连通的多个腔室。这种设备可称为“群集工具(clustertool)”或“群集系统(clustered system)”等。
一般来说,群集工具是包含多个腔室的模块化系统,多个腔室进行各种功能,包括基板中心寻找和定向、除气、退火、沉积和/或蚀刻。根据一个或多个实施方式,群集工具包括至少第一腔室和中央传送腔室。中央传送腔室可容纳机械手,而机械手可在处理腔室与装载锁定腔室之间与之中使基板往复运动。传送腔室通常维持在真空条件,并提供中间阶段以使基板从一个腔室往复运动到另一个腔室和/或到定位在群集工具前端的装载锁定腔室。可适用于本发明的两种广为人知的群集工具是与两者皆可从加利福尼亚州圣克拉拉市的应用材料公司获得。然而,可出于进行本文所述工艺的特定步骤的目的而改变腔室的确切布置与组合。可使用的其它处理腔室包括但不限于:周期性层沉积(cyclical layer deposition,CLD)、原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)、蚀刻、预清洁、化学清洁、热处理(如RTP)、等离子体氮化、除气、定向、羟基化和其它基板工艺。通过在群集工具上的腔室中执行处理,可避免大气杂质对基板的表面污染,而无需在沉积后续膜之前的氧化。
根据一个或多个实施方式,基板持续处于真空或“装载锁定(load lock)”条件下,并且当从一个腔室移动到下一个腔室时,不暴露于周围空气。因此传送腔室处在真空下并且于真空压力下被“降压(pump down)”。惰性气体可存在于处理腔室或传送腔室中。在某些实施方式中,惰性气体可用作净化气体,以移除某些或全部的反应物。根据一个或多个实施方式,可于沉积腔室的出口处注入净化气体,以避免反应物从沉积腔室移动至传送腔室和/或额外的处理腔室。因此,惰性气体的流动可于腔室的出口处形成帘幕。
可在单一基板沉积腔室中处理基板,其中在处理另一个基板之前,装载、处理并卸载单一基板。也可类似于传送带系统,以连续方式处理基板,其中将多个基板独立地载入腔室的第一部分,移动经过腔室并从腔室的第二部分卸载。腔室与相关传送带系统的形状可形成直线路径或弯曲路径。此外,处理腔室可为旋转式传送带(carousel),其中多个基板绕着中心轴移动并贯穿旋转式传送带路径而暴露于沉积、蚀刻、退火、清洁等工艺。
在处理期间,基板可被加热或冷却。可通过任何合适的方式完成加热或冷却,合适的方式包括但不限于改变基板支撑件的温度和使加热或冷却的气体流动到基板表面。在某些实施方式中,基板支撑件包括加热器/冷却器,可控制加热器/冷却器以传导地改变基板温度。在一个或多个实施方式中,所采用的气体(反应气体或惰性气体)被加热或冷却,以局部地改变基板温度。在某些实施方式中,将加热器/冷却器定位在腔室内,邻近于基板表面,以对流地改变基板温度。
在处理期间,也可使基板固定或旋转。旋转的基板可连续地旋转或以不连续的(discrete)步骤旋转。举例而言,可在整个工艺期间旋转基板,或可在暴露于不同的反应气体或净化气体之间少量地旋转基板。在处理期间(连续地或步进地)旋转基板可有助于通过使例如气流几何形状中局部变化的影响最小化,来产生更均匀的沉积或蚀刻。
本说明书通篇涉及的“一个实施方式(one embodiment)”、“某实施方式(certainembodiments)”、“一个或多个实施方式(one or more embodiments)”或“一实施方式(anembodiment)”意味着与所述实施方式有关的特定特征、结构、材料或性质包括在本公开内容的至少一个实施方式中。因此,本说明书通篇各处出现的短语,诸如“在一个或多个实施方式中”、“在某实施方式中”、“在一个实施方式中”或“在一实施方式中”不必指本公开内容的相同实施方式。再者,可在一个或多个实施方式中,以任何合适的方式组合特定特征、结构、材料或性质。
虽然本文已经参照特定实施方式来描述本公开内容,但可理解到这些实施方式仅为本公开内容的原理与应用的说明。对本领域技术人员而言显而易见的是,可对本公开内容的方法与设备进行各种修改与变化,而不背离本公开内容的精神与范围。因此,本公开内容欲包括在随附权利要求和它们的等效物的范围内的修改与变化。
Claims (15)
1.一种处理方法,包含下列步骤:
提供基板表面,所述基板表面具有至少一个沟槽,所述至少一个沟槽从所述基板表面到底部表面延伸某一深度,所述至少一个沟槽具有由第一侧壁和第二侧壁限定的宽度;
选择性地沉积膜材料,以形成初始膜,所述初始膜具有在所述沟槽中而不在所述基板表面上的膜材料体积,所述膜材料具有大于2的Pilling-Bedworth比值,并且包含选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U、W和V组成的群组的材料;和
处理所述初始膜,以使所述膜材料体积膨胀,以提供膨胀膜,所述膨胀膜延伸超过所述基板表面。
2.如权利要求1所述的方法,其中所述膜材料选自由Co、Fe、Mn、Nb、Os、Ta、U和V组成的群组。
3.如权利要求2所述的方法,其中处理所述初始膜包含下列步骤:将所述初始膜暴露于氧化环境。
4.如权利要求3所述的方法,其中所述膨胀膜包含选自由CoO、Fe2O3、Fe3O4、MnO2、Mn2O3、Mn3O4、MoO3、Nb2O5、Ta2O5、OsO2、UO2和V2O5组成的群组的材料。
5.如权利要求1所述的方法,其中所述膜材料具有大于2.5的Pilling-Bedworth比值,并且选自由Mo、Os和V组成的群组。
6.如权利要求4所述的方法,其中处理所述初始膜包含下列步骤:将所述初始膜暴露于氧化环境。
7.如权利要求5所述的方法,其中所述膨胀膜包含选自由MoO3、OsO2和V2O5组成的群组的材料。
8.如权利要求1所述的方法,其中处理所述初始膜包含下列步骤:将所述初始膜暴露于氮化环境。
9.如权利要求8所述的方法,其中所述膜材料选自由Cr、Mo和Os组成的群组。
10.如权利要求8所述的方法,其中所述膨胀膜包含选自由CrN2、MoN2和OsN2组成的群组的材料。
11.如权利要求1所述的方法,其中处理所述初始膜包含下列步骤:将所述初始膜暴露于氧化剂和/或氮化剂,所述氧化剂包含O2、O3、N2O、H2O、H2O2、CO、CO2、NH3、N2/Ar、N2/He或N2/Ar/He中的一种或多种,所述氮化剂包含氨、肼(hydrazine)、NO2或氮等离子体中的一种或多种。
12.如权利要求1所述的方法,其中处理所述初始膜发生在高于约300℃的温度下。
13.一种处理方法,包含下列步骤:
提供基板表面,所述基板表面具有至少一个沟槽,所述至少一个沟槽从所述基板表面到底部表面延伸某一深度,所述至少一个沟槽具有由第一侧壁和第二侧壁限定的宽度;
选择性地沉积膜材料,以形成初始膜,所述初始膜具有在所述沟槽中而不在所述基板表面上的膜材料体积,所述膜材料具有大于2的Pilling-Bedworth比值,并且包含选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U、W和V组成的群组的材料;和
处理所述初始膜,以形成金属的氮化物,以使所述膜材料体积膨胀,以提供膨胀膜,所述膨胀膜延伸超过所述基板表面,所述金属选自由Co、Cr、Fe、Mn、Nb、Os、Ta、U、W或V组成的群组。
14.如权利要求13所述的方法,其中所述膜材料包含选自由Cr、Mo和Os组成的群组的金属。
15.如权利要求13所述的方法,其中所述膨胀膜包含选自由CrN2、MoN2和OsN2组成的群组的材料。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662416992P | 2016-11-03 | 2016-11-03 | |
US62/416,992 | 2016-11-03 | ||
PCT/US2017/059737 WO2018085554A2 (en) | 2016-11-03 | 2017-11-02 | Deposition and treatment of films for patterning |
Publications (1)
Publication Number | Publication Date |
---|---|
CN109923661A true CN109923661A (zh) | 2019-06-21 |
Family
ID=62076683
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780067193.4A Pending CN109923661A (zh) | 2016-11-03 | 2017-11-02 | 用于图案化的膜的沉积与处理 |
Country Status (7)
Country | Link |
---|---|
US (2) | US10319636B2 (zh) |
EP (1) | EP3535782A4 (zh) |
JP (1) | JP2019534384A (zh) |
KR (1) | KR102317050B1 (zh) |
CN (1) | CN109923661A (zh) |
TW (1) | TWI719262B (zh) |
WO (1) | WO2018085554A2 (zh) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI680535B (zh) | 2016-06-14 | 2019-12-21 | 美商應用材料股份有限公司 | 金屬及含金屬化合物之氧化體積膨脹 |
TWI719262B (zh) | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | 用於圖案化之薄膜的沉積與處理 |
JP2020501344A (ja) | 2016-11-08 | 2020-01-16 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | パターニング用途のためのボトムアップ柱状体の形状制御 |
US10770349B2 (en) * | 2017-02-22 | 2020-09-08 | Applied Materials, Inc. | Critical dimension control for self-aligned contact patterning |
US10636659B2 (en) | 2017-04-25 | 2020-04-28 | Applied Materials, Inc. | Selective deposition for simplified process flow of pillar formation |
US10840186B2 (en) | 2017-06-10 | 2020-11-17 | Applied Materials, Inc. | Methods of forming self-aligned vias and air gaps |
TW201906035A (zh) | 2017-06-24 | 2019-02-01 | 美商微材料有限責任公司 | 生產完全自我對準的介層窗及觸點之方法 |
US10573555B2 (en) | 2017-08-31 | 2020-02-25 | Micromaterials Llc | Methods of producing self-aligned grown via |
US10510602B2 (en) | 2017-08-31 | 2019-12-17 | Mirocmaterials LLC | Methods of producing self-aligned vias |
WO2019050714A1 (en) | 2017-09-05 | 2019-03-14 | Applied Materials, Inc. | ASCENDING APPROACH FOR HIGH-FORM SHAPE FORMATION IN 3D MEMORY STRUCTURES |
TWI778118B (zh) * | 2017-09-05 | 2022-09-21 | 美商應用材料股份有限公司 | 來自次氧化物的自對準結構 |
US10600688B2 (en) | 2017-09-06 | 2020-03-24 | Micromaterials Llc | Methods of producing self-aligned vias |
JP2019106538A (ja) | 2017-12-07 | 2019-06-27 | マイクロマテリアルズ エルエルシー | 制御可能な金属およびバリアライナー凹部のための方法 |
EP3499557A1 (en) | 2017-12-15 | 2019-06-19 | Micromaterials LLC | Selectively etched self-aligned via processes |
KR20190104902A (ko) | 2018-03-02 | 2019-09-11 | 마이크로머티어리얼즈 엘엘씨 | 금속 산화물들을 제거하기 위한 방법들 |
TW201946113A (zh) * | 2018-04-27 | 2019-12-01 | 日商東京威力科創股份有限公司 | 用於先進接觸件中之覆蓋層形成的區域選擇性沉積 |
US10790191B2 (en) | 2018-05-08 | 2020-09-29 | Micromaterials Llc | Selective removal process to create high aspect ratio fully self-aligned via |
TW202011547A (zh) | 2018-05-16 | 2020-03-16 | 美商微材料有限責任公司 | 用於產生完全自對準的通孔的方法 |
WO2019236350A1 (en) | 2018-06-08 | 2019-12-12 | Micromaterials Llc | A method for creating a fully self-aligned via |
WO2020024221A1 (zh) * | 2018-08-02 | 2020-02-06 | 深圳市为通博科技有限责任公司 | 忆阻器电极材料的制备方法、制备装置和忆阻器电极材料 |
US10950460B2 (en) | 2018-08-08 | 2021-03-16 | Tokyo Electron Limited | Method utilizing using post etch pattern encapsulation |
US11164938B2 (en) | 2019-03-26 | 2021-11-02 | Micromaterials Llc | DRAM capacitor module |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60158643A (ja) * | 1984-01-27 | 1985-08-20 | Hitachi Ltd | 絶縁分離方法 |
JPS62142780A (ja) * | 1985-12-18 | 1987-06-26 | Canon Inc | 堆積膜形成法 |
KR20000012027A (ko) * | 1998-07-28 | 2000-02-25 | 가네꼬 히사시 | 반도체장치의제조방법 |
CA2365840A1 (en) * | 1999-03-05 | 2000-09-08 | Ramamoorthy Ramesh | Amorphous barrier layer in a ferroelectric memory cell |
JP2001167432A (ja) * | 1999-12-08 | 2001-06-22 | Hitachi Ltd | 高密度磁気記録媒体およびその作製方法 |
US6281114B1 (en) * | 2000-02-07 | 2001-08-28 | Infineon Technologies Ag | Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication |
US20080242097A1 (en) * | 2007-03-28 | 2008-10-02 | Tim Boescke | Selective deposition method |
US20100078617A1 (en) * | 2008-10-01 | 2010-04-01 | Breitwisch Matthew J | Method to reduce a via area in a phase change memory cell |
JP2011109099A (ja) * | 2009-11-17 | 2011-06-02 | Samsung Electronics Co Ltd | 導電構造物を含む半導体装置及びその製造方法 |
WO2015152228A1 (ja) * | 2014-03-31 | 2015-10-08 | ウシオ電機株式会社 | 半導体発光素子、半導体発光素子の製造方法、led素子、電子線励起型光源装置 |
JP2016004932A (ja) * | 2014-06-18 | 2016-01-12 | セイコーエプソン株式会社 | 圧電素子、液体噴射ヘッド、液体噴射装置及び圧電素子の製造方法 |
US20160284626A1 (en) * | 2015-03-25 | 2016-09-29 | Micron Technology, Inc. | Semiconductor devices having conductive vias and methods of forming the same |
Family Cites Families (105)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4671970A (en) | 1986-02-05 | 1987-06-09 | Ncr Corporation | Trench filling and planarization process |
JPH04349629A (ja) * | 1991-05-28 | 1992-12-04 | Hitachi Ltd | 半導体装置及びその製造方法 |
KR0165813B1 (ko) | 1995-04-12 | 1999-02-01 | 문정환 | 접속홀의 플러그 형성 방법 |
US5872052A (en) * | 1996-02-12 | 1999-02-16 | Micron Technology, Inc. | Planarization using plasma oxidized amorphous silicon |
KR100223334B1 (ko) | 1996-06-29 | 1999-10-15 | 김영환 | 반도체소자의 금속배선형성방법 |
US6143653A (en) | 1998-10-04 | 2000-11-07 | Promos Technologies, Inc. | Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss |
KR20000026588A (ko) | 1998-10-21 | 2000-05-15 | 윤종용 | 콘택홀을 갖는 반도체 장치 및 그 제조방법 |
US6130151A (en) | 1999-05-07 | 2000-10-10 | Taiwan Semiconductor Manufacturing Company | Method of manufacturing air gap in multilevel interconnection |
JP2001015479A (ja) | 1999-06-29 | 2001-01-19 | Toshiba Corp | 半導体装置の製造方法 |
KR20020020969A (ko) | 1999-08-18 | 2002-03-16 | 추후제출 | 반도체 웨이퍼 상에 구리 피처를 제조하는 방법 |
US6576113B1 (en) | 1999-10-29 | 2003-06-10 | California Institute Of Technology | Method of electroplating of high aspect ratio metal structures into semiconductors |
US6373087B1 (en) | 2000-08-31 | 2002-04-16 | Agere Systems Guardian Corp. | Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses |
US7192803B1 (en) | 2000-10-13 | 2007-03-20 | Bridge Semiconductor Corporation | Method of making a semiconductor chip assembly with simultaneously formed interconnect and connection joint |
US6653200B2 (en) | 2001-01-26 | 2003-11-25 | Applied Materials, Inc. | Trench fill process for reducing stress in shallow trench isolation |
JP2002252281A (ja) | 2001-02-27 | 2002-09-06 | Sony Corp | 半導体装置およびその製造方法 |
US6528884B1 (en) | 2001-06-01 | 2003-03-04 | Advanced Micro Devices, Inc. | Conformal atomic liner layer in an integrated circuit interconnect |
US7279119B2 (en) | 2001-06-14 | 2007-10-09 | Ppg Industries Ohio, Inc. | Silica and silica-based slurry |
EP1490529A1 (en) | 2002-03-28 | 2004-12-29 | President And Fellows Of Harvard College | Vapor deposition of silicon dioxide nanolaminates |
US7045073B2 (en) * | 2002-12-18 | 2006-05-16 | Intel Corporation | Pre-etch implantation damage for the removal of thin film layers |
US8298933B2 (en) | 2003-04-11 | 2012-10-30 | Novellus Systems, Inc. | Conformal films on semiconductor substrates |
US7276787B2 (en) | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
US7211844B2 (en) | 2004-01-29 | 2007-05-01 | International Business Machines Corporation | Vertical field effect transistors incorporating semiconducting nanotubes grown in a spacer-defined passage |
US7645677B2 (en) | 2004-03-16 | 2010-01-12 | Ishikawajima-Harima Heavy Industries Co., Ltd. | Method for manufacturing semiconductor device |
US7521378B2 (en) | 2004-07-01 | 2009-04-21 | Micron Technology, Inc. | Low temperature process for polysilazane oxidation/densification |
US7820020B2 (en) | 2005-02-03 | 2010-10-26 | Applied Materials, Inc. | Apparatus for plasma-enhanced physical vapor deposition of copper with RF source power applied through the workpiece with a lighter-than-copper carrier gas |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
JP4679437B2 (ja) * | 2005-06-02 | 2011-04-27 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP2007005381A (ja) | 2005-06-21 | 2007-01-11 | Matsushita Electric Ind Co Ltd | プラズマエッチング方法、及びプラズマエッチング装置 |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7351648B2 (en) | 2006-01-19 | 2008-04-01 | International Business Machines Corporation | Methods for forming uniform lithographic features |
US7368394B2 (en) | 2006-02-27 | 2008-05-06 | Applied Materials, Inc. | Etch methods to form anisotropic features for high aspect ratio applications |
US7288463B1 (en) | 2006-04-28 | 2007-10-30 | Novellus Systems, Inc. | Pulsed deposition layer gap fill with expansion material |
US7956465B2 (en) | 2006-05-08 | 2011-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing resistivity in interconnect structures of integrated circuits |
JP2008108757A (ja) | 2006-10-23 | 2008-05-08 | Matsushita Electric Works Ltd | 化合物半導体発光素子およびそれを用いる照明装置ならびに化合物半導体素子の製造方法 |
US7598170B2 (en) | 2007-01-26 | 2009-10-06 | Asm America, Inc. | Plasma-enhanced ALD of tantalum nitride films |
US20090017631A1 (en) | 2007-06-01 | 2009-01-15 | Bencher Christopher D | Self-aligned pillar patterning using multiple spacer masks |
WO2008153674A1 (en) | 2007-06-09 | 2008-12-18 | Boris Kobrin | Method and apparatus for anisotropic etching |
US20090072409A1 (en) | 2007-09-14 | 2009-03-19 | International Business Machines Corporation | Interconnect Structures Incorporating Air-Gap Spacers |
US7541297B2 (en) | 2007-10-22 | 2009-06-02 | Applied Materials, Inc. | Method and system for improving dielectric film quality for void free gap fill |
US20100330805A1 (en) | 2007-11-02 | 2010-12-30 | Kenny Linh Doan | Methods for forming high aspect ratio features on a substrate |
US7985977B2 (en) | 2007-12-11 | 2011-07-26 | Hvvi Semiconductors, Inc. | Sacrificial pillar dielectric platform |
MX2010008874A (es) * | 2008-02-14 | 2010-09-22 | Bristol Myers Squibb Co | Terapeuticos dirigidos a base de proteinas manipuladas que se unen al receptor de factor de crecimiento epidermico. |
KR101477661B1 (ko) | 2008-07-17 | 2014-12-31 | 삼성전자주식회사 | 텅스텐 재성장을 통한 심 없는 텅스텐 패턴 및 그 패턴형성 방법 |
US8169031B2 (en) | 2008-08-26 | 2012-05-01 | International Business Machines Corporation | Continuous metal semiconductor alloy via for interconnects |
KR101026486B1 (ko) | 2008-10-22 | 2011-04-01 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조방법 |
JP5133852B2 (ja) | 2008-11-13 | 2013-01-30 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法及び半導体装置 |
KR101534678B1 (ko) | 2009-02-12 | 2015-07-08 | 삼성전자주식회사 | 텅스텐 콘택 플러그를 산소 분위기에서 rta 처리하고, rto 처리된 텅스텐 플러그를 수소 분위기에서 환원시키는 반도체 소자의 제조방법 |
US8435830B2 (en) | 2009-03-18 | 2013-05-07 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices |
US8575753B2 (en) | 2009-05-27 | 2013-11-05 | Samsung Electronics Co., Ltd. | Semiconductor device having a conductive structure including oxide and non oxide portions |
JP2011060803A (ja) | 2009-09-07 | 2011-03-24 | Toshiba Corp | 半導体装置 |
US8531033B2 (en) | 2009-09-07 | 2013-09-10 | Advanced Interconnect Materials, Llc | Contact plug structure, semiconductor device, and method for forming contact plug |
US8274065B2 (en) | 2009-10-19 | 2012-09-25 | Macronix International Co., Ltd. | Memory and method of fabricating the same |
US8778749B2 (en) | 2011-01-12 | 2014-07-15 | Sandisk Technologies Inc. | Air isolation in high density non-volatile memory |
US8900988B2 (en) | 2011-04-15 | 2014-12-02 | International Business Machines Corporation | Method for forming self-aligned airgap interconnect structures |
JP2011233922A (ja) | 2011-07-20 | 2011-11-17 | Ihi Corp | 素子間分離領域の形成方法 |
US8946082B2 (en) | 2011-09-16 | 2015-02-03 | GlobalFoundries, Inc. | Methods for forming semiconductor devices |
DE112011105681B4 (de) * | 2011-09-28 | 2015-10-15 | Toyota Jidosha Kabushiki Kaisha | Verfahren zur Herstellung einer Halbleitervorrichtung |
KR20130046664A (ko) | 2011-10-28 | 2013-05-08 | 삼성전자주식회사 | 패턴 형성 방법 및 이를 이용한 반도체 소자의 제조 방법 |
CN113862634A (zh) | 2012-03-27 | 2021-12-31 | 诺发系统公司 | 钨特征填充 |
US8860001B2 (en) | 2012-04-09 | 2014-10-14 | Freescale Semiconductor, Inc. | ReRAM device structure |
US20140029181A1 (en) | 2012-07-27 | 2014-01-30 | Florian Gstrein | Interlayer interconnects and associated techniques and configurations |
US9245987B2 (en) | 2012-11-29 | 2016-01-26 | Micron Technology, Inc. | Semiconductor devices and fabrication methods |
US8901607B2 (en) | 2013-01-14 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabricating the same |
US9312220B2 (en) | 2013-03-12 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for a low-K dielectric with pillar-type air-gaps |
US9178011B2 (en) * | 2013-03-13 | 2015-11-03 | Intermolecular, Inc. | Deposition of anisotropic dielectric layers orientationally matched to the physically separated substrate |
US9012322B2 (en) | 2013-04-05 | 2015-04-21 | Intermolecular, Inc. | Selective etching of copper and copper-barrier materials by an aqueous base solution with fluoride addition |
US9040421B2 (en) | 2013-05-03 | 2015-05-26 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits with improved contact structures |
US9219007B2 (en) | 2013-06-10 | 2015-12-22 | International Business Machines Corporation | Double self aligned via patterning |
EP3796371A3 (en) | 2013-09-27 | 2021-10-06 | INTEL Corporation | Self-aligned via and plug patterning for back end of line (beol) interconnects |
EP3050086A4 (en) | 2013-09-27 | 2017-05-03 | Intel Corporation | Previous layer self-aligned via and plug patterning for back end of line (beol) interconnects |
US20150111374A1 (en) | 2013-10-18 | 2015-04-23 | International Business Machines Corporation | Surface treatment in a dep-etch-dep process |
US8951429B1 (en) | 2013-10-29 | 2015-02-10 | Applied Materials, Inc. | Tungsten oxide processing |
US9362413B2 (en) * | 2013-11-15 | 2016-06-07 | Cbrite Inc. | MOTFT with un-patterned etch-stop |
US9312168B2 (en) | 2013-12-16 | 2016-04-12 | Applied Materials, Inc. | Air gap structure integration using a processing system |
US9236292B2 (en) | 2013-12-18 | 2016-01-12 | Intel Corporation | Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) |
JP6297884B2 (ja) | 2014-03-28 | 2018-03-20 | 東京エレクトロン株式会社 | タングステン膜の成膜方法 |
KR102377372B1 (ko) | 2014-04-02 | 2022-03-21 | 어플라이드 머티어리얼스, 인코포레이티드 | 인터커넥트들을 형성하기 위한 방법 |
US9368395B1 (en) | 2014-05-06 | 2016-06-14 | Globalfoundries Inc. | Self-aligned via and air gap |
US9299745B2 (en) | 2014-05-08 | 2016-03-29 | GlobalFoundries, Inc. | Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same |
US9281382B2 (en) | 2014-06-04 | 2016-03-08 | Stmicroelectronics, Inc. | Method for making semiconductor device with isolation pillars between adjacent semiconductor fins |
US9627318B2 (en) | 2014-06-16 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company Ltd. | Interconnect structure with footing region |
US9679852B2 (en) | 2014-07-01 | 2017-06-13 | Micron Technology, Inc. | Semiconductor constructions |
US9324650B2 (en) | 2014-08-15 | 2016-04-26 | International Business Machines Corporation | Interconnect structures with fully aligned vias |
US9356047B2 (en) | 2014-08-18 | 2016-05-31 | Globalfoundries Inc. | Integrated circuits with self aligned contact structures for improved windows and fabrication methods |
US9508642B2 (en) | 2014-08-20 | 2016-11-29 | Globalfoundries Inc. | Self-aligned back end of line cut |
US9349637B2 (en) | 2014-08-21 | 2016-05-24 | Lam Research Corporation | Method for void-free cobalt gap fill |
US9735030B2 (en) * | 2014-09-05 | 2017-08-15 | Fujifilm Planar Solutions, LLC | Polishing compositions and methods for polishing cobalt films |
US9515085B2 (en) | 2014-09-26 | 2016-12-06 | Sandisk Technologies Llc | Vertical memory device with bit line air gap |
US20160111342A1 (en) | 2014-10-17 | 2016-04-21 | Lam Research Corporation | Method and apparatus for characterizing metal oxide reduction |
US10727122B2 (en) | 2014-12-08 | 2020-07-28 | International Business Machines Corporation | Self-aligned via interconnect structures |
CN107112212B (zh) | 2014-12-22 | 2021-03-12 | 东京毅力科创株式会社 | 使用接枝聚合物材料图案化基底 |
US20160260779A1 (en) * | 2015-03-06 | 2016-09-08 | Kabushiki Kaisha Toshiba | Non-volatile resistive random access memory device |
US9362165B1 (en) | 2015-05-08 | 2016-06-07 | Globalfoundries Inc. | 2D self-aligned via first process flow |
KR20180018510A (ko) * | 2015-06-18 | 2018-02-21 | 인텔 코포레이션 | 반도체 구조체들을 위한 금속 피처들의 BUF(Bottom-Up Fill) |
US9543148B1 (en) | 2015-09-01 | 2017-01-10 | Lam Research Corporation | Mask shrink layer for high aspect ratio dielectric etch |
US9716065B2 (en) | 2015-09-14 | 2017-07-25 | International Business Machines Corporation | Via bottom structure and methods of forming |
US9721888B2 (en) | 2015-12-08 | 2017-08-01 | International Business Machines Corporation | Trench silicide with self-aligned contact vias |
US10163704B2 (en) | 2015-12-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
WO2017136577A1 (en) | 2016-02-02 | 2017-08-10 | Tokyo Electron Limited | Self-alignment of metal and via using selective deposition |
US11127629B2 (en) * | 2016-05-17 | 2021-09-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and fabricating method thereof |
TWI680535B (zh) * | 2016-06-14 | 2019-12-21 | 美商應用材料股份有限公司 | 金屬及含金屬化合物之氧化體積膨脹 |
EP3520136A4 (en) | 2016-09-30 | 2020-05-06 | Applied Materials, Inc. | METHODS OF FORMING SELF-ALIGNED INTERCONNECT HOLES |
TWI719262B (zh) | 2016-11-03 | 2021-02-21 | 美商應用材料股份有限公司 | 用於圖案化之薄膜的沉積與處理 |
TW201833991A (zh) | 2016-11-08 | 2018-09-16 | 美商應用材料股份有限公司 | 自對準圖案化之方法 |
WO2018227110A1 (en) | 2017-06-10 | 2018-12-13 | Applied Materials, Inc. | Methods of forming self-aligned vias and air gaps |
-
2017
- 2017-10-27 TW TW106137034A patent/TWI719262B/zh not_active IP Right Cessation
- 2017-11-02 WO PCT/US2017/059737 patent/WO2018085554A2/en unknown
- 2017-11-02 US US15/801,949 patent/US10319636B2/en active Active
- 2017-11-02 KR KR1020197015909A patent/KR102317050B1/ko active IP Right Grant
- 2017-11-02 JP JP2019523723A patent/JP2019534384A/ja not_active Ceased
- 2017-11-02 EP EP17867127.7A patent/EP3535782A4/en not_active Withdrawn
- 2017-11-02 CN CN201780067193.4A patent/CN109923661A/zh active Pending
-
2019
- 2019-04-25 US US16/394,731 patent/US10699952B2/en active Active
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60158643A (ja) * | 1984-01-27 | 1985-08-20 | Hitachi Ltd | 絶縁分離方法 |
JPS62142780A (ja) * | 1985-12-18 | 1987-06-26 | Canon Inc | 堆積膜形成法 |
KR20000012027A (ko) * | 1998-07-28 | 2000-02-25 | 가네꼬 히사시 | 반도체장치의제조방법 |
CA2365840A1 (en) * | 1999-03-05 | 2000-09-08 | Ramamoorthy Ramesh | Amorphous barrier layer in a ferroelectric memory cell |
JP2001167432A (ja) * | 1999-12-08 | 2001-06-22 | Hitachi Ltd | 高密度磁気記録媒体およびその作製方法 |
US6281114B1 (en) * | 2000-02-07 | 2001-08-28 | Infineon Technologies Ag | Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication |
US20080242097A1 (en) * | 2007-03-28 | 2008-10-02 | Tim Boescke | Selective deposition method |
US20100078617A1 (en) * | 2008-10-01 | 2010-04-01 | Breitwisch Matthew J | Method to reduce a via area in a phase change memory cell |
JP2011109099A (ja) * | 2009-11-17 | 2011-06-02 | Samsung Electronics Co Ltd | 導電構造物を含む半導体装置及びその製造方法 |
WO2015152228A1 (ja) * | 2014-03-31 | 2015-10-08 | ウシオ電機株式会社 | 半導体発光素子、半導体発光素子の製造方法、led素子、電子線励起型光源装置 |
JP2016004932A (ja) * | 2014-06-18 | 2016-01-12 | セイコーエプソン株式会社 | 圧電素子、液体噴射ヘッド、液体噴射装置及び圧電素子の製造方法 |
US20160284626A1 (en) * | 2015-03-25 | 2016-09-29 | Micron Technology, Inc. | Semiconductor devices having conductive vias and methods of forming the same |
Also Published As
Publication number | Publication date |
---|---|
EP3535782A4 (en) | 2020-10-28 |
US10699952B2 (en) | 2020-06-30 |
KR102317050B1 (ko) | 2021-10-26 |
JP2019534384A (ja) | 2019-11-28 |
EP3535782A2 (en) | 2019-09-11 |
TW201829822A (zh) | 2018-08-16 |
US20180144980A1 (en) | 2018-05-24 |
US20190252252A1 (en) | 2019-08-15 |
WO2018085554A3 (en) | 2018-06-21 |
WO2018085554A2 (en) | 2018-05-11 |
US10319636B2 (en) | 2019-06-11 |
TWI719262B (zh) | 2021-02-21 |
KR20190067933A (ko) | 2019-06-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN109923661A (zh) | 用于图案化的膜的沉积与处理 | |
TWI680535B (zh) | 金屬及含金屬化合物之氧化體積膨脹 | |
TWI687978B (zh) | 用於圖案化應用之由下而上的柱體之幾何控制 | |
TW201824453A (zh) | 形成自對準介層窗之方法 | |
KR102474184B1 (ko) | 서브-옥사이드들로부터의 자기-정렬 구조들 | |
JP7305622B2 (ja) | シリサイド化による金属含有膜の体積膨張 | |
TWI760481B (zh) | 用於氧化鎢柱形成之簡化製程流程的鎢選擇性沉積 | |
TWI780922B (zh) | 形成鎢支柱的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190621 |