EP3520136A4 - Methods of forming self-aligned vias - Google Patents

Methods of forming self-aligned vias Download PDF

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Publication number
EP3520136A4
EP3520136A4 EP17857400.0A EP17857400A EP3520136A4 EP 3520136 A4 EP3520136 A4 EP 3520136A4 EP 17857400 A EP17857400 A EP 17857400A EP 3520136 A4 EP3520136 A4 EP 3520136A4
Authority
EP
European Patent Office
Prior art keywords
methods
forming self
aligned vias
vias
aligned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP17857400.0A
Other languages
German (de)
French (fr)
Other versions
EP3520136A1 (en
Inventor
David Thompson
Benjamin Schmiege
Jeffrey W. Anthis
Abhijit Basu Mallick
Susmit Singha ROY
Ziqing Duan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of EP3520136A1 publication Critical patent/EP3520136A1/en
Publication of EP3520136A4 publication Critical patent/EP3520136A4/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
EP17857400.0A 2016-09-30 2017-09-28 Methods of forming self-aligned vias Withdrawn EP3520136A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662403036P 2016-09-30 2016-09-30
PCT/US2017/053936 WO2018064292A1 (en) 2016-09-30 2017-09-28 Methods of forming self-aligned vias

Publications (2)

Publication Number Publication Date
EP3520136A1 EP3520136A1 (en) 2019-08-07
EP3520136A4 true EP3520136A4 (en) 2020-05-06

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Family Applications (1)

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EP17857400.0A Withdrawn EP3520136A4 (en) 2016-09-30 2017-09-28 Methods of forming self-aligned vias

Country Status (7)

Country Link
US (3) US10083834B2 (en)
EP (1) EP3520136A4 (en)
JP (1) JP2019530242A (en)
KR (1) KR20190047139A (en)
CN (1) CN109791913A (en)
TW (1) TW201824453A (en)
WO (1) WO2018064292A1 (en)

Families Citing this family (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI680535B (en) 2016-06-14 2019-12-21 美商應用材料股份有限公司 Oxidative volumetric expansion of metals and metal containing compounds
TWI719262B (en) 2016-11-03 2021-02-21 美商應用材料股份有限公司 Deposition and treatment of films for patterning
CN109923662A (en) 2016-11-08 2019-06-21 应用材料公司 For patterning the geometry control of the bottom-up column of application
TW201833991A (en) * 2016-11-08 2018-09-16 美商應用材料股份有限公司 Methods for self-aligned patterning
US10770349B2 (en) * 2017-02-22 2020-09-08 Applied Materials, Inc. Critical dimension control for self-aligned contact patterning
US10224224B2 (en) 2017-03-10 2019-03-05 Micromaterials, LLC High pressure wafer processing systems and related methods
US10424507B2 (en) 2017-04-04 2019-09-24 Mirocmaterials LLC Fully self-aligned via
WO2018200212A1 (en) 2017-04-25 2018-11-01 Applied Materials, Inc. Selective deposition of tungsten for simplified process flow of tungsten oxide pillar formation
US10847360B2 (en) 2017-05-25 2020-11-24 Applied Materials, Inc. High pressure treatment of silicon nitride film
US10622214B2 (en) 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US10950498B2 (en) 2017-05-31 2021-03-16 Applied Materials, Inc. Selective and self-limiting tungsten etch process
JP7190450B2 (en) 2017-06-02 2022-12-15 アプライド マテリアルズ インコーポレイテッド Dry stripping of boron carbide hardmask
US10840186B2 (en) 2017-06-10 2020-11-17 Applied Materials, Inc. Methods of forming self-aligned vias and air gaps
TW201906035A (en) * 2017-06-24 2019-02-01 美商微材料有限責任公司 Method of producing fully self-aligned vias and contacts
TWI760540B (en) 2017-08-13 2022-04-11 美商應用材料股份有限公司 Self-aligned high aspect ratio structures and methods of making
JP6947914B2 (en) 2017-08-18 2021-10-13 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ Annealing chamber under high pressure and high temperature
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
WO2019046402A1 (en) 2017-08-31 2019-03-07 Micromaterials Llc Methods of producing self-aligned grown via
WO2019046399A1 (en) 2017-08-31 2019-03-07 Micromaterials Llc Methods of producing self-aligned vias
TWI778118B (en) * 2017-09-05 2022-09-21 美商應用材料股份有限公司 Self-aligned structures from sub-oxides
CN111133579B (en) 2017-09-05 2023-09-01 应用材料公司 Bottom-up High Aspect Ratio Hole Formation in 3D Memory Structures
WO2019050735A1 (en) 2017-09-06 2019-03-14 Micromaterials Llc Methods of producing self-aligned vias
CN111095524B (en) 2017-09-12 2023-10-03 应用材料公司 Apparatus and method for fabricating semiconductor structures using protective barrier layers
US10643867B2 (en) 2017-11-03 2020-05-05 Applied Materials, Inc. Annealing system and method
JP7112490B2 (en) 2017-11-11 2022-08-03 マイクロマテリアルズ エルエルシー Gas supply system for high pressure processing chambers
KR102622303B1 (en) 2017-11-16 2024-01-05 어플라이드 머티어리얼스, 인코포레이티드 High pressure steam annealing processing equipment
JP2021503714A (en) 2017-11-17 2021-02-12 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ Capacitor system for high pressure processing system
JP2019106538A (en) 2017-12-07 2019-06-27 マイクロマテリアルズ エルエルシー Methods for controllable metal and barrier-liner recess
EP3499557A1 (en) 2017-12-15 2019-06-19 Micromaterials LLC Selectively etched self-aligned via processes
TW202321493A (en) * 2017-12-20 2023-06-01 美商應用材料股份有限公司 High pressure oxidation of metal films
KR102649241B1 (en) 2018-01-24 2024-03-18 어플라이드 머티어리얼스, 인코포레이티드 Seam healing using high pressure annealing
KR20190104902A (en) 2018-03-02 2019-09-11 마이크로머티어리얼즈 엘엘씨 Methods for removing metal oxides
EP3762962A4 (en) 2018-03-09 2021-12-08 Applied Materials, Inc. High pressure annealing process for metal containing materials
US10714331B2 (en) 2018-04-04 2020-07-14 Applied Materials, Inc. Method to fabricate thermally stable low K-FinFET spacer
US11170992B2 (en) * 2018-04-27 2021-11-09 Tokyo Electron Limited Area selective deposition for cap layer formation in advanced contacts
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
TW202002219A (en) 2018-05-08 2020-01-01 美商微材料有限責任公司 Selective removal process to create high aspect ratio fully self-aligned via
TW202011547A (en) 2018-05-16 2020-03-16 美商微材料有限責任公司 A method for creating a fully self-aligned via
US10566188B2 (en) 2018-05-17 2020-02-18 Applied Materials, Inc. Method to improve film stability
US10704141B2 (en) 2018-06-01 2020-07-07 Applied Materials, Inc. In-situ CVD and ALD coating of chamber to control metal contamination
WO2019236350A1 (en) 2018-06-08 2019-12-12 Micromaterials Llc A method for creating a fully self-aligned via
US10643846B2 (en) * 2018-06-28 2020-05-05 Lam Research Corporation Selective growth of metal-containing hardmask thin films
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
US10675581B2 (en) 2018-08-06 2020-06-09 Applied Materials, Inc. Gas abatement apparatus
WO2020033698A1 (en) 2018-08-10 2020-02-13 Applied Materials, Inc. Methods for selective deposition using self-assembled monolayers
US11387112B2 (en) * 2018-10-04 2022-07-12 Tokyo Electron Limited Surface processing method and processing system
WO2020092002A1 (en) 2018-10-30 2020-05-07 Applied Materials, Inc. Methods for etching a structure for semiconductor applications
KR20210077779A (en) 2018-11-16 2021-06-25 어플라이드 머티어리얼스, 인코포레이티드 Film Deposition Using Enhanced Diffusion Process
WO2020117462A1 (en) 2018-12-07 2020-06-11 Applied Materials, Inc. Semiconductor processing system
US11164938B2 (en) * 2019-03-26 2021-11-02 Micromaterials Llc DRAM capacitor module
US11404317B2 (en) * 2019-09-24 2022-08-02 International Business Machines Corporation Method for fabricating a semiconductor device including self-aligned top via formation at line ends
US11437274B2 (en) 2019-09-25 2022-09-06 Micromaterials Llc Fully self-aligned via
JP7362911B2 (en) * 2019-09-26 2023-10-17 アプライド マテリアルズ インコーポレイテッド Selective self-limiting tungsten etch process
US11069610B2 (en) 2019-10-15 2021-07-20 Micron Technology, Inc. Methods for forming microelectronic devices with self-aligned interconnects, and related devices and systems
US11901222B2 (en) 2020-02-17 2024-02-13 Applied Materials, Inc. Multi-step process for flowable gap-fill film
US11830729B2 (en) * 2021-01-08 2023-11-28 Applied Materials, Inc. Low-k boron carbonitride films

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068631A (en) * 1983-09-26 1985-04-19 Toshiba Corp Manufacture of semiconductor device
US20020163081A1 (en) * 2001-02-27 2002-11-07 Junichi Aoyama Semiconductor device and method of manufacturing the same
US20100301480A1 (en) * 2009-05-27 2010-12-02 Suk-Hun Choi Semiconductor device having a conductive structure
US20130307033A1 (en) * 2012-05-21 2013-11-21 International Business Machines Borderless Contact For An Aluminum-Containing Gate

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58143551A (en) * 1982-02-22 1983-08-26 Toshiba Corp Wiring method for semiconductor device
JPH0350726A (en) * 1989-07-19 1991-03-05 Nec Corp Structure of interlayer wiring connection part and its forming method
JPH09312336A (en) * 1996-05-20 1997-12-02 Yamaha Corp Connection hole formation method
JP2001093978A (en) * 1999-09-27 2001-04-06 Matsushita Electronics Industry Corp Semiconductor device and its manufacturing method
JP2002100533A (en) * 2000-07-19 2002-04-05 Sony Corp Method of forming capacitor element, method of forming composite thin film element, wiring board and module board
US6653200B2 (en) * 2001-01-26 2003-11-25 Applied Materials, Inc. Trench fill process for reducing stress in shallow trench isolation
CN100360710C (en) 2002-03-28 2008-01-09 哈佛学院院长等 Vapor deposition of silicon dioxide nanolaminates
WO2005088694A1 (en) 2004-03-16 2005-09-22 Ishikawajima-Harima Heavy Industries Co., Ltd. Process for fabricating semiconductor device
US8178386B2 (en) * 2007-09-14 2012-05-15 Macronix International Co., Ltd. Phase change memory cell array with self-converged bottom electrode and method for manufacturing
JP5775288B2 (en) * 2009-11-17 2015-09-09 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． Semiconductor device
KR101566925B1 (en) * 2010-01-29 2015-11-16 삼성전자주식회사 Method of fabricating semiconductor device
JP2011233922A (en) 2011-07-20 2011-11-17 Ihi Corp Method of forming inter-device isolating region
US8735262B2 (en) * 2011-10-24 2014-05-27 Infineon Technologies Ag Semiconductor device having a through contact and a manufacturing method therefor
US8901607B2 (en) 2013-01-14 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and fabricating the same
JP5576543B1 (en) * 2013-09-12 2014-08-20 太陽誘電株式会社 Circuit module
KR102377372B1 (en) 2014-04-02 2022-03-21 어플라이드 머티어리얼스, 인코포레이티드 Method for forming interconnects
US10727122B2 (en) * 2014-12-08 2020-07-28 International Business Machines Corporation Self-aligned via interconnect structures

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068631A (en) * 1983-09-26 1985-04-19 Toshiba Corp Manufacture of semiconductor device
US20020163081A1 (en) * 2001-02-27 2002-11-07 Junichi Aoyama Semiconductor device and method of manufacturing the same
US20100301480A1 (en) * 2009-05-27 2010-12-02 Suk-Hun Choi Semiconductor device having a conductive structure
US20130307033A1 (en) * 2012-05-21 2013-11-21 International Business Machines Borderless Contact For An Aluminum-Containing Gate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2018064292A1 *

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US20190013202A1 (en) 2019-01-10
US10083834B2 (en) 2018-09-25
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US10410865B2 (en) 2019-09-10
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