JP5775288B2 - semiconductor device - Google Patents

semiconductor device Download PDF

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JP5775288B2
JP5775288B2 JP2010256111A JP2010256111A JP5775288B2 JP 5775288 B2 JP5775288 B2 JP 5775288B2 JP 2010256111 A JP2010256111 A JP 2010256111A JP 2010256111 A JP2010256111 A JP 2010256111A JP 5775288 B2 JP5775288 B2 JP 5775288B2
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pattern
opening
insulating film
metal
film
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JP2011109099A (en
JP2011109099A5 (en
Inventor
錫 憲 崔
錫 憲 崔
キョン 顯 金
キョン 顯 金
泰 賢 金
泰 賢 金
キョン 兌 南
キョン 兌 南
起 浩 べ
起 浩 べ
義 官 洪
義 官 洪
峻 昊 鄭
峻 昊 鄭
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三星電子株式会社Samsung Electronics Co.,Ltd.
三星電子株式会社Samsung Electronics Co.,Ltd.
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Priority to KR1020090110694A priority Critical patent/KR101603161B1/en
Priority to KR10-2009-0110694 priority
Priority to US12/787,056 priority patent/US8575753B2/en
Priority to US12/787,056 priority
Application filed by 三星電子株式会社Samsung Electronics Co.,Ltd., 三星電子株式会社Samsung Electronics Co.,Ltd. filed Critical 三星電子株式会社Samsung Electronics Co.,Ltd.
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The present invention relates to a semiconductor device including a conductive structure, and more particularly, relates to a semiconductor equipment comprising a conductive structure in contact with the data storage device.

  Data can be recorded in or read from the resistive memory device by applying heat to a predetermined portion of the resistive memory device. In order to locally dissipate heat in a predetermined portion of the resistive memory device, the resistive memory device will include a conductive structure that functions as a heating electrode. Accordingly, a conductive structure that can heat the resistive memory device with high heating efficiency is required.

Korean Patent No. 0165813 specification US Pat. No. 6,117,720 Korean Patent Application Publication No. 2001-0028589 Specification JP 2004-214458 A US Patent Application Publication No. 2007-0155026 US Patent Application Publication No. 2002-0096775 Korean Patent No. 0869433 specification

  The present invention has been made in view of the above-described prior art, and an object of the present invention is to provide a semiconductor device including a conductive structure in which resistance can be easily adjusted and high integration is possible. It is in.

In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes an insulating film including an opening disposed on a substrate and exposing a conductive region of the substrate, and a barrier film disposed in the opening. A conductive pattern including a pattern, an oxidized portion disposed on the barrier film pattern and extending from the inside of the opening to the outside, and an unoxidized portion located in the opening, and The width of the conductive pattern is determined by the thickness of the barrier film pattern ,
The oxidized portion of the conductive pattern contacts one of a phase change material film of a phase change memory device (PRAM) and a free film pattern of a magnetic memory device (MRAM) .

  The width of the conductive pattern may be smaller than the width of the opening.

  The oxidized portion extending outside the opening may be thicker than the unoxidized portion in the opening.

  The width of the oxidized portion may be the same as the width of the non-oxidized portion.

  The width of the oxidized portion may be larger than the width of the non-oxidized portion.

  The semiconductor device may further include a filling film pattern disposed in the opening, and the conductive pattern may be disposed between the barrier film pattern and the filling film pattern.

  The conductive pattern may have a cylinder shape.

  The conductive pattern may include tungsten.

  The barrier film pattern may include at least one of titanium and titanium nitride.

  The barrier film pattern may include at least one of nitride and oxynitride.

  The barrier film pattern may contact a PN diode disposed under the barrier film pattern.

  The barrier film pattern may be in electrical contact with a MOS transistor disposed under the barrier film pattern.

  The size of the cross-sectional area of the oxidized portion on the plane may be smaller than the size of the cross-sectional area of the opening on the plane.

  The size of the cross-sectional area of the oxidized portion on a plane can be determined by the size of the cross-sectional area of the barrier film pattern.

  According to the present invention, a resistive memory device including a conductive structure that can ensure high heating efficiency can be easily manufactured through a simplified process. Therefore, the resistive memory device according to the present invention can be used in a memory device requiring high integration and high performance.

1 is a cross-sectional view of a conductive structure according to a first embodiment of the present invention. FIG. 2 is a perspective view of the conductive structure shown in FIG. 1. It is sectional drawing for demonstrating the formation method of the electrically-conductive structure shown in FIG. It is sectional drawing for demonstrating the formation method of the electrically-conductive structure shown in FIG. It is sectional drawing for demonstrating the formation method of the electrically-conductive structure shown in FIG. 1 is a cross-sectional view of a magnetic memory device according to a first embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining the method of manufacturing the magnetic memory device shown in FIG. 6. FIG. 7 is a cross-sectional view for explaining the method of manufacturing the magnetic memory device shown in FIG. 6. FIG. 7 is a cross-sectional view for explaining the method of manufacturing the magnetic memory device shown in FIG. 6. FIG. 7 is a cross-sectional view for explaining the method of manufacturing the magnetic memory device shown in FIG. 6. 1 is a cross-sectional view of a phase change memory device according to a first embodiment of the present invention. FIG. 12 is a cross-sectional view for explaining a method of manufacturing the phase change memory device shown in FIG. 11. FIG. 6 is a cross-sectional view of a phase change memory device according to a second embodiment of the present invention. FIG. 14 is a cross-sectional view for illustrating a method of manufacturing the phase change memory device shown in FIG. 13. FIG. 6 is a cross-sectional view of a phase change memory device according to a third embodiment of the present invention. It is sectional drawing of the electrically conductive structure by 2nd Embodiment of this invention. It is sectional drawing for demonstrating the formation method of the electrically conductive structure shown in FIG. It is sectional drawing of the electrically conductive structure by 3rd Embodiment of this invention. It is a perspective view of the electrically-conductive structure shown in FIG. It is a top view of the electrically conductive structure shown in FIG. It is sectional drawing for demonstrating the formation method of the electrically-conductive structure shown in FIG. It is sectional drawing for demonstrating the formation method of the electrically-conductive structure shown in FIG. 6 is a cross-sectional view of a magnetic memory device according to a second embodiment of the present invention. FIG. FIG. 24 is a cross-sectional view for illustrating the method of manufacturing the magnetic memory device shown in FIG. 23. FIG. 24 is a cross-sectional view for illustrating the method of manufacturing the magnetic memory device shown in FIG. 23. FIG. 6 is a cross-sectional view of a phase change memory device according to a fourth embodiment of the present invention. It is sectional drawing of the electrically conductive structure by 4th Embodiment of this invention. FIG. 7 is a cross-sectional view of a phase change memory device according to a fifth embodiment of the present invention. FIG. 29 is a cross-sectional view for illustrating a method of manufacturing the phase change memory device shown in FIG. 28. FIG. 29 is a cross-sectional view for explaining another method for manufacturing the phase change memory device shown in FIG. 28; FIG. 7 is a cross-sectional view of a phase change memory device according to a sixth embodiment of the present invention. It is sectional drawing of the electrically conductive structure by 5th Embodiment of this invention. It is sectional drawing for demonstrating the formation method of the electrically conductive structure shown in FIG. FIG. 6 is a cross-sectional view of a magnetic memory device according to a third embodiment of the present invention. 6 is a cross-sectional view of a magnetic memory device according to a fourth embodiment of the present invention. FIG. FIG. 9 is a cross-sectional view of a phase change memory device according to a seventh embodiment of the present invention. It is sectional drawing of the electrically conductive structure by 6th Embodiment of this invention. FIG. 10 is a cross-sectional view of a phase change memory device according to an eighth embodiment of the present invention. FIG. 39 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 38. FIG. 39 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 38. FIG. 39 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 38. FIG. 39 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 38. FIG. 39 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 38. FIG. 39 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 38. FIG. 20 is a cross-sectional view of a phase change memory device according to a ninth embodiment of the present invention. FIG. 46 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 45. FIG. 20 is a cross-sectional view of a phase change memory device according to a tenth embodiment of the present invention. FIG. 48 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 47. FIG. 48 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 47. FIG. 48 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 47. FIG. 48 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 47. FIG. 20 is a perspective view of a phase change memory device according to an eleventh embodiment of the present invention. FIG. 53 is a perspective view for illustrating a method for manufacturing the phase change memory device shown in FIG. 52. FIG. 53 is a perspective view for illustrating a method for manufacturing the phase change memory device shown in FIG. 52. FIG. 53 is a perspective view for illustrating a method for manufacturing the phase change memory device shown in FIG. 52. FIG. 53 is a perspective view for illustrating a method for manufacturing the phase change memory device shown in FIG. 52. FIG. 53 is a perspective view for illustrating a method for manufacturing the phase change memory device shown in FIG. 52. FIG. 53 is a perspective view for illustrating a method for manufacturing the phase change memory device shown in FIG. 52. 14 is a cross-sectional view of a phase change memory device according to a twelfth embodiment of the present invention; FIG. 60 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 59. FIG. 60 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 59. FIG. 60 is a cross-sectional view for illustrating the method for manufacturing the phase change memory device shown in FIG. 59. 1 is a schematic diagram of a communication system including a mobile phone network capable of broadband mobile communication according to an embodiment of the present invention. It is sectional drawing which shows the contact structure by the sample 1 thru | or the sample 8. It is sectional drawing which shows the contact structure by the comparative sample 11 thru | or the comparative sample 18. It is sectional drawing which shows the contact structure by the comparative sample 21 thru | or the comparative sample. It is a graph which shows the resistance of the contact structure by a sample and a comparative sample. 6 is a cross-sectional view showing a phase change memory device according to a comparative sample 9. FIG.

  Hereinafter, a specific example of a mode for carrying out a semiconductor device including a conductive structure of the present invention and a manufacturing method thereof will be described in detail with reference to the drawings. In the drawings of the present specification, the sizes of the components and / or structures are shown larger than the actual size for the sake of clarity of the present invention.

  In this specification, the terms first, second, etc. are used to describe various components, but the components are not limited by such terms, and the terms are different from one component. Used to distinguish from the components of

  The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular form includes the plural form unless the context clearly dictates otherwise. In this specification, terms such as “comprising” or “having” are intended to indicate that a feature, number, step, action, component, part, or combination of elements described in the specification is present. It does not pre-exclude the presence or the possibility of adding one or more other features or numbers, steps, actions, components, parts, or combinations thereof.

  In this specification, each floor (film), region, electrode, pattern, or structure is “above”, “upper”, or “lower” of the object, substrate, each floor (film), region, electrode, or pattern. Each floor (film), region, electrode, pattern, or structure is formed directly on the substrate, each floor (film), region, or pattern, or positioned below It means that other layers (films), other regions, other electrodes, other patterns, or other structures are additionally formed on the object or the substrate.

  For the embodiments of the invention disclosed herein, the specific structural or functional descriptions are merely exemplary for the purpose of illustrating the embodiments of the present invention. The forms can be implemented in various forms, and are not limited to the embodiments described herein. In other words, the present invention can be variously modified and can have various forms, and specific embodiments are illustrated in the drawings and described in detail in the present specification. This should not be construed as limiting the invention to the particular forms disclosed, but should be understood to include all modifications, equivalents or alternatives falling within the spirit and scope of the invention.

  FIG. 1 is a cross-sectional view of a conductive structure according to a first embodiment of the present invention, and FIG. 2 is a perspective view of the conductive structure shown in FIG.

  Referring to FIGS. 1 and 2, an insulating film 52 is provided on the substrate 50. The insulating film 52 includes an opening 54 that exposes a part of the substrate 50. For example, the opening 54 exposes the conductive region of the substrate 50. In the present embodiment, a conductive pattern can be provided on the substrate 50, and the opening 54 exposes the conductive pattern on the substrate 50.

  According to the present embodiment, the opening 54 has a contact hole shape. However, the structure of the opening 54 varies depending on the structure of the conductive structure. That is, the opening 54 can have various shapes, and is not limited to the structure of the opening 54 exemplarily shown in FIG. For example, the opening 54 may have a trench shape.

  A barrier metal film pattern 56 a is formed on the side wall and bottom surface of the opening 54. The barrier metal film pattern 56a has a cylindrical shape. The barrier metal film pattern 56a may include at least one of a metal and a nitride. For example, the barrier metal film pattern 56a includes one or more of titanium (Ti) and titanium nitride (TiNx). The barrier metal film pattern 56a may have a single layer structure or a multilayer structure. For example, the barrier metal film pattern 56a includes one or more of a titanium film and a titanium nitride film.

  The barrier metal film pattern 56 a serves to prevent metal atoms and / or metal ions in the metal pattern 58 b from spreading on the insulating film 52 or the substrate 50. The barrier metal film pattern 56a increases the contact area of the conductive structure and decreases the contact resistance of the conductive structure.

  In this embodiment, the barrier metal film pattern 56a may include a material that is slowly oxidized or hardly oxidized.

  The metal pattern 58b is disposed on the barrier metal film pattern 56a. For example, the metal pattern 58b includes tungsten (W). The metal pattern 58b may not completely fill the opening 54. That is, the metal pattern 58b can partially fill the opening 54. The barrier metal film pattern 56 a and the metal pattern 58 b serve as a conductive pattern that is electrically connected to the conductive region of the substrate 50.

  A metal oxide pattern 60 is formed on the metal pattern 58b. For example, the metal oxide pattern 60 includes tungsten oxide (WOx). In one embodiment, the metal oxide pattern 60 can be obtained by oxidizing the surface of the metal pattern 58b. The metal oxide pattern 60 protrudes from the insulating film 52. According to one embodiment, the protrusion of the metal oxide pattern 60 may have a thickness that is substantially greater than a portion of the metal oxide pattern 60 located in the opening 54. Further, the metal oxide pattern 60 may have substantially the same width as the metal pattern 58b.

  In the present embodiment, the metal oxide pattern 60 has a resistance substantially higher than that of the metal pattern 58b. The thickness of the metal oxide pattern 60 can be adjusted by adjusting the process conditions of the oxidation process in which the metal pattern 58b is oxidized to form the metal oxide pattern 60. Accordingly, the resistance of the metal oxide pattern 60 can be adjusted.

  The width of the metal oxide pattern 60 may be substantially smaller than the limit width (CD) of the photolithography process. In one embodiment, the width of the metal oxide pattern 60 can be reduced by increasing the thickness of the barrier metal film pattern 56a. For example, the metal oxide pattern 60 has a small width of about 50 nm or less.

  When the metal oxide pattern 60 has a relatively high resistance, a current is applied to the metal oxide pattern 60 and a joule heating effect is generated in the metal oxide pattern 60. The object pattern 60 can serve as a heating electrode.

  In the present embodiment, when the metal oxide pattern 60 has a line shape, the metal oxide pattern 60 can serve as a wiring having a width smaller than a limit width (CD) of a photolithography process. .

  3 to 5 are cross-sectional views for explaining a method of forming the conductive structure shown in FIG.

  Referring to FIG. 3, an insulating film 52 is formed on the substrate 50. The substrate 50 can be formed using a semiconductor substrate, a substrate having a semiconductor layer, a metal oxide substrate, or the like. The insulating film 52 can be formed using, for example, the same oxide as silicon oxide.

  The insulating film 52 is partially removed to form an opening 54 that exposes part of the substrate 50. The opening 54 can be formed so as to penetrate the insulating film 52 through a photographic etching process. The exposed portion of the substrate 50 includes a conductive region. In one embodiment, the opening 54 has a contact hole shape. When the opening 54 is formed through a photolithography process, the opening 54 is substantially the same as or substantially larger than the critical width (CD) of the photolithography process.

  A barrier metal film 56 is formed on the side wall and bottom surface of the opening 54 and the insulating film 52. The barrier metal film 56 is formed along the profile of the opening 54 and the insulating film 52. The barrier metal film 56 serves to prevent a phenomenon in which metal atoms and / or metal ions contained in the metal film 58 formed later diffuse into the insulating film 52 or the substrate 50. The barrier metal film 56 can be formed using a material that is slowly oxidized or hardly oxidized. For example, the barrier metal film 56 is formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. These can be used alone or in combination of two or more. The barrier metal film 56 can be formed with a single layer structure or a multilayer structure.

  The barrier metal film 56 may not completely fill the opening 54. The barrier metal film 56 is uniformly formed on the side wall and bottom surface of the opening 54 along the profile of the opening 54. When the barrier metal film 56 is formed on the side wall of the opening 54, the opening 54 has a width that is reduced by about twice the thickness of the barrier metal film 56. Therefore, the width of the opening 54 can be adjusted by adjusting the thickness of the barrier metal film 56.

  A metal film 58 is formed on the barrier metal film 56 while completely filling the opening 54. The metal film 58 is formed using, for example, tungsten. In one embodiment, since the width of the opening 54 is changed by adjusting the thickness of the barrier metal film 56, the thickness or width of the metal film 58 also changes depending on the thickness of the barrier metal film 56.

  Referring to FIG. 4, the metal film 58 and the barrier metal film 56 are partially removed until the upper surface of the insulating film 52 is exposed. For example, the metal film 58 and the barrier metal film 56 are partially removed through a chemical mechanical polishing (CMP) process. Accordingly, a barrier metal film pattern 56a and a preliminary metal pattern 58a are formed in the opening 54.

  In the chemical mechanical polishing process according to the present embodiment, the insulating film 52 is polished, and the preliminary metal pattern 58 a and the barrier metal film pattern 56 a protrude from the insulating film 52. For example, the protrusions of the preliminary metal pattern 58a and the barrier metal film pattern 56a each have a height of about 10 nm. In this case, the preliminary metal pattern 58a and the barrier metal film pattern 56a having protrusions can be obtained by a single chemical mechanical polishing process without requiring an additional etching process or a planarization process.

  In this embodiment, the preliminary metal pattern 58a having the protrusion and the barrier metal film pattern 56a may be formed through two or more chemical mechanical polishing processes performed under different process conditions. For example, after the metal film 58 and the barrier metal film 56 are polished through a first chemical mechanical polishing process under a first process condition, the insulating film 52 is polished by a second chemical mechanical polishing process under a second process condition. As a result, it is possible to form the preliminary metal pattern 58a and the barrier metal film pattern 56a having the protruding portions protruding from the insulating film 52.

  Referring to FIG. 5, the preliminary metal pattern 58a is heat-treated in an oxygen atmosphere to form a metal pattern 58b and a metal oxide pattern 60 on the barrier metal film pattern 56a.

  When the preliminary metal pattern 58 a is heat-treated in an oxygen atmosphere, the surface of the preliminary metal pattern 58 a reacts with oxygen, so that the surface of the preliminary metal pattern 58 a thermally expands along the side wall of the opening 54. Accordingly, the metal oxide pattern 60 is generated on the preliminary metal pattern 58a while the preliminary metal pattern 58a is changed to the metal pattern 58b. In one embodiment, the shape of the metal oxide pattern 60 varies depending on the structure of the preliminary metal pattern 58a.

  When the upper surface of the preliminary metal pattern 58a is positioned higher than the upper surface of the insulating film 52, the metal oxide pattern 60 grows anisotropically from the upper surface of the preliminary metal pattern 58a. Accordingly, the metal oxide pattern 60 may have a width that is substantially similar to the width of the preliminary metal pattern 58a. However, when the upper surface of the preliminary metal pattern 58a is positioned lower than the upper surface of the insulating film 52, the metal oxide pattern 60 grows isotropically from the upper surface of the preliminary metal pattern 58a. In one embodiment, the metal oxide pattern 60 may have a width wider than that of the preliminary metal pattern 58a.

  As shown in FIG. 4, when the upper surface of the preliminary metal pattern 58a is positioned slightly higher than the upper surface of the insulating film 52, the metal oxide pattern 60 grows anisotropically from the upper surface of the preliminary metal pattern 58a. That is, the metal oxide pattern 60 is formed substantially perpendicularly from the preliminary metal pattern 58a, and the metal oxide pattern 60 has a width substantially similar to the width of the preliminary metal pattern 58a. Accordingly, the width of the metal oxide pattern 60 can be substantially narrower than the width of the opening 54.

  On the other hand, when the width of the metal oxide pattern 60 is reduced, the metal oxide pattern 60 has a reduced surface roughness. For example, when the metal oxide pattern 60 has a width of about 50 nm, the metal oxide pattern 60 has a surface roughness reduced to about 1 to several tens of inches. As a result, the occurrence of electrical defects due to the surface irregularities of the metal oxide pattern 60 can be reduced. In one embodiment, when the opening 54 is formed through a photolithography process, the metal oxide pattern 60 may have a small width of about 50 nm or less by adjusting the thickness of the barrier metal film pattern 56a.

  In the present embodiment, the metal oxide pattern 60 is formed on the upper surface of the opening 54 while reacting the upper surface of the preliminary metal pattern 58a with oxygen. Accordingly, the metal oxide pattern 60 protrudes from the opening 54 to the outside. During the formation of the metal oxide pattern 60, the preliminary metal pattern 58a changes to a metal pattern 58b having a lower height than the preliminary metal pattern 58a. The height of the preliminary metal pattern 58a decreases as the height of the metal oxide pattern 60 increases. In one embodiment, the metal oxide pattern 60 has a substantially higher resistance than the resistance of the metal pattern 58b.

  In the present embodiment, the metal pattern 58b is obtained by heat-treating the preliminary metal pattern 58a. Such a heat treatment process is performed in the vicinity of the preliminary metal pattern 58a. The heat treatment process can be performed by one or more of plasma treatment and rapid thermal treatment (RTA). For example, the metal oxide pattern 60 is formed through plasma processing or rapid thermal processing. In contrast, plasma processing and rapid thermal processing may be sequentially performed to form the metal oxide pattern 60.

  The height and thickness of the metal pattern 58b and the metal oxide pattern 60 are adjusted by changing the process conditions of the heat treatment process. The widths of the metal pattern 58b and the metal oxide pattern 60 are adjusted by adjusting the thickness of the barrier metal film 56. Accordingly, the resistance of the metal pattern 58b and the metal oxide pattern 60 can be easily adjusted.

  In the present embodiment, the metal pattern 58b and the metal oxide pattern 60 are formed through a rapid thermal process. Such a rapid thermal process is performed in an oxygen atmosphere at a temperature of about 400 ° C. to about 600 ° C. for about 1 minute to about 10 minutes. In contrast, the metal pattern 58b and the metal oxide pattern 60 may be formed through a plasma processing process. In one embodiment, the plasma treatment process is performed for about 1 minute to about 10 minutes while applying a power of about 20 W to about 100 W in an oxygen atmosphere.

In this embodiment, the preliminary metal pattern 58a can be oxidized using a processing gas including oxygen (O 2 ) gas, ozone (O 3 ) gas, and the like. For example, the preliminary metal pattern 58a is oxidized while supplying oxygen gas at a flow rate of about 500 sccm or more. However, the preliminary metal pattern 58a is not limited by the above-described gas and process conditions, and can be oxidized under various gases and process conditions.

  In the present embodiment, the barrier metal film pattern 56a may not be oxidized while the preliminary metal pattern 58a is oxidized. Even if the barrier metal film pattern 56 a is slightly oxidized, the oxidized portion of the barrier metal film pattern 56 a may have a very small thickness compared to the thickness of the metal oxide pattern 60. For example, when the barrier metal film pattern 56a includes at least one of titanium and titanium oxide, the barrier metal film pattern 56a may not be substantially oxidized.

  After the metal oxide pattern 60 is formed, a process of treating the surface of the metal oxide pattern 60 is additionally performed. Such a surface treatment process includes a rapid thermal nitridation (RTN) process in which the surface of the metal oxide pattern 60 is heat-treated in a nitrogen atmosphere. In addition, a reduction process may be performed on the surface of the metal oxide pattern 60 to reduce the amount of metal oxide in the metal oxide pattern 60. Since the resistance of the metal oxide pattern 60 is changed through the surface treatment process and / or the reduction process, the resistance of the conductive structure can be adjusted.

  According to the present embodiment, the metal oxide pattern 60 is formed without depositing metal oxide or etching the deposited metal oxide. Further, the metal oxide pattern 60 has a width substantially smaller than a limit width (CD) of the photolithography process. Under the metal oxide pattern 60, a metal pattern 58b that can function as a contact plug and a barrier metal film pattern 56a are provided. Accordingly, the contact plug has a resistance substantially smaller than that of the metal oxide pattern 60, but the width of the contact plug is substantially larger than the width of the metal oxide pattern 60. Since the resistance of the metal pattern 58b and the metal oxide pattern 60 can be adjusted by adjusting the thickness and width of the metal pattern 58b and the metal oxide pattern 60, the resistance of the conductive structure can be obtained. .

  FIG. 6 is a cross-sectional view of a magnetic memory device according to the first embodiment of the present invention. The magnetic memory device shown in FIG. 6 may include a conductive structure according to the above embodiment of the present invention. For example, the magnetic memory device includes a conductive structure having substantially the same structure as the conductive structure described with reference to FIG.

  Referring to FIG. 6, a MOS transistor is provided on a semiconductor substrate 400. The MOS transistor selects at least one unit cell of the magnetic memory device. The MOS transistor includes a gate insulating film 402, a gate electrode 404, and an impurity region 406. The gate electrode 404 is provided on a word line of the magnetic memory device. In one embodiment, the gate electrode 404 extends along the first direction.

  In a spin transfer torque magnetic memory device, a current is supplied to a magnetic tunnel junction (MJT) structure in both directions of the magnetic memory device. Accordingly, a MOS transistor is applied to the magnetic memory device as a switching device.

  A first insulating film 408 covering the MOS transistor is formed on the semiconductor substrate 400. The first insulating film 408 includes, for example, an oxide such as silicon oxide. A contact plug 410 is formed through the first insulating film 408. Contact plug 410 is in electrical contact with impurity region 406.

  A conductive pattern 412 is disposed on the contact plug 410. The conductive pattern 412 can extend in the first direction. The conductive pattern 412 may have a line shape. The conductive pattern 412 includes, for example, a metal such as tungsten.

  A second insulating film 414 that covers the conductive pattern 412 is formed on the first insulating film 408. The second insulating film 414 includes, for example, the same oxide as silicon oxide. An opening 415 is formed through the second insulating film 414. The opening 415 partially exposes the conductive pattern 412. The opening 415 has a contact hole shape. In one embodiment, the plurality of openings 415 are regularly arranged in the cell region of the magnetic memory device. According to another embodiment, one opening 415 is disposed in one unit cell of the magnetic memory device.

  A first barrier metal film pattern 416 is formed on the side wall and bottom surface of the opening 415. A metal pattern 418 is located on the first barrier metal film pattern 416. The metal pattern 418 can include tungsten. The metal pattern 418 partially fills the opening 415.

  A metal oxide pattern 420 is disposed on the metal pattern 418. The metal oxide pattern 420 protrudes from the opening 415. The metal oxide pattern 420 is formed by oxidizing the metal pattern 418. When the metal pattern 418 includes tungsten, the metal oxide pattern 420 includes tungsten oxide.

  The metal pattern 418 and the metal oxide pattern 420 have substantially the same width. That is, the first barrier metal film pattern 416, the metal pattern 418, and the metal oxide pattern 420 have the same shape as the pattern structure shown in FIG.

  In the present embodiment, the width of the metal pattern 418 is substantially the same as the width of the metal oxide pattern 420. For example, the first barrier metal film pattern 416, the metal pattern 418, and the metal oxide pattern 420 correspond to the barrier metal film pattern 56a, the metal pattern 58b, and the metal oxide pattern 60 described with reference to FIG. .

  In the conductive structure, the metal pattern 418 and the first barrier metal film pattern 416 may serve as a lower electrode contact of the magnetic memory device. The metal oxide pattern 420 having a relatively high resistance may function as a heating electrode capable of heating a free layer pattern in a magnetic tunnel junction (MJT) structure of a magnetic memory device.

  A third insulating film 422 is formed on the second insulating film 414. The third insulating film 422 fills a gap between adjacent metal oxide patterns 420. The third insulating layer 422 may include a material having a high density and an excellent step coverage. For example, the third insulating layer 422 includes silicon oxide obtained using a high density plasma-chemical vapor deposition (HDP-CVD) process or an atomic layer deposition (ALD) process. Therefore, the third insulating film 422 can be uniformly formed along the profile of the metal oxide pattern 420.

  In the present embodiment, the upper surface of the third insulating film 422 and the upper surface of the metal oxide pattern 420 are located on substantially the same plane. Since the upper surface of the first barrier metal film pattern 416 is covered with the third insulating film 422, the first barrier metal film pattern 416 is not exposed.

  A magnetic tunnel junction (MTJ) structure is disposed on the third insulating film 422. The magnetic tunnel junction structure is sandwiched so that when a signal is applied from the outside to the magnetic memory device, electrons can be tunneled through a very thin tunnel oxide film interposed between the two ferromagnetic thin film layers. It has a multilayer structure. The magnetic tunnel junction structure includes a free film pattern 426, a tunnel oxide film pattern 428, and first and second fixed film patterns 430 a, 430 b, 430 c, and 432. The first and second fixed film patterns 430a, 430b, 430c, and 432 include spins having a magnetization direction substantially the same as the magnetization direction of the magnetic polarization fixed to the two ferromagnetic thin films.

  In the magnetic tunnel junction structure, at least a part of the free film pattern 426 contacts the upper surface of the metal oxide pattern 420. In an exemplary embodiment, the magnetic tunnel junction may have a multi-layered structure including a free film pattern 426, a tunnel oxide film pattern 428, and first and second fixed film patterns 430a, 430b, 430c, and 432. The structure of the magnetic tunnel junction structure is not limited.

  In the present embodiment, the free film pattern 426 includes a metal compound such as cobalt-iron-boron (Co—Fe—B).

  A second barrier metal film pattern 424 is provided between the third insulating film 422 and the free film pattern 426. The second barrier metal film pattern 424 prevents abnormal growth of metal contained in the free film pattern 426. The second barrier metal film pattern 424 may include at least one of a metal and a metal compound. For example, the second barrier metal film pattern 424 includes tantalum (Ta), titanium, tantalum nitride (TANx), titanium nitride, and the like.

  The tunnel oxide film pattern 428 may include a metal oxide such as magnesium oxide (MgOx). The first and second fixed film patterns 430a, 430b, 430c, and 432 have a structure in which the first fixed film patterns 430a, 430b, and 430c and the second fixed film pattern 432 are stacked. The first fixed film patterns 430a, 430b, and 430c are in direct contact with the tunnel oxide film pattern 428.

  In the present embodiment, the first fixed film patterns 430a, 430b, and 430c may be divided into a lower ferromagnetic layer 430a, an anti-ferromagnetic coupling spacer 430b, and an upper ferromagnetic layer 430c. . The first fixed film patterns 430a, 430b, and 430c have a stacked synthetic antiferromagnetic layer structure. The lower ferromagnetic layer 430a may include cobalt-iron-boron (Co-Fe-B), and the upper ferromagnetic layer 430c may include cobalt-iron (Co-Fe). The antiferromagnetic coupling spacer 430b includes, for example, the same metal as ruthenium (Ru). The second fixed film pattern 432 may include platinum-manganese (Pt—Mn).

  In the magnetic junction tunnel structure, the bottom surface of the free film pattern 426 is located on the metal oxide pattern 420. The metal oxide pattern 420 performs a heating film pattern function for heating the free film pattern 426. Since the width of the metal oxide pattern 420 is smaller than the width of the opening 415 in the second insulating film 414, the metal oxide pattern 420 may have a high resistance that can heat the free film pattern 426 more effectively.

  When the magnetic tunnel junction structure is provided on the upper part of the layer having a poor surface roughness like the layer having the concavo-convex portion, the characteristics of the magnetic tunnel junction structure may be deteriorated due to the Neel coupling phenomenon. is there. However, since the magnetic memory device according to the present embodiment is disposed on the metal oxide pattern 420 having an excellent flat surface, excellent operating characteristics of the magnetic memory device can be ensured.

  When the free film pattern 426 has a high temperature, the coercive force of the free film pattern 426 is reduced when storing data in the magnetic memory device. When the free film pattern 426 has a high temperature, a write current or a critical current decreases in a magnetic memory device (Spin Transfer Torque Magnetic Random Access Memory: STT-MRAM) using a spin injection mechanism, thereby reducing power consumption of the device. be able to. In one embodiment, a hard mask pattern is disposed on the magnetic tunnel junction structure.

  A fourth insulating film 434 is formed on the third insulating film 422 while filling a gap between adjacent magnetic tunnel junction structures. A fifth insulating film 436 is formed on the fourth insulating film 434. For example, the fourth insulating film 434 and the fifth insulating film 436 each include an oxide.

  An upper electrode 438 is located in the fifth insulating film 436. The upper electrode 438 passes through the fifth insulating film 436 and contacts a fixed film pattern disposed on the uppermost layer of the magnetic tunnel junction structure. The upper electrode 438 includes a metal having a small resistance, for example, tungsten.

  A bit line 440 is formed on the fifth insulating film 436. Bit line 440 is electrically connected to upper electrode 438. The bit line 440 extends along a second direction substantially orthogonal to the direction in which the word line extends.

  Hereinafter, a data storage process of the magnetic memory device according to the present embodiment will be described.

  Referring to FIG. 6, a word line signal is applied to the gate electrode 404 of the transistor, and a bit line write signal is applied to the bit line 440 at the same time. The word line signal corresponds to a voltage pulse signal having a word line voltage higher than a threshold voltage of the transistor for a predetermined time. Accordingly, the transistor connected to the word line is turned on while the word line voltage is applied. The bit line write signal corresponds to a current pulse signal that applies current to the bit line 440 while the word line signal is applied. As a result, a write current flows through the magnetic tunnel junction structure and the transistor electrically connected to the magnetic tunnel junction structure.

  The write current includes a first write current and a second write current. The first write current flows from the free film pattern 426 toward the second fixed film pattern 432. The second write current flows from the second fixed film pattern 432 toward the free film pattern 426. In one embodiment, the first write current can flow in a positive direction of the Y axis in the magnetic tunnel junction structure, and the second write current is directed in a negative direction of the Y axis. Can flow. In other words, electrons flow in the negative direction of the Y axis while the first write current flows. Also, electrons flow in the positive direction of the Y axis while the second write current flows.

  When the first write current flows through the magnetic tunnel junction structure, electrons are injected into the free film pattern 426. The electrons include up spin electrons and down spin electrons. When most of the fixed magnetic polarization in the second fixed film pattern 432 has an up spin, only the up spin electrons injected into the free film pattern 426 pass through the tunnel insulating film pattern 428 and pass through the second fixed film pattern. The downspin electrons injected into the free film pattern 426 can be accumulated in the free film pattern 426.

  The number of up-spin electrons and down-spin electrons injected into the free film pattern 426 is proportional to the current density of the first write current. Accordingly, when the current density of the first write current is increased, the free film pattern 426 is reversed to the magnetization direction of the second fixed film pattern 432 regardless of the initial magnetization direction by the down spin electrons accumulated in the free film pattern 426. It will have multiple magnetic polarizations parallel in the direction. As a result, when the current density of the first write current is higher than the first critical current density, the magnetic tunnel junction structure can be switched to have a maximum resistance value. When the first write current is supplied, the metal oxide pattern 420 heats the free film pattern 426 to reduce the coercivity of the free film pattern 426 and lower the first critical current density. Accordingly, the first write current is reduced, and the power consumption of the magnetic memory device can be minimized.

  When the second write current flows through the magnetic tunnel junction structure, most of the electrons passing through the second fixed film pattern 432 have the same magnetization direction as the fixed magnetic polarizations in the second fixed film pattern 432. It has the spin which shows. For example, when many magnetic polarizations in the second fixed film pattern 432 have up-spin, most of the electrons passing through the second fixed film pattern 432 have up-spin. For example, when the second pinned film pattern 432 is a synthetic antiferromagnetic layer, most of the electrons have spins that show the same magnetization direction as the upper ferromagnetic layer 430c of the synthetic antiferromagnetic pinned film pattern. Up-spin electrons pass through the tunnel insulating film pattern 428 and reach the free film pattern 426. The number of up spin electrons reaching the free film pattern 426 is proportional to the current density of the second write current. Accordingly, when the current density of the second write current is increased, the free film pattern 426 has a large number of magnetic polarizations parallel to the fixed magnetic polarization in the second fixed film 432 regardless of the initial magnetization direction. . Such a point is caused by up-spin electrons injected into the free film pattern 426. As a result, when the current density of the second write current is larger than the second critical current density, the magnetic tunnel junction structure can be switched to have a low resistance value. When the second write current is supplied, the metal oxide pattern 420 heats the free film pattern 426 to reduce the coercivity of the free film pattern 426 and lower the second critical current density. Accordingly, the second write current is reduced, and the power consumption of the magnetic memory device can be minimized.

  7 to 10 are cross-sectional views for explaining a method of manufacturing the magnetic memory device shown in FIG.

  Referring to FIG. 7, a MOS transistor for selecting a desired cell of a magnetic memory device is formed on a semiconductor substrate 400.

  In the process of forming the MOS transistor, a gate insulating film 402 and a gate electrode film are formed on the semiconductor substrate 400. Thereafter, the gate electrode film is patterned to form a gate electrode 404 on the gate insulating film 402. Impurities are implanted into part of the semiconductor substrate 400 adjacent to the gate electrode 404 to form impurity regions 406. The gate electrode 404 is provided on a word line of the magnetic memory device. The gate electrode 404 has a line shape extending along the first direction.

  A first insulating film 408 covering the MOS transistor is formed on the semiconductor substrate 402. A contact plug 410 penetrating the first insulating film 408 is formed. Contact plug 410 is in contact with impurity region 406. A conductive pattern 412 is formed on the first insulating film 408 and the contact plug 410. The conductive pattern 412 is electrically connected to the impurity region 406 through the contact plug 410. The contact plug 410 and the conductive pattern 412 each include a metal having a low resistance.

  In the process of forming the contact plug 410 and the conductive pattern 412, the first insulating film 408 is partially etched to form a contact hole. The contact hole is formed through, for example, a photographic etching process. A conductive film is formed over the first insulating film 408 while filling the contact hole. The contact plug 410 and the conductive pattern 412 are formed by patterning the conductive film. In another embodiment, after the contact plug 410 is formed in the contact hole, an additional conductive film is formed on the contact plug 410 and the first insulating film 408 and patterned to form the contact plug 410 and the first insulating film 408. A conductive pattern 412 can be formed thereon. In another embodiment, the contact plug 410 and the conductive pattern 412 may be formed through a damascene process.

  Referring to FIG. 8, a second insulating film 414 covering the conductive pattern 412 is formed on the first insulating film 408. The second insulating film 414 is partially etched to form an opening 415 that exposes the conductive pattern 412 at least partially. The opening 415 is formed through, for example, a photographic etching process. The opening 415 has a contact hole shape.

  A conductive structure that fills the inside of the opening 415 is formed by performing a process that is substantially the same as or substantially similar to the process described with reference to FIGS. The conductive structure protrudes from the opening 415. The conductive structure includes a first barrier metal film pattern 416, a metal pattern 418, and a metal oxide pattern 420. The first barrier metal film pattern 416 is formed on the sidewall and bottom surface of the opening 415, and the metal pattern 418 is formed on the first barrier metal film pattern 416. The metal pattern 418 partially fills the opening 415. The metal oxide pattern 420 protrudes outside the opening 415. The metal pattern 418 and the metal oxide pattern 420 may include tungsten and tungsten oxide, respectively. In one embodiment, the metal pattern 418 and the first barrier metal layer pattern 416 are used as a lower electrode of the magnetic memory device, and the metal oxide pattern 420 is used as a heating electrode of the magnetic memory device.

  Referring to FIG. 9, a third insulating film 422 covering the metal oxide pattern 420 is formed on the second insulating film 414. The third insulating film 422 is partially removed until the metal oxide pattern 420 is exposed. The third insulating film 422 is partially removed through a chemical mechanical polishing process.

  The third insulating film 422 can be formed using a material having high density and excellent step coverage. For example, the third insulating layer 422 includes silicon oxide obtained through a high density plasma-chemical vapor deposition (HDP-CVD) process or an atomic layer deposition (ALD) process. Accordingly, the third insulating film 422 is uniformly formed along the profile of the conductive structure. When the third insulating film 422 has a high density, the third insulating film 422 and the metal oxide pattern 420 may have a uniform surface without unevenness after the third insulating film 422 is partially removed by a chemical mechanical polishing process. Have

  Referring to FIG. 10, a plurality of thin films constituting a magnetic tunnel junction structure are formed on the third insulating film 422 and the metal oxide pattern 420. In one embodiment, a second barrier metal film, a free film, a tunnel oxide film, a first fixed film, and a second fixed film are sequentially stacked to form a magnetic tunnel junction structure. The first fixed film includes a lower ferromagnetic layer, an antiferromagnetic coupling spacer layer, an upper ferromagnetic layer, and the like. The second barrier metal film prevents abnormal growth of metal contained in the free film pattern. The second barrier metal film can include an amorphous metal. For example, the second barrier metal film includes tantalum, tantalum nitride, titanium, titanium nitride, and the like. The free film can include cobalt-iron-boron, and the tunnel oxide film can include magnesium oxide. In the first pinned film, the lower ferromagnetic layer may include cobalt-iron-boron, the upper ferromagnetic layer may include cobalt-iron, and the antiferromagnetic coupling spacer layer may include ruthenium. The second fixed film located on the first fixed film may include platinum-manganese (Pt—Mn).

  A plurality of thin films for forming a magnetic tunnel junction structure are sequentially patterned to form a second barrier metal film pattern 424, a free film pattern 426, a tunnel oxide film pattern 428, first fixed film patterns 430a, 430b, 430c, and first 2 A fixed film pattern 432 is formed. That is, the magnetic tunnel junction structure includes a second barrier metal film pattern 424, a free film pattern 426, a tunnel oxide film pattern 428, first fixed film patterns 430a, 430b, and 430c, and a second fixed film pattern 432. The magnetic tunnel junction structure contacts the metal oxide pattern 420. The magnetic tunnel junction structure may have an island shape. In one embodiment, a hard mask pattern is formed on the magnetic tunnel junction structure. The hard mask pattern is used as an etching mask for forming a magnetic tunnel junction structure.

  As shown in FIG. 6, a fourth insulating film 434 is formed on the third insulating film 422 while covering the magnetic tunnel junction structure. The fourth insulating film 434 sufficiently fills a gap between adjacent magnetic tunnel junction structures. A fifth insulating film 436 is formed on the fourth insulating film 434.

  The fifth insulating film 436 is partially etched to form a second contact hole that penetrates the fifth insulating film 436. The second contact hole partially exposes the magnetic tunnel junction. That is, the second fixed film pattern 432 is exposed through the second contact hole.

  After a conductive material is deposited on the fifth insulating film 436 while filling the second contact hole, the conductive material is partially removed until the fifth insulating film 436 is exposed. Accordingly, the upper electrode 438 is formed in the second contact hole. The upper electrode 438 may include tungsten and is formed through a chemical mechanical polishing process.

  A conductive film is formed over the fifth insulating film 436 and the upper electrode 438. The bit line 440 is formed by patterning the conductive film. The bit line 440 can be formed through a photolithography process.

  As described above, the conductive structure may include the metal oxide pattern 420 including tungsten oxide through a simple process. Since the metal oxide pattern 420 has a low resistance and a small width, it is used as a heating electrode of a magnetic memory device. When the magnetic memory device includes the metal oxide pattern 420 including tungsten oxide, the magnetic memory device has a low coercive force.

  FIG. 11 is a cross-sectional view of the phase change memory device according to the first embodiment of the present invention. The phase change memory device shown in FIG. 11 includes a conductive structure having substantially the same or similar configuration as the conductive structure described with reference to FIG.

  Referring to FIG. 11, a substrate 490 including an element isolation region and an active region is prepared. An impurity region 490 a is formed in the active region of the substrate 490. For example, the impurity region 490a includes the same N-type impurity as phosphorus (P), arsenic (As), or the like. An element isolation trench is provided in the element isolation region of the substrate 490, and an element isolation film pattern 492 is formed in the element isolation trench.

  A first insulating film 494 is formed over the substrate 490. A first opening 496 is formed through the first insulating film 494 to expose the impurity region 490a. A PN diode 500 is disposed in the first opening 496. The PN diode 500 fills the first opening 496. The PN diode 500 is in electrical contact with the impurity region 490a.

  In the present embodiment, the PN diode 500 includes a first polysilicon film pattern 500a and a second polysilicon film pattern 500b. The first polysilicon film pattern 500a can be doped with N-type impurities, while the second polysilicon film pattern 500b can be doped with P-type impurities. A metal silicide pattern is formed on the PN diode 500, and the metal silicide pattern reduces the interface resistance between the PN diode 500 and the conductive structure.

  A second insulating film 504 is formed on the first insulating film 494 and the PN diode 500. The second insulating film 504 includes a second opening 505 that partially exposes the PN diode 500. The second opening 505 has a contact hole shape.

  A conductive structure is located in the second opening 505. The conductive structure has substantially the same configuration as the conductive structure described with reference to FIG. The conductive structure includes a barrier metal film pattern 506, a metal pattern 508, and a metal oxide pattern 510. For example, the metal pattern 508 and the metal oxide pattern 510 include tungsten and tungsten oxide, respectively. The conductive structure is used as a lower electrode of a memory cell of the phase change memory device. Since the metal oxide pattern 510 including tungsten oxide has a high resistance, the metal oxide pattern 510 of the conductive structure can heat the phase change structure 514. For example, the metal oxide pattern 510 has a higher resistance than the metal pattern 508. In addition, the metal oxide pattern 510 may have a resistance that is greater than the total resistance of the metal pattern 508 and the barrier metal film pattern 506.

  A third insulating film 512 is formed on the second insulating film 504. The metal oxide pattern 510 of the conductive structure protrudes from the second insulating film 504 and is buried in the third insulating film 512. Accordingly, the third insulating film 512 fills the gap between the adjacent metal oxide patterns 510.

  In the present embodiment, the third insulating film 512 is formed using a material having high density and excellent step coverage, thereby sufficiently electrically insulating the metal oxide pattern 510 adjacent to the third insulating film 512. Then, the metal oxide pattern 510 is uniformly formed on the second insulating film 504 along the profile of the metal oxide pattern 510. For example, the third insulating film 512 includes silicon oxide formed through a high density plasma-chemical vapor deposition process or an atomic layer stacking process. The third insulating film 512 has substantially the same height as the metal oxide pattern 510. In one embodiment, the upper surface of the third insulating film 512 and the upper surface of the metal oxide pattern 510 are substantially on the same plane.

  The phase change structure 514 is disposed on the metal oxide pattern 510 of the conductive structure. If the metal oxide pattern 510 has a width smaller than the limit width of the photolithography process, the contact area between the metal oxide pattern 510 and the phase change structure is reduced. Therefore, phase transition easily occurs in the phase change structure 514 due to Joule heating.

  In this embodiment, the phase change structure 514 includes a chalcogenide compound that reversibly changes between an amorphous state and a crystalline state. When the chalcogenide compound has a crystalline state, the chalcogenide compound has high optical reflectivity and low electrical resistance. On the other hand, when the chalcogenide compound has an amorphous state, the chalcogenide compound has low optical reflectivity and high electrical resistance. The phase change structure 514 includes a chalcogenide compound such as a germanium-antimony-tellurium (Ge-Sb-Te) alloy.

  An upper electrode 516 is disposed on the phase change structure 514. The upper electrode 516 includes, for example, the same metal nitride as titanium nitride.

  A fourth insulating film 518 covering the upper electrode 516 is formed on the third insulating film 512. That is, the upper electrode 516 and the phase change structure 514 are embedded in the fourth insulating film 518.

  A contact hole is formed in the fourth insulating film 518. The contact hole partially exposes the upper electrode 516. An upper electrode contact 522 is disposed in the contact hole, and the upper electrode contact 522 contacts the upper electrode 516. The upper electrode contact 522 includes, for example, a metal such as tungsten.

  In the phase change memory device according to the present embodiment, the conductive structure includes a metal oxide pattern in contact with the phase change structure. Since the metal oxide pattern that can include tungsten oxide has a high resistance and a small width, the Joule heating efficiency of the phase change structure increases, and the reset current of the phase change memory device decreases. In one embodiment, the set state and the reset state of the phase change memory device are clearly distinguished because the resistance distribution of the phase change structure is reduced in the set state and the reset state.

  FIG. 12 is a cross-sectional view for explaining a method of manufacturing the phase change memory device shown in FIG.

  Referring to FIG. 12, an impurity is implanted into a predetermined portion of the substrate 490, and an impurity region 490a is formed in the predetermined portion of the substrate 490. The impurity region 490a can be formed using an ion implantation process.

  The substrate 490 is partially etched to form element isolation trenches in the substrate 490. The trench extends along the first direction. After the element isolation film is formed so as to fill the inside of the element isolation trench, the element isolation film is partially removed to form an element isolation film pattern 492 in the trench. The element isolation film pattern 492 includes, for example, an oxide.

  A first insulating film 494 is formed on the substrate 490 having the element isolation film pattern 492. For example, the first insulating film 494 is formed using the same oxide as silicon oxide. The first insulating film 494 is partially etched to form a first opening 496 that partially exposes the impurity region 490a.

  A silicon film is formed on the first insulating film 494 while filling the first opening 496. The silicon film is partially removed until the first insulating film 494 is exposed. Accordingly, a silicon film pattern is formed on the impurity region 490a in the first opening 496.

  P-type impurities are doped into the upper part of the silicon film pattern, while N-type impurities are implanted into the lower part of the silicon film pattern. Accordingly, the PN diode 500 is formed on the impurity region 490a in the first opening 496. The PN diode 500 includes a first silicon film pattern 500a and a second silicon film pattern 500b. The first and second silicon film patterns 500a and 500b include N-type impurities and P-type impurities, respectively.

  In the present embodiment, a metal silicide pattern is additionally formed on the PN diode 500.

  A second insulating film 504 is formed on the first insulating film 494 and the PN diode 500. The second insulating film 504 is formed using, for example, the same oxide as silicon oxide. The second insulating film 504 is partially etched to form a second opening 505 that partially exposes the PN diode 500.

  A conductive structure is formed on the PN diode 500. The conductive structure is formed through a process that is substantially the same as or substantially similar to the process described with reference to FIGS. The conductive structure projects onto the second opening 505 while filling the second opening 505.

  The conductive structure includes a barrier metal film pattern 506, a metal pattern 508, and a metal oxide pattern 510. The barrier metal film pattern 506 is formed on the side wall and the bottom surface of the second opening 505. The metal pattern 508 is located on the barrier metal film pattern 506. The metal pattern 508 partially fills the second opening 505. The metal pattern 508 can include tungsten. The metal oxide pattern 510 is located on the metal pattern 508 and completely fills the second opening 505. The metal oxide pattern 510 may include tungsten oxide. Since the metal oxide pattern 510 is formed in the second opening 505 through the barrier metal film pattern 506, the metal oxide pattern 510 has a width substantially smaller than the width of the second opening 505.

A third insulating film 512 that covers the metal oxide pattern 510 is formed on the second insulating film 504.
The third insulating film 512 can be formed using a material having high density and excellent step coverage. For example, the third insulating film 512 includes silicon oxide formed through a high density plasma-chemical vapor deposition process or an atomic layer stacking process. The third insulating film 512 is partially removed so that the metal oxide pattern 510 is exposed. The third insulating film 512 is partially removed using a chemical mechanical polishing process and / or an etchback process.

  Referring to FIG. 11, a phase change material film is formed on the third interlayer insulating film 512. The phase change material film is formed using, for example, the same chalcogenide compound as a germanium-antimony-tellurium (GST) alloy.

  An upper electrode film is formed on the phase change material film. For example, the upper electrode film is formed using a metal nitride such as titanium nitride. The phase change structure 514 and the upper electrode 516 are formed by patterning the upper electrode film and the phase change material film. The upper electrode 516 and the phase change structure 514 may be formed through a photolithography process.

  A fourth insulating film 518 is formed on the third insulating film 512 to cover the upper electrode 516 and the phase change structure 514. The fourth insulating film 518 is partially etched to form a contact hole 520 that exposes at least part of the upper electrode 516.

  A conductive material is deposited in the contact hole 520 to form the upper electrode contact 522 on the upper electrode 522. For example, the upper electrode contact 522 includes a metal such as tungsten, aluminum, titanium, tantalum, copper (Cu), or platinum.

  According to the present embodiment, a metal oxide pattern 510 made of tungsten oxide having a low resistance and a small width can be obtained through a simplified process. The metal oxide pattern 510 can sufficiently serve as an electrode for heating the phase change structure 514. If the phase change memory device includes the metal oxide pattern 510, the reset current of the phase change memory device is reduced, the resistance distribution is reduced, and data can be easily recorded in the phase change memory device and stored in the phase change memory device. Data can be easily read.

  FIG. 13 is a cross-sectional view of a phase change memory device according to a second embodiment of the present invention. The phase change memory device shown in FIG. 13 includes a conductive structure having substantially the same configuration as the conductive structure described with reference to FIG. The phase change memory device shown in FIG. 13 has substantially the same configuration as the phase change memory device described with reference to FIG. 11 except for the phase change structure.

  Referring to FIG. 13, a first insulating film 494, a PN diode 500, and a second insulating film 504 are provided on a substrate 490. A second opening 505 that penetrates the second insulating film 504 and exposes the PN diode 500 is formed. A conductive structure is disposed in the second opening 505. The conductive structure includes a barrier metal film pattern 506, a metal pattern 508, and a metal oxide pattern 510a having substantially the same shape as the components of the conductive structure described with reference to FIG.

  A third insulating film 512 is disposed on the second insulating film 504. The third insulating film 512 covers the conductive structure. The third insulating layer 512 may include a material having high density and excellent step coverage. For example, the third insulating film 512 includes silicon oxide obtained through a high-density plasma-chemical vapor deposition process, an atomic layer stacking process, or the like. The third insulating film 512 has an upper surface located substantially higher than the upper surface of the metal oxide pattern 510a.

  A third opening 515 is formed through the third insulating film 512 to expose the metal oxide pattern 510a. The width of the third opening 515 is substantially the same as the width of the metal oxide pattern 510a.

  A phase change structure 514a is formed on the metal oxide pattern 510a while filling the third opening 515. The phase change structure 514a protrudes above the third opening 515. In one embodiment, the phase change structure 514a includes a lower portion located in the third opening 515 and an upper portion protruding above the third opening 515. The lower width of the phase change structure 514a is smaller than the upper width. Since the phase change structure 514a contacts the metal oxide pattern 510a, a part of the phase change structure 514a heated by the metal oxide pattern 510a is limited to the third opening 515.

  An upper electrode 516 is disposed on the phase change structure 514a. A fourth insulating film 518 covering the upper electrode 516 and the phase change structure 514a is disposed on the third insulating film 512. An upper electrode contact 522 is formed through the fourth insulating film 518. The upper electrode contact 512 is electrically connected to the upper electrode 516.

  FIG. 14 is a cross-sectional view for explaining a method of manufacturing the phase change memory device shown in FIG.

  As described with reference to FIG. 12, the element isolation film pattern 492, the first insulating film 494, and the PN diode 500 are formed on the substrate 490. A second insulating film 504 is formed on the first insulating film 494 and the PN diode 500. The second insulating film 504 is partially etched to form a second opening 505 that penetrates the second insulating film 504. The second opening 505 exposes the PN diode 500 at least partially.

  A preliminary conductive structure is formed on the PN diode 500 through substantially the same or substantially similar process as described with reference to FIGS. The preliminary conductive structure projects onto the second opening 505 while filling the second opening 505. The preliminary conductive structure includes a barrier metal film pattern 506, a metal pattern 508, and a preliminary metal oxide pattern.

  The metal pattern 508 and the preliminary metal oxide pattern may include tungsten and tungsten oxide, respectively. The barrier metal film pattern 506 is formed on the side wall and the bottom surface of the second opening 505. The metal pattern 508 formed on the barrier metal film pattern 506 partially fills the second opening 505. The preliminary metal oxide pattern protrudes over the second opening 505. The preliminary metal oxide pattern has a thickness that is substantially greater than the thickness of the subsequently formed metal oxide pattern 510a. For example, the height of the preliminary metal oxide pattern is substantially the same as the sum of the height of the metal oxide pattern 510a and the height of the lower portion of the phase change structure 514a.

  A third insulating film 512 is formed on the second insulating film 504 to cover the preliminary metal oxide pattern. The third insulating film 512 can be formed using a material having high density and excellent step coverage. The third insulating film 512 is partially removed until the preliminary metal oxide pattern is exposed. The third insulating film 512 is partially removed through a chemical mechanical polishing process and / or an etchback process.

  Referring to FIG. 14, the preliminary metal oxide pattern is partially removed to form a metal oxide pattern 510 a on the metal pattern 508. At this time, the metal oxide pattern 510a protrudes on the second insulating film 504, and the barrier metal film pattern 506 is not exposed after the metal oxide pattern 510a is formed.

  When the metal oxide pattern 510a is formed on the metal pattern 508, a third opening 515 is formed at a portion where the preliminary metal oxide pattern is partially removed. That is, the portion where the preliminary metal oxide pattern is removed corresponds to the third opening 515. The metal oxide pattern 510 a is exposed through the third opening 515 formed in the third insulating film 512. The width of the third opening 515 is substantially the same as the width of the metal oxide pattern 510a.

  As shown in FIG. 13, a phase change material film is formed on the third insulating film 512 while filling the third opening 515. The phase change material film is formed using a chalcogenide compound such as a germanium-antimony-tellurium (GST) alloy. An upper electrode film is formed on the phase change material film. The upper electrode film can be formed using the same metal nitride as titanium nitride.

  The upper electrode layer and the phase change material layer are patterned to form a phase change structure 514a and an upper electrode 516 on the metal oxide pattern 510a. In one embodiment, the phase change structure 514a includes a lower portion located on the metal oxide pattern 510a in the third opening 515. The width of the lower portion of the phase change structure 514a may be substantially wider than the width of the upper portion of the phase change structure 514a.

  A fourth insulating film 518 covering the upper electrode 515 is formed on the third insulating film 512. An upper electrode contact 522 that penetrates the fourth insulating film 518 and contacts the upper electrode 516 is formed.

  FIG. 15 is a cross-sectional view of a phase change memory device according to a third embodiment of the present invention. The phase change memory device shown in FIG. 15 includes a conductive structure having substantially the same or similar configuration as the conductive structure described with reference to FIG. The phase change memory device shown in FIG. 15 has substantially the same or substantially similar configuration as the phase change memory device described with reference to FIG. 13 except for the phase change structure.

  Referring to FIG. 15, the conductive structure is located in the second opening 505 formed through the second insulating film 504. The conductive structure includes a first barrier metal film pattern 506, a metal pattern 508, and a metal oxide pattern 510a.

  A third insulating film 512 a is disposed on the second insulating film 504. A third opening 513 is formed through the third insulating film 512a. The third opening 513 exposes the metal oxide pattern 510a at least partially. The width of the third opening 513 is substantially the same as the width of the metal oxide pattern 510a.

  Phase change structure 514 b is disposed on metal oxide pattern 510 a in third opening 513. The phase change structure 514 b is located in the third opening 513 and does not protrude above the third opening 513. That is, the depth of the third opening 513 and the height of the phase change structure 514b are substantially the same.

  An upper electrode 516 is disposed on the third insulating film 512a and the phase change structure 514b. A fourth insulating film 518 covering the upper electrode 516 is formed on the third insulating film 512a. An upper electrode contact 522 is disposed through the fourth insulating film 518. The upper electrode contact 522 is electrically connected to the upper electrode 516.

  The phase change memory device shown in FIG. 15 can be manufactured through a method described later.

  Steps substantially the same as or substantially similar to the steps described with reference to FIG. 14 are performed to form a result having substantially the same configuration as the result shown in FIG.

  Referring to FIG. 15, a phase change material film is formed on the third insulating film 512a while completely filling the third opening 513. The phase change material film is partially removed until the third insulating film 512a is exposed. Accordingly, a phase change structure 514b is formed in the third opening 513. The phase change structure 514a is formed through a chemical mechanical polishing process, for example.

  An upper electrode film is formed on the phase change structure 514b and the third insulating film 512a. Next, the upper electrode film is patterned to form the upper electrode 516 on the phase change structure 514a.

  A fourth insulating film 518 covering the upper electrode 516 and the phase change structure 514b is formed on the third insulating film 512a. An upper electrode contact 522 that penetrates the fourth insulating film 518 and is electrically connected to the upper electrode 516 is formed.

  FIG. 16 is a cross-sectional view of a conductive structure according to a second embodiment of the present invention.

  Referring to FIG. 16, an insulating film 52 is provided on the substrate 50. The insulating film 52 includes an opening 54 that exposes a part of the substrate 50.

  A spacer 62 is disposed on the side wall of the opening 54. The spacer 62 includes the same nitride as the silicon nitride or the same oxynitride as the silicon oxynitride. The spacer 62 can prevent a phenomenon in which metal atoms and / or metal ions included in the metal pattern 59a spread to the insulating film 52. In one embodiment, the barrier metal film pattern may not be formed on the sidewall of the opening 54. Unlike this, a barrier metal film pattern may be formed on the spacer 62 and the substrate 50 in the opening 54.

A metal pattern 59 a is disposed in the opening 54. The metal pattern 59a partially fills the opening 54. The metal pattern 59a may include tungsten. A metal oxide pattern 60 is disposed on the metal pattern 59 a in the opening 54. The metal oxide pattern 60 may include tungsten oxide. The metal oxide pattern 60 has a width that is substantially narrower than the width of the opening 54. The metal oxide pattern 60 is generated from the metal pattern 59a. For example, the metal pattern 59a is oxidized to form the metal oxide pattern 60.
The metal oxide pattern 60 protrudes over the opening 54.

  In this embodiment, the metal oxide pattern 60 has a width substantially smaller than the limit width of the photolithography process. The width of the metal oxide pattern 60 can be changed by adjusting the thickness of the spacer 60 located on the sidewall of the opening 54.

  17 is a cross-sectional view for explaining a method of forming the conductive structure shown in FIG.

  Referring to FIG. 17, an insulating film 52 including an opening 54 is formed on the substrate 50. For example, the opening 54 exposes a predetermined portion of the substrate 50 that is the same as the conductive region.

  A spacer formation film is formed on the side wall and bottom surface of the opening 54 and the insulating film 52. The spacer forming film is formed using, for example, nitride or oxynitride. For example, the spacer forming film is formed using silicon nitride or silicon oxynitride. The spacer forming film is etched anisotropically to form the spacer 62 on the side wall of the opening 54. When the spacer 62 is formed, the width of the opening 54 is reduced to about twice the thickness of the spacer 62.

  A metal film 59 that completely fills the opening 54 is formed on the spacer 62, the substrate 50, and the insulating film 52. The metal film 59 is formed using, for example, tungsten.

  Referring to FIGS. 16 and 17, the metal film 59 is partially removed until the insulating film 52 is exposed, and a preliminary metal pattern is formed in the opening 54. The preliminary metal pattern is formed through a chemical mechanical polishing process. In an exemplary embodiment, the upper surface of the preliminary metal pattern may be substantially higher than the upper surfaces of the insulating film 52 and the spacer 62. For example, the upper surface of the preliminary metal pattern protrudes from the insulating film 52 by a thickness of about 10 mm or more. That is, the upper surface of the preliminary metal pattern is located at a finely higher position than the upper surface of the insulating film 52.

  The metal oxide pattern 60 is formed by heat-treating the preliminary metal pattern in an oxygen atmosphere. During the oxidation of the preliminary metal pattern, the preliminary metal pattern changes to the metal pattern 59a. The heat treatment process is substantially the same as or substantially similar to the heat treatment process described with reference to FIG.

  Through the above steps, a conductive structure having substantially the same configuration as the conductive structure shown in FIG. 16 is formed on the substrate 50. In one embodiment, the conductive structure is applied to the magnetic memory device described with reference to FIG. 6, the phase change memory device described with reference to FIG. 11, the phase change memory device described with reference to FIG. Is done.

  18 is a sectional view of a conductive structure according to a third embodiment of the present invention, FIG. 19 is a perspective view of the conductive structure shown in FIG. 18, and FIG. 20 is a conductive structure shown in FIG. It is a top view of a thing.

  18 to 20, an insulating film 66 is disposed on the substrate 64. The insulating film 66 includes an opening 68 that exposes a contact region on the substrate 64. In contrast, the opening 68 can directly expose a part of the substrate 64 or a conductive pattern formed on the substrate 64.

  In the present embodiment, the opening 68 may have various shapes such as a contact hole shape and a trench shape.

  A barrier metal film pattern 70 a is disposed on the side wall and bottom surface of the opening 68. The barrier metal film pattern 70 a is uniformly formed along the profile of the opening 68. For example, the barrier metal film pattern 70a includes titanium, titanium nitride, tantalum, tantalum nitride, or the like. These can be used alone or in combination.

  The barrier metal film pattern 70a serves to prevent diffusion of metal atoms and / or metal ions contained in the metal pattern 72b. The barrier metal film pattern 70a has a contact resistance in which the conductive structure is reduced by reducing a contact area between the conductive structure and the contact region of the substrate 64 or the substrate 64.

  A metal pattern 72 b is disposed on the barrier metal film pattern 70 a in the opening 68. The metal pattern 72b has a cylindrical shape and can include tungsten. The upper part of the metal pattern 72b has a ring shape. In one embodiment, the metal pattern 72b has a cylinder tube shape. The upper surface of the metal pattern 72b is positioned substantially lower than the upper surface of the barrier metal film pattern 70a. Therefore, the metal pattern 72 b is located only in the opening 68.

  A metal oxide pattern 76 is disposed on the metal pattern 72b. The outer lower portion of the metal oxide pattern 76 is in contact with the metal pattern 72b. The metal oxide pattern 76 extends from the upper part of the metal pattern 72 b, and the metal oxide pattern 76 protrudes on the insulating film 66. The metal oxide pattern 76 includes, for example, tungsten oxide. The metal oxide pattern 76 has a substantially higher resistance than the metal pattern 72b.

  In the present embodiment, the upper part of the metal oxide pattern 76 may have substantially the same ring shape as the upper part of the metal pattern 72b. The width of the upper portion of the metal oxide pattern 76 is substantially the same as the width of the upper portion of the metal pattern 72b. The metal oxide pattern 76 is generated by oxidizing the metal pattern 72b. When the upper part of the metal oxide pattern 76 has a ring shape, the area of the upper part of the metal oxide pattern 76 is substantially smaller than that of a circular column or a polygonal column. The metal oxide pattern 76 has a width substantially smaller than the width of the opening 68.

  A filling film pattern 74a that completely fills the opening 68 is disposed on the metal pattern 72b. Therefore, the upper surface of the filling film pattern 74 a is located on the same plane as the upper surface of the insulating film 66. The inner lower part of the metal pattern 76 is in contact with the filling film pattern 74a.

  In the present embodiment, the filling film pattern 74a may include a metal whose oxidation reaction is slow or hardly oxidized. For example, the filling film pattern 74a is made of titanium, titanium nitride, tantalum, tantalum nitride, or the like. These may be used alone or in combination. In contrast, the filling film pattern 74a may be made of an insulating material such as oxide, nitride, or oxynitride.

  In the present embodiment, the barrier metal film pattern 70a, the metal pattern 72b, and the filling film pattern 74a all serve as a conductive pattern that is electrically connected to the conductive region. Since the metal oxide pattern 76 has a relatively high resistance and a small area, the metal oxide pattern 76 can serve as a heating electrode.

  21 and 22 are cross-sectional views for explaining a method of forming the conductive structure shown in FIG.

  Referring to FIG. 21, an insulating film 66 is formed on a substrate 64 having a contact region formed thereon. The insulating film 66 is partially etched to form an opening 68 that partially exposes the conductive region of the substrate 64. The opening 68 can be formed through a photolithography process.

  A barrier metal film 70 is formed on the side wall and bottom surface of the opening 68 and on the insulating film 66. The barrier metal film 70 is uniformly formed along the profile of the opening 68 and the insulating film 66. When the barrier metal film 70 is formed in the opening 68, the width of the opening 68 decreases to about twice the thickness of the barrier metal film 70. Therefore, the width of the opening 68 can be adjusted by adjusting the thickness of the barrier metal film 70. As a result, the width of the opening 68 can be adjusted, and the width of the metal pattern 72b and the metal oxide pattern 76 can be adjusted.

  A metal film 72 is formed on the barrier metal film 70. For example, the metal film 72 is formed using tungsten. The metal film 72 is uniformly formed along the profile of the barrier metal film 70. The metal film 72 has a thickness substantially corresponding to the upper width of the metal pattern 72b. Accordingly, the upper width of the metal pattern 72b can be changed by adjusting the thickness of the metal film 72.

  A filling film 74 is formed on the metal film 72 while completely filling the opening 68. The filling film 74 can be formed using a material that is slow or hardly oxidized. In one embodiment, the filling film 74 is formed using the same material as the barrier metal film 70. In other embodiments, the filling layer 74 may be formed using an insulating material such as an oxide, nitride, oxynitride, or organic material.

  Referring to FIG. 22, the metal film 72, the barrier metal film 70, and the filling film 74 are partially removed until the insulating film 66 is exposed. The metal film 72, the barrier metal film 70, and the filling film 74 are partially removed through a chemical mechanical polishing process and / or an etchback process. Accordingly, a barrier metal film pattern 70a, a preliminary metal pattern 72a, and a filling film pattern 74a are formed in the opening 68. Each of the barrier metal film pattern 70a and the preliminary metal pattern 72a has a cylindrical shape. The filling film pattern 74 a on the preliminary metal pattern 72 a fills the opening 68.

  In the process of removing the metal film 72, the barrier metal film 70, and the filling film 74 in the chemical mechanical polishing process, the insulating film 66 is polished faster than the metal film 72. Accordingly, the preliminary metal pattern 72a, the barrier metal film pattern 70a, and the filling film pattern 74a protrude on the insulating film 66. For example, the upper surfaces of the preliminary metal pattern 72a, the barrier metal film pattern 70a, and the filling film pattern 74a protrude finely with a thickness of about 10 mm or more from the upper surface of the insulating film 66.

  As shown in FIG. 18, the preliminary metal pattern 72a is heat-treated in an oxygen atmosphere to form a metal pattern 72b and a metal oxide pattern 76 on the barrier metal film pattern 70a. The metal pattern 72b and the metal oxide pattern 76 may be obtained through a heat treatment process that is substantially the same as or substantially similar to the heat treatment process described with reference to FIG.

  In this embodiment, the preliminary metal pattern 72a is partially oxidized to form a metal pattern 72b having a height substantially lower than that of the preliminary metal pattern 72a. Accordingly, the metal pattern 72b has a cylindrical shape having a height substantially lower than the upper surface of the insulating film 66. The metal oxide pattern 76 has a cylindrical shape extending from the metal pattern 72b. Here, the upper portion of the metal oxide pattern 76 has a ring shape and protrudes on the insulating film 66. In one embodiment, the height of the metal oxide pattern 76 can be adjusted by adjusting the degree of oxidation of the preliminary metal pattern 72a.

  According to the present embodiment, a cylindrical tungsten oxide pattern can be formed without performing a separate tungsten vapor deposition step and / or a tungsten film etching step. Under the tungsten oxide pattern, the same plug or contact as the tungsten pattern is provided. The plug or contact has a substantially lower resistance than the tungsten oxide pattern. Since the thickness and width of the tungsten pattern and the tungsten oxide pattern can be easily adjusted, the conductive structure including the tungsten pattern and the tungsten oxide pattern can have a level of resistance desired by various semiconductor memory devices. .

  FIG. 23 is a cross-sectional view of a magnetic memory device according to the second embodiment of the present invention. The magnetic memory device shown in FIG. 23 includes a conductive structure having a configuration that is substantially the same as or substantially similar to the conductive structure described with reference to FIG. The magnetic memory device shown in FIG. 23 has substantially the same configuration as the magnetic memory device described with reference to FIG. 6 except for the conductive structure.

  Referring to FIG. 23, a MOS transistor and a first insulating film 408 covering the MOS transistor are disposed on a semiconductor substrate 400. A contact plug 410 is formed through the first insulating film 408. Contact plug 410 is in electrical contact with impurity region 406. A conductive pattern 412 is disposed on the contact plug 410.

  A second insulating film 414 covering the conductive pattern 412 is disposed on the first insulating film 408. An opening 415 is formed through the second insulating film 414 to partially expose the conductive pattern 412. The opening 415 has a contact hole shape.

  A conductive structure is located in the opening 415. The conductive structure has substantially the same or similar shape as the conductive structure described with reference to FIG. The conductive structure includes a first barrier metal film pattern 610 formed on the sidewall and bottom surface of the opening 415, a metal pattern 612 formed on the first barrier metal film pattern 610, and a filling formed on the metal pattern 612. A film pattern 614 and a metal oxide pattern 616 extending from the metal pattern 612 are included.

  The metal pattern 612 and the metal oxide pattern 616 include, for example, tungsten and tungsten oxide, respectively. The metal pattern 612 has a cylindrical shape, and the filling film pattern 614 fills the opening 415. The metal oxide pattern 616 protrudes over the opening 415. The metal oxide pattern 616 is formed by oxidizing the metal pattern 612. Accordingly, when the metal pattern 612 includes tungsten, the metal oxide pattern 616 includes tungsten oxide.

  In the conductive structure, the metal pattern 612, the first barrier metal film pattern 610, and the filling film pattern 614 are provided as lower electrode contacts of the magnetic memory device. The metal oxide pattern 616 having a relatively high resistance is provided as a heating electrode for heating the free film pattern in the magnetic tunnel junction structure of the magnetic memory device.

  A third insulating film 618 is disposed on the second insulating film 414. The third insulating film 618 fills a gap between adjacent metal oxide patterns 616. The third insulating layer 618 may include a material having a high density and an excellent step coverage. For example, the third insulating film 618 is made of silicon oxide obtained by a high-density plasma-chemical vapor deposition process or an atomic layer stacking process. The upper surfaces of the third insulating film 618 and the metal oxide pattern 616 are located on substantially the same plane. Since the upper surface of the first barrier metal film pattern 610 is covered with the third insulating film 618, the first barrier metal film pattern 610 is not exposed.

  A magnetic tunnel junction structure is disposed on the third insulating film 618. The magnetic tunnel junction structure has substantially the same or similar structure as the magnetic tunnel junction structure described with reference to FIG. The free film pattern 426 of the magnetic tunnel junction structure is located on the metal oxide pattern 616. When the metal oxide pattern 616 has a ring shape, the contact area between the free film pattern 426 and the metal oxide pattern 616 is reduced. As a result, the heating efficiency of the free film pattern 426 by the metal oxide pattern 616 is further increased. As the upper surface area of the metal oxide pattern 616 is reduced, the flatness of the upper surface of the metal oxide pattern 616 is further improved.

  A fourth insulating film 434, a fifth insulating film 436, an upper electrode 438, and a third insulating film 618 are formed on the third insulating film 618 by performing a process that is substantially the same as or substantially similar to the process described with reference to FIG. Bit line 440 is formed.

  24 and 25 are cross-sectional views for explaining a method of manufacturing the magnetic memory device shown in FIG. The magnetic memory device shown in FIG. 23 has substantially the same or similar configuration as the magnetic memory device described with reference to FIG. 6 except for the conductive structure. Therefore, the process for manufacturing the magnetic memory device shown in FIG. 23 is substantially the same as or similar to the process described with reference to FIGS. 7 to 10 except for the process of forming the conductive structure. Yes.

  A transistor, a first insulating film 408, a contact plug 410, and a conductive pattern 412 are formed on the semiconductor substrate 400 by performing substantially the same or similar process as that described with reference to FIG.

  Referring to FIG. 24, a second insulating film 414 covering the conductive pattern 412 is formed on the first insulating film 408. By partially removing the second insulating film 414, an opening 415 that at least partially exposes the conductive pattern 412 is formed.

  A conductive structure that fills the opening 415 is formed by performing substantially the same or similar process as described with reference to FIGS. 21 and 22. The conductive structure includes a barrier metal film pattern 610 having a cylinder shape, a metal pattern 612 having a cylinder shape, a filling film pattern 614 filling the opening 415, and a metal oxide pattern 616 extending upward from the metal pattern 612. .

  Referring to FIG. 25, a third insulating film 618 covering the metal oxide pattern 616 is formed on the second insulating film 414. The third insulating film 618 can be formed using a material having high density and excellent step coverage. For example, the third insulating layer 618 includes silicon oxide obtained and formed through a high-density plasma-chemical vapor deposition process or an atomic layer stacking process.

  The third insulating film 618 is partially removed until the metal oxide pattern 616 is exposed. The third insulating film 618 is partially removed through a chemical mechanical polishing process. In this case, the barrier metal film pattern 610 is not exposed through the third insulating film 618. When the third insulating film 618 has high density, the third insulating film 618 and the metal oxide pattern 616 are uniform without unevenness after the chemical mechanical polishing process for partially removing the third insulating film 618. Having a surface.

  As shown in FIG. 23, a magnetic tunnel junction structure is formed on the third insulating film 618 and the metal oxide pattern 616. A fourth insulating film 434, a fifth insulating film 436, an upper electrode 438, and a bit line 440 are formed on the third insulating film 618 while covering the magnetic tunnel junction structure. The process of forming the magnetic tunnel junction structure, the fourth insulating film 434, the fifth insulating film 436, the upper electrode 438, and the bit line 440 is substantially the same as or similar to the process described with reference to FIG. .

  FIG. 26 is a cross-sectional view of a phase change memory device according to a fourth embodiment of the present invention. The phase change memory device shown in FIG. 26 includes a conductive structure having substantially the same or similar configuration as the conductive structure described with reference to FIG. 1 or FIG. In one embodiment, the phase change memory device shown in FIG. 26 has substantially the same or similar configuration as the phase change memory device described with reference to FIG. 11 except for the conductive structure.

  Referring to FIG. 26, the first insulating film 494, the PN diode 500, and the second insulating film 504 are disposed on the substrate 490. The first insulating film 494 includes a first opening 496 in which the PN diode 500 is located.

  A second opening 505 is formed through the second insulating film 504. The second opening 505 partially exposes the PN diode 500.

  A first barrier metal film pattern 650, a metal pattern 652, a filling film pattern 654, and a metal oxide pattern 656 are disposed in the second opening 505. For example, the metal pattern 652 and the metal oxide pattern 656 include tungsten and tungsten oxide, respectively. The first barrier metal film pattern 650, the metal pattern 652, the filling film pattern 654, and the metal oxide pattern 656 are the barrier metal film pattern 70a, the metal pattern 72b, the filling film pattern 74a, and the metal oxide described with reference to FIG. The object pattern 76 has substantially the same structure. Metal oxide pattern 656 heats phase change structure 514.

  A third insulating film 660 is disposed on the second insulating film 504. The third insulating film 660 fills a gap between adjacent metal oxide patterns 656.

  The phase change structure 514 is disposed on the metal oxide pattern 656 and the third insulating film 660. Phase change structure 514 contacts metal oxide pattern 656. When the metal oxide pattern 656 has a ring shape, a contact area between the metal oxide pattern 656 and the phase change structure 514 is reduced. Therefore, phase transition easily occurs in the phase change structure 514 due to Joule heating.

  An upper electrode 516, a fourth insulating film 518, and an upper electrode contact 522 are disposed on the phase change structure 514.

  According to the present embodiment, the phase change memory device can ensure high Joule heating efficiency and reduced reset current. Since the resistance distribution of the phase change structure in the set state and the reset state of the phase change memory device is reduced, the set state and the reset state of the phase change memory device are clearly distinguished.

  In the manufacturing process of the phase change memory device shown in FIG. 26, substantially the same or similar process as the process described with reference to FIG. 12 is performed, and the first insulating film 494, the PN diode is formed on the substrate 490. 500, a second insulating film 504, and a second opening 505 are formed. Thereafter, a conductive structure protruding above the second opening 505 while filling the second opening 505 by performing substantially the same or similar process as described with reference to FIGS. 21 and 22. Form.

  After the third insulating film 660 is formed on the second insulating film 504 so as to cover the metal oxide pattern 656, the third insulating film 660 is partially removed through a chemical mechanical polishing process, thereby forming the metal oxide pattern 656. Expose.

  A phase change structure 514, an upper electrode 516, and a fourth insulating film 518 are formed on the metal oxide pattern 656 and the third insulating film 660 by performing substantially the same or similar processes as described with reference to FIG. And an upper electrode contact 522 are formed.

  FIG. 27 is a cross-sectional view of a conductive structure according to a fourth embodiment of the present invention.

  Referring to FIG. 27, an insulating film 66 is provided on the substrate 64. The insulating film 66 includes an opening 68 that exposes the conductive region of the substrate 64.

  A spacer 80 made of an insulating material is disposed on the side wall of the opening 68. For example, the spacer 80 includes silicon nitride, silicon oxynitride, or the like. In one embodiment, the barrier metal film pattern may not be formed on the sidewall of the opening 68. Unlike this, a barrier metal film pattern may be disposed on the spacer 80 and the substrate 64 in the opening 68.

  A metal pattern 82 having a cylindrical shape and containing tungsten is disposed in the opening 68. The metal pattern 82 is uniformly formed along the profile of the opening 68 and the substrate 64. A filling film pattern 84 is disposed on the metal pattern 82. The filling film pattern 84 fills the opening 68. A metal oxide pattern 86 containing tungsten oxide is disposed on the metal pattern 82. The metal oxide pattern 86 extends from the metal pattern 82. The metal pattern 82, the metal oxide pattern 86, and the filling film pattern 84 have substantially the same structure as the metal pattern 72b, the filling film pattern 74a, and the metal oxide pattern 76 described with reference to FIG.

  In the process of forming the conductive structure shown in FIG. 27, an insulating film 66 is formed on the substrate 64. The insulating film 66 is partially etched to form an opening 68 that exposes part of the substrate 64. The opening 68 can be formed through a photolithography process. A spacer 80 is formed on the side wall of the opening 68.

  A metal film is formed on the spacer 80, the substrate 64, and the insulating film 66. The metal film is uniformly formed along the profile of the opening 68. A filling film filling the opening 68 is formed on the metal film.

  The metal film and the spacer 80 are partially removed through a chemical mechanical polishing process until the insulating film 66 is exposed. Along with this, a preliminary metal pattern is formed in the opening 68. By heat-treating the preliminary metal pattern in an oxygen atmosphere, a metal pattern 82 containing tungsten and a metal oxide pattern 86 containing tungsten oxide are formed in the opening 68. As a result, a conductive structure having substantially the same configuration as the conductive structure described with reference to FIG. 18 can be obtained.

  In the present embodiment, the conductive structure shown in FIG. 27 includes the magnetic memory device described with reference to FIG. 6, the phase change memory device described with reference to FIG. 11, and the phase change memory described with reference to FIG. It can be applied to various devices.

  FIG. 28 is a cross-sectional view of a phase change memory device according to a fifth embodiment of the present invention.

  Referring to FIG. 28, the first insulating film 494 and the PN diode 500 are disposed on the substrate 490. The first insulating film 494 and the PN diode 500 are substantially the same as those described with reference to FIG.

  A metal pattern 530 a containing tungsten is disposed on the first insulating film 494. The metal pattern 530a is electrically connected to the PN diode 500d. A second insulating film 504 covering the metal pattern 530a is disposed on the first insulating film 494.

  A metal oxide pattern 536 including tungsten oxide is disposed on the metal pattern 530a. The metal oxide pattern 536 extends from the metal pattern 530a and may have a cylindrical shape.

  An insulating film pattern 534 that contacts the metal oxide pattern 536 is formed. When the metal oxide pattern 536 has a cylindrical shape, the insulating film pattern 534 fills the inside of the metal oxide pattern 536. For example, the insulating film pattern 534 includes the same oxide as silicon oxide. In contrast, the insulating film pattern 534 may have a multilayer structure including a silicon nitride film and a silicon oxide film.

  A phase change structure 514 is disposed on the insulating film pattern 534 and the second insulating film 504. Phase change structure 514 contacts metal oxide pattern 536. An upper electrode 516 and an upper electrode contact 522 are disposed on the phase change structure 514.

  FIG. 29 is a cross-sectional view for illustrating the method of manufacturing the phase change memory device shown in FIG.

  Referring to FIG. 29, the device isolation layer pattern 492, the first insulating layer 494, and the PN diode are formed on the substrate 490 by performing substantially the same or similar process as described with reference to FIG. 500 is formed.

  A preliminary metal pattern 530 containing tungsten is formed on the PN diode 500, and a second insulating film 504 covering the preliminary metal pattern 530 is formed on the first insulating film 494. The second insulating film 504 is partially etched to form a second opening 505 that exposes the preliminary metal pattern 530.

  A spacer formation film is formed on the side wall and bottom surface of the second opening 505. The spacer formation film can be formed using oxide, nitride, oxynitride, or the like. For example, the spacer formation film is formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. An inner spacer is formed on the side wall of the second opening 505 by partially etching the spacer forming film through an anisotropic etching process.

  An additional insulating film is formed in the second opening 505 where the inner spacer is formed. The additional insulating film is formed using, for example, an oxide, a nitride, or an oxynitride. In one embodiment, the additional insulating film is formed using a material having an etching selection cost with respect to the spacer forming film. For example, when the spacer forming film includes silicon nitride, the additional insulating film includes silicon oxide.

The additional insulating film is partially removed until the second insulating film 504 and the inner spacer are exposed.
The additional insulating film is partially removed using a chemical mechanical polishing process and / or an etchback process.

  The inner spacer is removed from the second opening 505, and an insulating film pattern 534 including the third opening 532 is formed in the second opening 505. The insulating film pattern 534 has a cylinder shape. The inner spacer is removed through an isotropic etching process or an anisotropic etching process. The insulating film pattern 534 includes silicon oxide. In one embodiment, the width of the third opening 532 varies depending on the thickness of the insulating film pattern 534.

  As shown in FIG. 28, the preliminary metal pattern 530 exposed through the third opening 532 is oxidized to form a metal oxide pattern 536 in the third opening 532. The metal oxide pattern 536 fills the third opening 532. Simultaneously with the formation of the metal oxide pattern 536, the metal pattern 530a is formed from the preliminary metal pattern 530. That is, the spare metal pattern 530 is partially consumed due to oxidation, so that the spare metal pattern 530 is changed to the metal pattern 530a.

  The insulating film pattern 534 and the metal oxide pattern 536 are partially removed until the second insulating film 504 is exposed. The insulating film pattern 534 and the metal oxide pattern 536 are partially removed through a chemical mechanical polishing process, for example.

  A phase change structure 514 is formed on the metal oxide pattern 536 and the second insulating film 504. An upper electrode 516 and an upper electrode contact 522 are formed on the phase change structure 514.

  FIG. 30 is a cross-sectional view for explaining another method for manufacturing the phase change memory device shown in FIG.

  Referring to FIG. 30, a process substantially the same as or similar to the process described with reference to FIG. 12 is performed, and the device isolation layer pattern 492, the first insulating layer 494, and the PN diode 500 are formed on the substrate 490. Form.

  A preliminary metal pattern 530 containing tungsten, a second insulating film 504, and a second opening 505 are formed by performing substantially the same or similar process as described with reference to FIG. The preliminary metal pattern 530 contacts the PN diode 500, and the second insulating film 504 covers the preliminary metal pattern 530. The second opening 505 partially exposes the upper surface of the preliminary metal pattern 530.

  After the first additional insulating film is formed on the side wall and the bottom surface of the second opening 505, a second additional insulating film that completely fills the second opening 505 is formed on the first additional insulating film. In one embodiment, the second additional insulating film includes a material having an etching selectivity with respect to the first additional insulating film. The first and second additional insulating films are partially removed until the second insulating film 504 is exposed.

  The first and second additional insulating films are partially etched to form an insulating film pattern 534 including a third opening 532. The insulating film pattern 534 is formed through an anisotropic etching process. The insulating film pattern 534 has a cylinder shape. Since the first additional insulating film partially remains in the second opening 505, the insulating film pattern 534 includes silicon nitride and silicon oxide. That is, the insulating film pattern 534 includes the remaining portions of the first and second additional insulating films.

  28, a metal pattern 530a, a metal oxide pattern 536 including tungsten oxide, and a phase change structure are performed on the insulating film pattern 534, which is substantially the same as or substantially similar to the process described with reference to FIG. 514, the upper electrode 516, and the upper electrode contact 522 are formed one after another.

  FIG. 31 is a cross-sectional view of a phase change memory device according to a sixth embodiment of the present invention. The phase change memory device shown in FIG. 31 has substantially the same or similar configuration as the phase change memory device described with reference to FIG. 28 except for the phase change structure.

  Referring to FIG. 31, the phase change structure 514a of the phase change memory device includes a lower portion extending from a metal oxide pattern 536a including tungsten oxide. That is, the phase change structure 514a has a cylindrical shape. The phase change structure 514 a protrudes into the second insulating film 504.

  The process for manufacturing the phase change memory device shown in FIG. 31 is substantially the same as or similar to the process described with reference to FIG.

  In the manufacturing process of the phase change memory device shown in FIG. 31, the preliminary metal pattern including tungsten exposed through the third opening 532 is oxidized to form a metal oxide pattern 536a and a metal pattern 530a including tungsten oxide. . Here, the metal oxide pattern 536a partially fills the third opening 532. Further, the metal oxide pattern 536a and the metal pattern 530a are not partially removed.

  After the metal oxide pattern 536a is partially filled with the third opening 532, the phase change structure 514a completely fills the third opening 532 over the metal oxide pattern 536a and the second insulating layer 504. Formed.

  In the present embodiment, the conductive structure used as the heating electrode shown in FIG. 28 can be applied to the magnetic memory device described with reference to FIG. That is, the conductive structure in contact with the magnetic tunnel junction structure shown in FIG. 6 can replace the conductive structure shown in FIG.

  FIG. 32 is a cross-sectional view of a conductive structure according to a fifth embodiment of the present invention.

  Referring to FIG. 32, a metal pattern 92 a containing tungsten is disposed on the substrate 90. The metal pattern 92a includes an upper portion in which a recess is formed. That is, the process condition of the heat treatment process is adjusted so that the upper central portion of the metal pattern 92a is oxidized faster than the upper end portion of the metal pattern 92a. The recess of the metal pattern 92a may have a round shape such as an arch shape. Accordingly, the upper edge portion of the metal pattern 92a is positioned higher than the upper central portion of the metal pattern 92a.

  An insulating film 94 covering the metal pattern 92a is formed on the substrate 90. An opening 96 is formed through the insulating film 94. The opening 96 exposes the upper surface of the metal pattern 92a having a recess.

  A metal oxide pattern 98 including tungsten oxide is disposed on the metal pattern 92a. The metal oxide pattern 98 fills the opening 96. The metal oxide pattern 98 is generated from the metal pattern 92a. For example, the metal oxide pattern 98 is formed by oxidizing the metal pattern 92a.

  FIG. 33 is a cross-sectional view for explaining a method of forming the conductive structure shown in FIG.

  Referring to FIG. 33, after forming a metal film containing tungsten on the substrate 90, the metal film is patterned to form a preliminary metal pattern 92 on the substrate 90. An insulating film 94 covering the preliminary metal pattern 92 is formed on the substrate 90.

  By partially etching the insulating film 94, an opening 96 exposing at least a part of the preliminary metal pattern 92 is formed. The opening 96 can be formed through a photolithography process.

  Referring to FIGS. 32 and 33, the preliminary metal pattern 92 exposed through the opening 96 is heat-treated in an oxygen atmosphere to form a metal oxide pattern 98 and a metal pattern 92 a on the substrate 90. The metal oxide pattern 98 and the metal pattern 92a include tungsten oxide and tungsten, respectively.

  In the heat treatment process for forming the metal oxide pattern 98 and the metal pattern 92a, the preliminary metal pattern 92 reacts with oxygen and expands above the opening 96. Accordingly, a metal oxide pattern 98 that fills the opening 96 is formed on the metal pattern 92a. At the same time, the upper portion of the preliminary metal pattern 92 is oxidized, whereby the preliminary metal pattern 92 is changed to the metal pattern 92a. By adjusting the process conditions of the heat treatment process, the central portion of the upper portion of the preliminary metal pattern 92 is oxidized earlier than the upper edge portion of the preliminary metal pattern 92. Accordingly, the metal pattern 92a may include an upper portion where a round-shaped recess is formed, and the metal oxide pattern 98 may include a protrusion corresponding to the recess of the metal pattern 92a.

  In the present embodiment, the metal oxide pattern 98 and the insulating film pattern 94 are planarized through a planarization process. For example, the metal oxide pattern 98 and the insulating film pattern 94 are planarized through a chemical mechanical polishing process.

  FIG. 34 is a cross-sectional view of a magnetic memory device according to a third embodiment of the present invention. The magnetic memory device shown in FIG. 34 includes a conductive pattern and a lower electrode contact having substantially the same configuration as the conductive pattern and the lower electrode pattern of the conductive structure described with reference to FIG. Also, the magnetic memory device shown in FIG. 34 has substantially the same configuration as the magnetic memory device described with reference to FIG. 6 except for the conductive pattern and the lower electrode contact.

  Referring to FIG. 34, a conductive structure is disposed on the first insulating film 408 and the contact plug 410. The conductive structure may have a structure that is substantially the same as or similar to the conductive structure described with reference to FIG.

  The conductive structure includes a metal pattern 450 including tungsten and a metal oxide pattern 454 including tungsten oxide. The metal pattern 450 contacts the contact plug 410. The metal pattern 450 includes an upper portion in which a round-shaped recess is formed. The upper edge of the metal pattern 450 is substantially higher than the upper central portion of the metal pattern 450.

  A second insulating film 452 covering the metal pattern 450 is disposed on the first insulating film 408. An opening 453 passing through the second insulating film 452 is provided. The opening 453 exposes at least a part of the upper portion of the metal pattern 450.

  A metal oxide pattern 454 including tungsten oxide is disposed on the metal pattern 450. The metal oxide pattern 454 fills the opening 453. The metal oxide pattern 454 is generated by oxidizing the metal pattern 450.

  The metal oxide pattern 454 serves as a heating electrode for heating the magnetic tunnel junction structure of the magnetic memory device. The metal oxide pattern 454 also functions as a lower electrode contact of the magnetic memory device.

  A magnetic tunnel junction structure, a third insulating film 434a, a fourth insulating film 436, an upper electrode 438, and a bit line 440 are disposed on the second insulating film 452.

  The magnetic memory device shown in FIG. 34 has substantially the same or similar configuration as the magnetic memory device described with reference to FIG. 6 except for the conductive pattern and the lower electrode pattern. Therefore, the magnetic memory device shown in FIG. 34 performs substantially the same or similar processes as those described with reference to FIGS. 7 to 10 except for the process of forming the conductive pattern and the lower electrode contact. Can be manufactured. The conductive pattern and the lower electrode contact are formed through substantially the same or similar process as described with reference to FIG.

  FIG. 35 is a cross-sectional view of a magnetic memory device according to a fourth embodiment of the present invention. The magnetic memory device shown in FIG. 35 has substantially the same or similar configuration as the magnetic memory device described with reference to FIG. 6 except for the conductive pattern and the lower electrode contact. The magnetic memory device shown in FIG. 35 is substantially the same as or similar to the conductive pattern of the conductive structure and the lower electrode contact described with reference to FIG. 32 except for the spacer on the metal oxide pattern sidewall. And a lower electrode contact.

  Referring to FIG. 35, a spacer 455 is provided on the sidewall of the opening 453 formed through the second insulating film 452. The spacer 455 reduces the width of the opening 453, and accordingly, the upper width of the metal oxide pattern 456 including tungsten oxide is considerably reduced as compared with the conductive structure described with reference to FIG.

  The process for manufacturing the magnetic memory device shown in FIG. 35 is substantially the same or similar to the process for manufacturing the magnetic memory device described with reference to FIG. In one embodiment, after forming the opening 453 through the second insulating film 452, the spacer 455 is formed on the sidewall of the opening 453. The spacer 455 can include an oxide, a nitride, an oxynitride, or the like. For example, the spacer 455 is formed using silicon oxide, silicon nitride, silicon oxynitride, or the like.

  FIG. 36 is a cross-sectional view of a phase change memory device according to a seventh embodiment of the present invention.

  Referring to FIG. 36, a first insulating layer 494 and a PN diode 500 are provided on a substrate 490. A metal pattern 502 a containing tungsten is located on the first insulating film 494. The metal pattern 502 a is in contact with the PN diode 500. The metal pattern 502a has an upper portion including a round-shaped recess. In one embodiment, the round recess of the metal pattern 502a is formed through an oxidation process described below.

  A second insulating film 550 that covers the metal pattern 502 a is disposed on the first insulating film 494. An opening 553 that penetrates the second insulating film 550 is formed. The opening 553 exposes at least a part of the metal pattern 502a. A spacer 552 is provided on the side wall of the opening 553. The spacer 552 includes an insulating material. When the spacer 552 is positioned in the opening 553, the width of the opening 553 can be reduced.

  A metal oxide pattern 554 containing tungsten oxide is disposed on the metal pattern 502a located in the opening 553 in which the spacer 552 is formed. The metal oxide pattern 554 is generated from the metal pattern 502a by partially oxidizing the metal pattern 502a. The upper surface of the metal oxide pattern 554 is positioned substantially lower than the upper end of the opening 553. That is, the metal oxide pattern 554 partially fills the opening 553. The metal oxide pattern 554 functions as a lower electrode contact of the phase change memory device.

  A phase change structure 556 is disposed on the metal oxide pattern 554. Phase change structure 556 fills opening 553 and protrudes into opening 553. Phase change structure 556 includes a lower portion located in opening 553 and an upper portion protruding above opening 553. The lower portion of phase change structure 556 has a substantially smaller width than the upper portion of phase change structure 556.

An upper electrode 516, a third insulating layer 518 a, and an upper electrode contact 522 are provided on the phase change structure 556.
FIG. 37 is a cross-sectional view of a conductive structure according to a sixth embodiment of the present invention.

  The conductive structure shown in FIG. 37 is substantially the same as the conductive structure described with reference to FIG. 32 except that the metal oxide pattern 98a containing tungsten partially fills the opening 96. It has a similar configuration.

  The process for forming the conductive structure shown in FIG. 37 is substantially the same as or similar to the process described with reference to FIG. In one embodiment, the metal oxide pattern 98a may partially fill the opening 96 by adjusting the process conditions of the oxidation process performed on the preliminary metal pattern.

  FIG. 38 is a cross-sectional view of a phase change memory device according to an eighth embodiment of the present invention.

  Referring to FIG. 38, the first insulating film 10 and the PN diode 11 are provided on the substrate 8. A conductive pattern 12 a containing a metal is disposed on the PN diode 11 and the first insulating film 10. The conductive pattern 12a includes a metal having a low resistance. For example, the conductive pattern 12a includes tungsten.

A second insulating film pattern 14 is formed on the first insulating film 10 to cover the conductive pattern 12a.
A first opening 16 is formed in the second insulating film pattern 14. The first opening 16 at least partially exposes the conductive pattern 12a. The second insulating film pattern 14 includes an oxide or a nitride. For example, the second insulating film pattern 14 includes silicon nitride or silicon oxide.

  In the present embodiment, the conductive pattern 12a has an upper portion in which a recess is formed. The upper edge of the conductive pattern 12a is substantially higher than the upper center of the conductive pattern 12a. According to one embodiment, by adjusting the process conditions of the heat treatment process, the upper central portion of the preliminary metal pattern is oxidized earlier than the upper edge portion of the preliminary metal pattern.

  A lower electrode contact 18 is disposed in the first opening 16. The lower electrode contact 18 includes a metal oxide generated from the conductive pattern 12a. The lower electrode contact 18 fills the first opening 16.

  In the present embodiment, the lower electrode contact 18 is obtained by oxidizing the conductive pattern 12a. For example, a metal oxide is generated from the conductive pattern 12 a above the first opening 16, and accordingly, the lower electrode contact 18 is formed in the first opening 16. The conductive pattern 12a includes a rounded recess, and the lower electrode contact 18 includes a round-shaped protrusion corresponding to the round-shaped recess of the conductive pattern 12a. When the lower electrode contact 18 has a round-shaped protrusion and the conductive pattern 12a has a round-shaped recess, the upper surface of the lower electrode contact 18 is further separated from the upper surface of the conductive pattern 12a. Accordingly, it is possible to reduce a phenomenon in which heat generated between the phase change structure 22a and the lower electrode contact 18 is diffused. That is, the phase change structure 22a can ensure more improved Joule heating efficiency.

  In the present embodiment, the conductive pattern 12a may include tungsten, and accordingly, the lower electrode contact 18 includes tungsten oxide.

A spacer 20 is disposed on the side wall of the first opening 16. The spacer 20 contacts the lower electrode contact 18. The width of the first opening 16 is reduced by forming the spacer 20. Accordingly, the contact area between the lower electrode contact 18 and the phase change structure 22a is also reduced.
The spacer 20 includes the same nitride as the silicon nitride and the same oxynitride as the silicon oxynitride.

The phase change structure 22 a is disposed on the lower electrode contact 18 while filling the first opening 16. In one embodiment, the contact area between the lower electrode contact 18 and the phase change structure 22a decreases as the area corresponding to the contact area of the spacer 20 provided on the lower electrode contact 18 decreases.

The phase change structure 22a includes a chalcogenide compound whose crystal structure changes between an amorphous state and a crystalline state by heating. The chalcogenide compound is relatively high in optical reflectivity and relatively low in electrical resistance in a crystalline state. On the other hand, chalcogenide compounds have low reflectivity and high electrical resistance in the amorphous state. In one embodiment, the chalcogenide compound comprises a germanium-antimony-tellurium (Ge-Sb-Te) alloy.
The phase change structure 22 a filling the first opening 16 protrudes above the second insulating film pattern 14. In one embodiment, the upper portion of the phase change structure 22a has a wider width than the lower portion.

  An upper electrode 24 is disposed on the phase change structure 22a. For example, the upper electrode 24 includes a metal nitride such as titanium nitride. The upper electrode 24 has substantially the same width as the upper portion of the phase change structure 22a.

  A third insulating film pattern 26 is formed on the second insulating film pattern 14. The third insulating film pattern 26 covers the upper electrode 24 and the phase change structure 22a. A second opening 28 is formed through the third insulating film pattern 26. The second opening 28 exposes the upper electrode 24 at least partially.

  An upper electrode contact 30 is disposed in the second opening 28. The upper electrode contact 30 includes, for example, the same metal as tungsten.

According to the present embodiment, the phase change memory device includes a lower electrode contact including a metal oxide generated from a conductive pattern of metal. In one embodiment, the bottom electrode contact has a high resistance. Since the phase change memory device includes a lower electrode contact made of a metal oxide, the phase change memory device can secure a reduced reset current due to an improved Joule heating effect. Since the resistance distribution of the phase change structure is fine in the set state and the reset state, the set state and the reset state of the phase change memory device are clearly distinguished.
In one embodiment, since the lower electrode contact is disposed under the phase change structure in the opening, the opening formed in the portion where the phase change structure is located has a reduced aspect ratio. . Therefore, a phenomenon in which voids or seams are generated in the phase change structure can be prevented, and malfunction of the phase change memory device can be prevented.

  39 to 44 are cross-sectional views for explaining a method of manufacturing the phase change memory device shown in FIG.

  Referring to FIG. 39, an element isolation film pattern and an impurity region 8a are formed on a substrate 8. A first insulating film 10 is formed on the substrate 8 while covering the element isolation film pattern and the impurity region 8a. The first insulating film 10 is formed using, for example, the same oxide as silicon oxide.

  A PN diode 11 is formed through the first insulating film 10. The PN diode 11 is in electrical contact with the impurity region 8a. A preliminary conductive pattern 12 is formed on the PN diode 11 and the first insulating film 10. The preliminary conductive pattern 12 contacts the PN diode 11, and the preliminary conductive pattern 12 includes a metal.

  In the present embodiment, the preliminary conductive pattern 12 includes a metal having a low resistance. In this case, the oxide of such a metal is electrically conductive and expands upward when such a metal is oxidized. For example, the preliminary conductive pattern 12 includes the same metal as tungsten.

  A second insulating film is formed on the first insulating film 10 while covering the preliminary conductive pattern 12. The second insulating film is formed using the same oxide as silicon oxide or a nitride such as silicon nitride.

  The second insulating film is partially etched to form a first opening 16 that partially exposes the preliminary conductive pattern 12. The first opening 16 has a contact hole shape. By forming the first opening 16, the second insulating film pattern 14 including the first opening 16 is formed on the first insulating film 10.

  Referring to FIG. 40, the exposed portion of the preliminary conductive pattern 12 through the first opening 16 is heat-treated in an oxygen atmosphere to form the lower electrode contact 18 on the preliminary conductive pattern 12. For example, the preliminary conductive pattern 12 is reacted with oxygen, and the reacted part of the preliminary conductive pattern 12 is thermally expanded toward the upper side of the first opening 16, thereby forming the lower electrode contact 18. The lower electrode contact 18 partially fills the first opening 16.

  In the present embodiment, the lower electrode contact 18 includes a metal oxide generated from the metal of the preliminary conductive pattern 12. The lower electrode contact 18 including a metal oxide has a resistance substantially higher than that of the preliminary conductive pattern 12.

  While the preliminary conductive pattern 12 is heat-treated in an oxygen atmosphere, the exposed portion of the preliminary conductive pattern 12 continues to react with oxygen, so that the lower electrode contact 18 extends laterally along the upper surface of the preliminary conductive pattern 12. Is done. Accordingly, the preliminary conductive pattern 12 changes to a conductive pattern 12a having a recess formed thereon. In one embodiment, the recess of the conductive pattern 12a has inclined sidewalls. The lower electrode contact 18 includes a side extended portion located in the recess of the conductive pattern 12a. For example, the lower electrode contact 18 has an arrow-shaped cross section with the tip cut off.

  As described above, the conductive pattern 12a has a recess by the heat treatment process, and the lower electrode contact 18 has an expanded lower portion. Accordingly, the contact region between the conductive pattern 12a and the lower electrode contact 18 increases.

  In the present embodiment, a plasma treatment process, a rapid thermal treatment (RTA) process, or the like can be applied as the heat treatment process. For example, the conductive pattern 12a and the lower electrode contact 18 are formed by a plasma processing process or a rapid thermal process. In contrast, the conductive pattern 12a and the lower electrode contact 18 may be formed by performing a plasma treatment process and a rapid heat treatment process one after another.

  According to the present embodiment, the thickness of the lower electrode contact 18 is changed by adjusting the process conditions of the heat treatment process. For example, the lower electrode contact 18 has a thickness of about 200 to about 600 mm from the upper surface of the conductive pattern 12a.

  In the present embodiment, the conductive pattern 12a includes tungsten, and the lower electrode contact 18 includes tungsten oxide. When heat treatment is performed in an oxygen atmosphere, tungsten is oxidized and the tungsten oxide expands rapidly. Tungsten oxide has a substantially higher resistance than tungsten and has etching resistance to an etching solution used in a wet etching process. In order to ensure appropriate resistance and etching resistance of the conductive pattern 12a and / or the lower electrode contact 18, the conductive pattern 12a and the lower electrode contact 18 include tungsten and tungsten oxide, respectively.

  In the present embodiment, the heat treatment process may include a rapid heat treatment process performed at a temperature of about 400 ° C. to about 600 ° C. for about 1 minute to about 10 minutes in an oxygen atmosphere. In contrast, the heat treatment process may include a plasma treatment process performed for about 1 minute to about 10 minutes while applying a power of about 20 W to about 100 W in an oxygen atmosphere.

  In this embodiment, the lower electrode contact 18 formed in the first opening 16 can have a high resistance without performing a film deposition process and a film etching process. Therefore, the lower electrode contact 18 can be obtained through a simple process.

Referring to FIG. 41, a spacer forming film is formed on the second insulating film pattern 14, the side wall of the first opening 16, and the lower electrode contact 18. The spacer forming film is formed using the same nitride as the silicon nitride. The spacer forming film reduces the width of the first opening 16.
Accordingly, the width of the first opening 16 can be reduced to a predetermined value by adjusting the thickness of the spacer forming film.

  The spacer forming film is partially etched to form the spacer 20 on the side wall of the first opening 16. The spacer 20 is formed through an anisotropic etching process. The spacer 20 has substantially the same or similar width as the spacer forming film.

  Referring to FIG. 42, the phase change material film 22 is formed on the lower electrode contact 18 and the spacer 20 while filling the first opening 16. The phase change material film 22 is formed using, for example, a chalcogenide compound germanium-antimony-tellurium (GST) alloy.

  The contact area between the phase change material film 22 and the lower electrode contact 18 is reduced by the spacer 20. Accordingly, an area where a phase transition occurs due to Joule heating of the phase change material film 22 is reduced, and a reset current of the phase change memory device can be reduced. Since the lower electrode contact 18 is located in the first opening 16, the aspect ratio of the first opening 16 in which the phase change material film 22 is formed is reduced. Therefore, the phase change material film 22 can be easily formed in the first opening 16 without generating voids or seams in the phase change material film 22.

  Referring to FIG. 43, an upper electrode film is formed on the phase change material film 22. The upper electrode film may include a metal nitride. For example, the upper electrode film is formed using titanium nitride.

  The phase change structure 22 a and the upper electrode 24 are formed by patterning the upper electrode film and the phase change material film 22. The phase change structure 22a is formed on the lower electrode contact 18 and the first insulating film 14, and the upper electrode 24 is disposed on the phase change structure 22a. Here, the lower part of the phase change structure 22 a is located in the first opening 16, and the upper part of the phase change structure 22 a protrudes on the second insulating film pattern 14.

  Referring to FIG. 44, a third insulating film is formed on the second insulating film pattern 14 while covering the upper electrode 24 and the phase change structure 22a. The third insulating film is partially etched to form a second opening 28 that partially exposes the upper electrode 24. Along with this, the third insulating film changes to the third insulating film pattern 26 including the second opening 28. For example, the second opening 28 has a contact hole shape.

  A conductive material is deposited in the second opening 28 to form the upper electrode contact 30 on the upper electrode 24. The upper electrode contact 30 includes a metal. For example, the upper electrode contact 30 includes tungsten. As a result, a phase change memory device having a lower electrode contact 18 made of a metal oxide is provided.

  FIG. 45 is a cross-sectional view of a phase change memory device according to a ninth embodiment of the present invention. The phase change memory device shown in FIG. 45 has substantially the same or similar configuration as the phase change memory device described with reference to FIG. 38 except that no spacer is disposed on the sidewall of the first opening. Have

  Referring to FIG. 45, the lower electrode contact 18 is provided in the first opening 16 formed through the second insulating film pattern 14 disposed on the substrate 8. The lower electrode contact 18 partially fills the first opening 16 and includes a metal oxide.

  A phase change structure 22 a is disposed on the lower electrode contact 18. The phase change structure 22a completely fills the first opening 16. The upper surface of the phase change structure 22 a is positioned substantially higher than the upper surface of the second insulating film pattern 14. An upper electrode 24 is disposed on the phase change structure 22a.

  A third insulating film pattern 26 covering the upper electrode 24 is formed on the second insulating film pattern 14, and the upper electrode 24 and the phase change structure 22 a are covered with the third insulating film pattern 26.

  A second opening 28 is formed through the third insulating film pattern 26. The second opening 28 partially exposes the upper electrode 24. An upper electrode contact 30 is disposed in the second opening 28.

  In the phase change memory device shown in FIG. 45, since the spacer is not provided on the side wall of the phase change structure 22a, the contact area between the lower electrode contact 18 and the phase change structure 22a is the first opening 16. Is substantially the same as the width of. Therefore, the phase change memory device shown in FIG. 45 can be manufactured through a simpler process while ensuring the required characteristics.

  FIG. 46 is a cross-sectional view for illustrating the method of manufacturing the phase change memory device shown in FIG.

  In the method of manufacturing the phase change memory device shown in FIG. 46, substantially the same or similar processes as those described with reference to FIGS. 39 and 40 are performed, and the results substantially similar to the results described with reference to FIG. Results in the same structure.

  Referring to FIG. 46, the phase change material film 22 is formed on the second insulating film pattern 14 while filling the first opening 16 in which the lower electrode 18 is formed. In this case, no spacer is formed on the side wall of the first opening 16.

  Thereafter, a phase change memory having substantially the same configuration as the phase change memory device shown in FIG. 38, performing substantially the same or substantially similar steps as those described with reference to FIGS. Manufacture equipment.

  FIG. 47 is a cross-sectional view of a phase change memory device according to a tenth embodiment of the present invention. The phase change memory device shown in FIG. 47 has a configuration in which unit cells are arranged in an array structure.

  Referring to FIG. 47, the first insulating film pattern 102 is disposed on the substrate 100 in which the element isolation region 100a and the active region are defined. A first opening 104 is formed through the first insulating film pattern 102. The first opening 104 is selectively formed in a portion of the substrate 100 where a unit cell of the phase change memory device is formed. The first opening 104 is repeatedly disposed on the substrate 100. Each first opening 104 has a contact hole shape. The first opening 104 exposes a predetermined portion of the substrate 100.

  A PN diode 106 is disposed in each of the first openings 104. In one embodiment, a vertical PN diode 106 is disposed in the first opening 104. For example, each of the vertical PN diodes 106 includes polysilicon. The PN diode 106 partially fills the first opening 104. For example, the PN diode 106 fills the lower portion of the first opening 104.

  A metal silicide pattern 108 is disposed on the PN diode 106. The metal silicide pattern 108 reduces the contact resistance between the PN diode 106 and the conductive pattern 110a. For example, the metal silicide pattern 108 includes cobalt silicide, titanium silicide, nickel silicide, tungsten silicide, and the like.

  The conductive pattern 110 a is disposed on the metal silicide pattern 108. Each of the conductive patterns 110a includes a metal having a small resistance. Here, the upper surface of the conductive pattern 110 a is positioned substantially lower than the upper end of the first opening 104. In addition, each of the conductive patterns 110a has an upper portion including a round recess. That is, the upper edge of the conductive pattern 110a is positioned higher than the center of the upper portion of the conductive pattern 110a. In one embodiment, each conductive pattern 110a includes tungsten.

A second insulating film pattern 112 is disposed on the conductive pattern 110 a and the first insulating film pattern 102. For example, the second insulating film pattern 112 includes an oxide such as silicon oxide.
A second opening 114 is formed through the second insulating film pattern 112. Each second opening 114 partially exposes the conductive pattern 110a. Each second opening 114 has a contact hole shape. In one embodiment, the second opening 114 has a width smaller than the width of the conductive pattern 110a.

  A lower electrode contact 116 is disposed on the conductive pattern 110 a in the second opening 114. Each of the lower electrode contacts 116 includes a metal oxide generated from the conductive pattern 110a. The lower electrode contact 116 partially fills the second opening 114. For example, the lower electrode contact 116 fills the lower portion of the second opening 114.

  The lower electrode contact 116 is formed by oxidizing the conductive pattern 110a. For example, a metal oxide grows from the conductive pattern 110 a above the second opening 114, and a lower electrode contact 116 containing the metal oxide is formed in the second opening 114. The conductive pattern 110a has a round-shaped recess on the top thereof, and the lower electrode contact 116 includes a round-shaped protrusion corresponding to the round-shaped recess of the conductive pattern 110a. In one embodiment, the conductive patterns 110a each include tungsten, and the lower electrode contacts 116 each include tungsten oxide.

  A spacer 118 is disposed on the side wall of the second opening 114. The spacer 118 contacts the lower electrode contact 116. Due to the formation of the spacer 118, the second opening 114 has a reduced width. Each of the spacers 118 includes nitride or oxynitride. For example, the spacers 118 each include silicon nitride or silicon oxynitride.

  The phase change structure 120 is disposed on the lower electrode contact 116 while filling the second opening 114. The phase change structure 120 may include a chalcogenide compound. The upper surface of the phase change structure 120 that fills the second opening 114 and the upper surface of the second insulating layer pattern 112 are located on substantially the same plane. Accordingly, the phase change structure 120 does not protrude on the second insulating layer pattern 112.

  Upper electrode 122 is disposed on phase change structure 120. Each of the upper electrodes 122 may include the same metal oxide as the titanium nitride. Upper electrode 122 has a substantially larger width than phase change structure 120.

  A third insulating film pattern 124 is disposed on the second insulating film pattern 112. The third insulating film 124 covers the upper electrode 122 and the phase change structure 120. A third opening 126 is formed in the third insulating film pattern 124 to partially expose the upper electrode 122. An upper electrode contact 128 is disposed in the third opening 126. For example, each upper electrode contact 128 is made of the same metal as tungsten. The phase change memory device shown in FIG. 47 has an array structure in which unit cells are arranged in the first and second openings 104 and 114.

  48 to 51 are cross-sectional views for explaining a method of manufacturing the phase change memory device shown in FIG.

  Referring to FIG. 48, an element isolation process such as a shallow trench isolation process is performed on the substrate 100 to define an element isolation region 100 a and an active region in the substrate 100. An oxide film is formed on the substrate 100 including the active region and the element isolation region 100a. The oxide film is changed to the first insulating film pattern 102 while forming the first opening 104 by partially etching the oxide film. The first opening 104 is formed in the substrate 100 where the unit cell of the phase change memory device is formed.

  A PN diode 106 is formed in the first opening 104 of the first insulating film pattern 102. Each of the PN diodes 106 includes polysilicon and has a vertical structure.

  In the process of forming the PN diode 106, after forming a polysilicon film in the first opening 104, the polysilicon film is partially etched to form the PN diode 106. Therefore, the PN diode 106 is located in the first opening 104. In one embodiment, the lower portion of the polysilicon film in the first opening 104 is doped with N-type impurities, and the upper portion of the polysilicon film is implanted with P-type impurities.

  A metal silicide pattern 108 is formed on the PN diode 106. The metal silicide pattern 108 is formed by forming a metal film on the PN diode 106 and then heat-treating the PN diode 106 and the metal film. That is, the metal silicide pattern 108 is formed by a reaction between the metal in the metal film and the silicon in the PN diode 106. The metal silicide pattern 108 includes cobalt silicide, titanium silicide, tungsten silicide, nickel silicide, and the like.

  A preliminary conductive pattern 110 is formed on the metal silicide pattern 108. The preliminary conductive pattern 110 fills the first opening 104. Each of the preliminary conductive patterns 110 includes a metal. For example, the preliminary conductive pattern 110 includes tungsten.

  In the process of forming the preliminary conductive pattern 110, a metal film is formed on the metal silicide pattern 108 and the first insulating film pattern 102 while filling the first opening 104, and then the metal film is exposed until the first insulating film pattern 102 is exposed. Then, the preliminary conductive pattern 110 is formed by partially removing. In this case, the metal film is partially removed by a chemical mechanical polishing process.

  Referring to FIG. 49, a second insulating film is formed on the first insulating film pattern 102 while covering the preliminary conductive pattern 110. The second insulating film is formed using the same oxide as silicon oxide.

The second insulating film is changed to the second insulating film pattern 112 while the second insulating film is partially etched to form the second opening 114 that partially exposes the preliminary conductive pattern 110.
The second opening 114 can be formed using a photolithography process. In one embodiment, the first opening 114 has a width substantially smaller than the width of the preliminary conductive pattern 110.

  Referring to FIG. 50, the preliminary conductive pattern 110 exposed through the second opening 114 is heat-treated in an oxygen atmosphere to form the lower electrode contact 116 on the preliminary conductive pattern 110. The lower electrode contact 116 partially fills the second opening 114.

  In the process of forming the lower electrode contact 116, the upper part of the preliminary conductive pattern 110 reacts with oxygen, and accordingly, the metal oxide grows upward in the first opening 114. At this time, the preliminary conductive pattern 110 changes to the conductive pattern 110a. The lower electrode contact 116 has a substantially higher resistance than the conductive pattern 110a. When the preliminary conductive pattern 110 includes tungsten, the lower electrode contact 116 includes tungsten oxide.

  When the preliminary conductive pattern 110 is heat-treated, the conductive pattern 110a has an upper portion where a round-shaped recess is formed. Will have. The conductive pattern 110a and the lower electrode contact 116 are obtained through a process that is substantially the same as or substantially similar to the process described with reference to FIG.

  Referring to FIG. 51, a spacer 118 is formed on the side wall of the second opening 114. A phase change material film is formed on the lower electrode contact 116 while filling the second opening 114. For example, the phase change material film is formed using a chalcogenide compound such as germanium-antimony-tellurium (GST).

  The phase change material 120 is partially removed until the second insulating layer pattern 112 is exposed, thereby forming the phase change structure 120 in the second opening 114. The upper surface of the phase change structure 120 and the upper surface of the second insulating layer pattern 112 are substantially in the same plane.

  As shown in FIG. 47, the upper electrode film is formed on the phase change structure 120 and the second insulating film pattern 112. The upper electrode film is patterned to form the upper electrode 122 on the phase change structure 120.

  A third insulating film covering the upper electrode 122 is formed on the second insulating film pattern 112. The third insulating film is partially etched to form a third opening 126 that partially exposes the upper electrode 122. Along with this, the third insulating film changes to the third insulating film pattern 124. For example, each of the third openings 126 has a contact hole shape.

  A conductive material is deposited in the third opening 126 to form an upper electrode contact 128 in the third opening 126 on the upper electrode 122. Each upper electrode contact 128 is formed using a metal. For example, the upper electrode contact 128 includes tungsten.

  FIG. 52 is a perspective view of a phase change memory device according to an eleventh embodiment of the present invention. The phase change memory device shown in FIG. 52 is the same as the phase change memory described with reference to FIG. 47 except for the vertically stacked structure including the lower electrode contact, the phase change structure, and the second insulating film pattern. It has a configuration that is substantially the same as or substantially similar to the device.

  Referring to FIG. 52, the vertical stacked structure including the lower electrode contact 116 and the phase change structure 120 has a rectangular upper surface, and is repeatedly disposed in a dash shape on the substrate 100. Accordingly, a large number of vertically stacked structures are provided within a very small area of the substrate 100.

  The second insulating layer pattern 112 surrounds the lower electrode contact 116 and the phase change structure 120. The second insulating film pattern 112 includes, for example, the same nitride as silicon nitride.

  In the present embodiment, since the second opening 160 has a sufficiently small width, no spacer is provided on the sidewalls of the lower electrode contact 116 and the second opening 160 as shown in FIG. Alternatively, additional spacers may be located on the sidewalls of the lower electrode contact 116 and the second opening 160.

  53 to 58 are perspective views for explaining a method of manufacturing the phase change memory device shown in FIG.

  Referring to FIG. 53, substantially the same or substantially similar process as described with reference to FIG. 51 is performed to form the result shown in FIG.

  A first additional insulating film is formed on the preliminary conductive pattern 110 and the first insulating film pattern 102. The first additional insulating film is formed using the same nitride as the silicon nitride.

  A first trench 150 exposing the preliminary conductive pattern 110 is formed by partially etching the first additional insulating film. Each first trench 150 extends along the first direction. Accordingly, the first additional insulating film pattern 152 including the first trench 150 is formed on the first insulating film pattern 102.

  A second additional insulating film is formed on the preliminary conductive pattern 110 in the first trench 150. The second additional insulating layer is formed using a material having a high etching selectivity with respect to the first additional insulating layer pattern 152. For example, the second additional insulating film is formed using the same oxide as silicon oxide.

  The second additional insulating film is partially removed until the first additional insulating film pattern 152 is exposed. The second additional insulating film is removed using a chemical mechanical polishing process and / or an etchback process. Accordingly, a second additional insulating film pattern 154 is formed between the first additional insulating film patterns 152. The second additional insulating film patterns 154 extend along a second direction substantially orthogonal to the first direction.

  A mask pattern is formed on the first and second additional insulating film patterns 152 and 154. The mask pattern extends in a second direction substantially perpendicular to the first direction. Each mask pattern has a line shape. In addition, the mask pattern is arranged so as to repeat regularly on the first and second additional insulating film patterns 152 and 154.

  Referring to FIG. 54, using the mask pattern as an etching mask, the first and second additional insulating film patterns 152 and 154 are partially etched until the first insulating film pattern 102 is exposed. A second trench 156 is formed on the first insulating film pattern 102 by partially etching the first and second additional insulating film patterns 152 and 154. At this time, the preliminary conductive pattern 110 is not exposed. The first and second additional insulating film patterns 152 and 154 each have a circular or polygonal column shape.

  Referring to FIG. 55, a third additional insulating layer is formed on the first and second additional insulating layer patterns 152 and 154. For example, the third additional insulating film is formed using a nitride such as silicon nitride. A third additional insulating film pattern 158 is formed in the second trench 156 by partially removing the third additional insulating film until the first and second additional insulating film patterns 152 and 154 are exposed.

  When the third additional insulating layer pattern 158 is formed, the first and third additional insulating layer patterns 152 and 158 including substantially the same material may include different materials from the first and third additional insulating layer patterns 152 and 158. 2 Arranged so as to enclose the additional insulating film pattern 154.

  Referring to FIG. 56, the second additional insulating layer pattern 154 is selectively removed up to the first insulating layer pattern 102 to form a second opening 160 between the first and second additional insulating layer patterns 152 and 158. To do. The second opening 160 partially exposes the preliminary conductive pattern 110. As a result, the second insulating film pattern 112 is provided on the first insulating film pattern 102. The second insulating film pattern 112 includes a first additional insulating film pattern 152, a third additional insulating film pattern 158, and a second opening 160. Each second opening 160 has a contact hole shape. The second opening 160 extends along the first direction and the second direction.

  In the present embodiment, the second additional insulating layer pattern 154 is removed through a wet etching process or a dry etching process. In order to prevent the first and third additional insulating layer patterns 152 and 158 from being damaged by etching during the dry etching process, it is advantageous to remove the second additional insulating layer pattern 154 through a wet etching process. is there.

  According to the present embodiment, the second opening 160 may have a substantially smaller width than a conventional contact hole formed by a photolithography process. The second opening 160 has a dash structure on a plane.

  Referring to FIG. 57, the preliminary conductive pattern 110 is partially oxidized through an oxidation process, and a metal oxide generated from the preliminary conductive pattern 110 is grown upward in the second opening 160. Accordingly, the lower electrode contact 116 is formed in the second opening 160. In the oxidation process, the preliminary conductive pattern 110 is changed to a conductive pattern 110a having an upper portion in which a round-shaped recess is formed, and the lower electrode contact 116 includes a round-shaped protrusion corresponding to the recess. The conductive pattern 110a and the lower electrode contact 116 may be obtained through a process that is substantially the same as or substantially similar to the process described with reference to FIG.

  Referring to FIG. 58, after the phase change material film filling the second opening 160 is formed on the lower electrode contact 116, the phase change material film is partially removed until the second insulating film pattern 112 is exposed. Accordingly, the phase change structure 120 that fills the second opening 160 is formed on the lower electrode contact 116.

  In the present embodiment, since the second opening 160 has a relatively small width, no spacer is formed on the side wall of the second opening 160. However, an additional spacer may be formed on the sidewall of the second opening 160 so as to adjust the width of the second opening 160.

  As shown in FIG. 52, the upper electrode 122 is formed on the phase change structure 120. Further, a third insulating film 124 having a third opening is formed on the second insulating film pattern 112 while covering the upper electrode 122. An upper electrode contact 128 is formed on the upper electrode 122 in the third opening. Therefore, a phase change memory device having a high degree of integration can be manufactured.

  FIG. 59 is a cross-sectional view of a phase change memory device according to a twelfth embodiment of the present invention.

  Referring to FIG. 59, a first insulating layer 192 and a PN diode 194 are provided on the substrate 190. A second insulating film pattern 202 is formed on the first insulating film 192. The second insulating film pattern 202 includes a first opening 204 that exposes the PN diode 194. The second insulating film pattern 202 includes the same nitride as silicon nitride and oxynitride such as silicon oxide.

  A first lower electrode contact 206 a that partially fills the first opening 204 is disposed on the PN diode 194. The first lower electrode contact 206a includes a metal. A second lower electrode contact 208a filling the first opening 204 is disposed on the first lower electrode contact 206a. The second lower electrode contact 208a includes a metal oxide generated from the metal included in the first lower electrode contact 206a. In one embodiment, the first lower electrode contact 206a includes tungsten and the second lower electrode contact 208a includes tungsten oxide.

  A phase change structure 210 is disposed on the second insulating layer pattern 202 and the second lower electrode contact 208a. An upper electrode 212 is disposed on the phase change structure 210. For example, the upper electrode 212 includes metal nitride.

  A third insulating film pattern 214 covering the upper electrode 212 is disposed on the second insulating film pattern 202. A second opening is provided through the third insulating layer pattern 214. The second opening partly exposes the upper electrode 212. An upper electrode contact 216 is disposed on the upper electrode 212 in the second opening.

  According to the present embodiment, since the second lower electrode contact 208a contacting the phase change structure 210 has a high resistance, the phase change memory device may have improved operation characteristics.

  60 to 62 are cross-sectional views for describing a method of manufacturing the phase change memory device shown in FIG.

  Referring to FIG. 60, a first insulating film 192 and a PN diode 194 are formed on a substrate 190. The PN diode 194 is formed on the substrate 190 through the first insulating film 192. After the second insulating film is formed on the first insulating film 192, the second insulating film is partially removed. Accordingly, a second insulating film pattern 202 including a first opening 204 is formed on the first insulating film 192. The first opening 204 exposes the PN diode 194.

  A first metal film is formed on the PN diode 194 and the second insulating film pattern 202 while filling the first opening 204. The first metal film is formed using tungsten. A preliminary lower electrode contact 206 is formed in the first opening 204 by partially removing the first metal film. The upper surface of the preliminary lower electrode contact 206 is positioned substantially lower than the upper end of the first opening 204. Alternatively, the upper surface of the preliminary lower electrode contact 206 and the upper end of the first opening 204 may be substantially on the same plane.

  Referring to FIG. 61, the preliminary lower electrode contact 206 is heat-treated in an atmosphere containing oxygen, and the preliminary lower electrode contact 206a is changed to the first lower electrode contact 206a while changing the preliminary lower electrode contact 206 to the first lower electrode contact 206a. An electrode contact 208 is formed. The preliminary second lower electrode contact 208 includes a metal oxide generated from the metal included in the preliminary lower electrode contact 206.

  In this embodiment, since the preliminary lower electrode contact 206 is oxidized to form the second preliminary lower electrode contact 208, the first lower electrode contact 206 a is an upper portion that is substantially lower than the upper end of the first opening 204. Having a surface. The second preliminary lower electrode contact 208 protrudes from the first opening 204 through an oxidation process performed on the preliminary lower electrode contact 206. That is, since the upper surface of the preliminary lower electrode contact 206 is positioned substantially at the same level as or substantially lower than the upper end of the first opening 204, the metal oxide is isotropically isolated from the preliminary lower electrode contact 206. The preliminary second lower electrode contact 208 protrudes from the first opening 204 by growing.

  Referring to FIG. 62, the preliminary second lower electrode contact 208 is partially removed until the second insulating film pattern 202 is exposed, whereby the second lower electrode contact 208a filling the first opening 204 is formed into the first lower electrode. Formed on contact 206a.

  As shown in FIG. 59, a phase change material film and an upper electrode film are formed on the second insulating film pattern 202 while covering the second lower electrode contact 208a. The phase change material layer and the upper electrode layer are patterned to form the phase change structure 210 and the upper electrode 212 on the second lower electrode contact 208 a and the second insulating layer pattern 202.

  A third insulating film pattern 214 including a second opening is formed on the second insulating film pattern 202 while covering the upper electrode 212. The second opening partly exposes the upper electrode 212. An upper electrode contact 216 is formed on the upper electrode 212 while filling the second opening.

  FIG. 63 is a schematic diagram of a broadband communication system including a mobile communication terminal network capable of broadband mobile communication according to an embodiment of the present invention.

  Referring to FIG. 63, the broadband mobile communication system 250 includes a sensor module 252, a position tracking system (GPS) 254, and a mobile communication terminal 256. The broadband mobile communication system 250 can communicate with the data server 258 and the base station 260. The mobile communication terminal 256 is required to have a high communication speed and high data reliability because the data server 258 and the base station 260 receive / transmit a lot of data.

  The mobile communication terminal 256 may include at least one of the resistive memory devices according to the embodiment of the present invention. The resistive memory device may include a magnetic memory device and / or a phase change memory device according to the above-described embodiments. The resistive memory device according to the embodiment of the present invention can be applied to the mobile communication terminal 256 because it can secure a low driving voltage, a high-speed operation, and a high data reliability.

  The resistive memory device according to the present embodiment can be used in various electrical and electronic devices such as a USB memory, an MP3 player, a digital camera, and a memory card.

<Evaluation of contact structure resistance>
The resistance memory device according to the present embodiment can ensure high Joule heating efficiency because the lower electrode contact has a large resistance. The following samples and comparative samples were manufactured to compare the resistance of the lower electrode contact structure included in the resistive memory device.

<Sample 1 to Sample 8>
FIG. 64 is a cross-sectional view showing contact structures according to Sample 1 to Sample 8.

  As shown in FIG. 64, an insulating film pattern 302 including an opening was formed on the substrate 300. A contact plug 308 was formed in the opening. The contact plug 308 includes a tungsten pattern 304 and a tungsten oxide pattern 306. The tungsten oxide pattern 306 was obtained by heat-treating the tungsten pattern 304 in a rapid heat treatment process.

  The diameters of the contact plugs 308 of samples 1 to 8 are different from each other. In the following Table 1, the diameters of the contact plugs 308 according to the samples 1 to 8 are described. The contact plugs 308 according to samples 1 to 8 have substantially the same configuration as the conductive structure of the above-described resistance memory device.

<Comparative Sample 11 to Comparative Sample 18>
FIG. 65 is a cross-sectional view showing a contact structure according to Comparative Sample 11 to Comparative Sample 18.

  As shown in FIG. 65, an insulating film pattern 302 including an opening was formed on the substrate 300. A contact plug 312 was formed in the opening. The contact plug 312 includes a tungsten pattern 304 and a tungsten nitride pattern 310 formed on the tungsten pattern 304. The diameters of the contact plugs 312 in the comparative samples 11 to 18 are different from each other. Table 1 below shows the diameters of the contact plugs 312 according to the comparative samples 11 to 18.

<Comparative Sample 21 to Comparative Sample 28>
66 is a cross-sectional view showing a contact structure according to Comparative Sample 21 to Comparative Sample 28. FIG.

  As shown in FIG. 66, an insulating film pattern 302 including an opening was formed on the substrate 300. A contact plug 314 containing tungsten was formed in the opening. The diameters of the contact plugs 314 of the comparative samples 21 to 28 are different from each other. Table 1 below shows the diameters of the contact plugs 314 of the comparative samples 21 to 28.

  FIG. 67 is a graph showing the resistance of the contact structure according to each sample and the comparative sample. In FIG. 67, reference numeral 320 indicates the resistance measured in Samples 1 to 8, reference numeral 322 indicates the resistance measured in Comparative Sample 11 through Comparative Sample 18, and reference numeral 324 indicates Comparative Sample 21 through Comparative Sample 28. Indicates the measured resistance.

  As shown in FIG. 67, the resistance of the contact structures having the same diameter was measured using the sample and the comparative sample. As a result, the resistance of the contact structures of Sample 1 to Sample 8 was relatively high. For example, the resistance of the contact structure according to the comparative sample 11 and the comparative sample 21 having a diameter of about 130 nm is about 1,380Ω and about 1,310Ω, respectively, while the resistance of the contact structure according to the sample 1 having a diameter of about 130 nm. Is about 1,480Ω, which is about 100Ω higher than that of the comparative sample 11.

  As described above, the contact structure of the resistive memory device according to the present embodiment includes a tungsten pattern and a tungsten oxide pattern, and thus has a high resistance. Since the Joule heating efficiency is improved by the contact structure, the resistance memory device can ensure improved characteristics.

<Electrical characteristic evaluation of resistance memory device>
<Sample 9>
A phase change memory device was manufactured through substantially the same process as described with reference to FIGS. The phase change memory device according to the sample 9 has substantially the same structure as the phase change memory device described with reference to FIG. The conductive pattern of the phase change memory device was formed using tungsten. The lower electrode contact formed on the conductive pattern in the first opening was formed by heat-treating the conductive pattern in a rapid heat treatment process. The lower electrode contact includes tungsten oxide. The upper electrode was formed using titanium nitride, and the upper electrode contact was formed using tungsten.

<Comparative sample 9>
In order to compare the electrical characteristics with the phase change memory device of Sample 9, another phase change memory device was manufactured.

  FIG. 68 is a cross-sectional view showing a phase change memory device according to comparative sample 9.

  Referring to FIG. 68, the phase change memory device according to the comparative sample 9 includes a conductive pattern 12 a, a phase change structure 52 a, an upper electrode 24, and an upper electrode contact 30 formed on the substrate 8. The phase change memory device additionally includes a first insulating film 10, a second insulating film pattern 14, and a third insulating film pattern 26. A PN diode 11 is buried in the first insulating film 10. The phase change memory device according to the comparative sample 9 does not include the lower electrode contact, and the phase change structure 52a is disposed on the conductive pattern 12a made of tungsten. That is, the conductive pattern 12a is used as the lower electrode. The phase change memory device includes a spacer 50a disposed on the sidewall of the opening in which the phase change structure 52a is formed.

  A plurality of phase change memory devices having the configuration of Sample 9 and Comparative Sample 9 were manufactured. The resistance in the set state and the reset state of the phase change memory device and the current in the reset state were measured.

  Table 2 below shows the set resistance, reset resistance, and reset current of the phase change memory device.

  As shown in Table 2, the set resistance of the phase change memory device according to sample 9 is lower than the set resistance of the phase change memory device according to comparison sample 9, and the resistance distribution of the phase change memory device according to sample 9 is also the phase change due to comparison sample 9. It was smaller than the resistance spread of the memory device. The reset resistance of the phase change memory device according to Sample 9 was greater than the reset resistance of the phase change memory device according to Comparative Sample 9. Further, in the phase change memory device according to the comparative sample 9, since the phase change structure has a deeper depth in the opening, voids and scenes are often generated in the phase change structure. A malfunction occurred, and its electrical characteristics deteriorated.

  On the other hand, the phase change memory device according to sample 9 not only has a low resistance distribution, but also has a large resistance difference between the set state and the reset state, so that data can be easily distinguished. It has been found that the required electrical characteristics are fully satisfied.

  As mentioned above, although embodiment of this invention was described in detail, referring drawings, this invention is not limited to the above-mentioned embodiment, In the range which does not deviate from the technical scope of this invention, it changes variously. It is possible to implement.

8, 50, 64, 90, 100, 190, 300, 400, 490 Substrate 8a, 406, 490a Impurity region 10, 192, 408, 494 First insulating film 11, 106, 194, 500 P-N diode 12, 110 Preliminary conductive pattern 12a, 110a, 412 Conductive pattern 14, 112, 202 Second insulating film pattern 16, 104, 204, 496 First opening 18, 116 Lower electrode contact 20, 50a, 62, 80, 118, 455, 552 Spacer 22 Phase change material film 22a, 52a, 120, 210, 514, 514a, 514b, 556 Phase change structure 24, 122, 212, 438, 516 Upper electrode 26, 124, 214 Third insulating film pattern 28, 114, 160, 505 Second opening 30, 128, 216, 52 Upper electrode contact 52, 66, 94 Insulating film 54, 68, 96, 415, 453, 553 Opening 56, 70 Barrier metal film 56a, 70a, 506 Barrier metal film pattern 58, 59, 72 Metal film 58a, 72a, 92 530 Preliminary metal pattern 58b, 59a, 72b, 82, 92a, 418, 450, 502a, 508, 530a, 612, 652 Metal pattern 60, 76, 86, 98, 98a, 420, 454, 456, 510, 510a, 536, 536a, 554, 616, 656 Metal oxide pattern 74 Fill film 74a, 84, 614, 654 Fill film pattern 100a Element isolation region 102, 162 First insulation film pattern 108 Metal silicide pattern 126, 513, 515, 532 First 3 openings 150 1st train 152 First additional insulating film pattern 154 Second additional insulating film pattern 156 Second trench 158 Third additional insulating film pattern 206 Preliminary lower electrode contact 206a First lower electrode contact 208 Preliminary second lower electrode contact 208a Second lower electrode contact 250 Broadband mobile communication system 252 Sensor module 254 Position tracking system (GPS)
256 Mobile communication terminal 258 Data server 260 Base station 302, 534 Insulating film pattern 304 Tungsten pattern 306 Tungsten oxide pattern 308, 312, 314, 410 Contact plug 310 Tungsten nitride pattern 402 Gate insulating film 404 Gate electrodes 414, 452, 504, 550 Second insulating film 416, 610, 650 First barrier metal film pattern 422, 434a, 512, 512a, 518a, 618, 660 Third insulating film 424 Second barrier metal film pattern 426 Free film pattern 428 Tunnel oxide film Pattern 430a, 430b, 430c First fixed film pattern 432 Second fixed film pattern 434, 436, 518 Fourth insulating film 436 Fifth insulating film 440 Bit line 492 Element isolation film pattern Turn 500a First polysilicon film pattern 500b Second polysilicon film pattern 520 Contact hole

Claims (14)

  1. An insulating film disposed on the substrate and including an opening exposing the conductive region of the substrate;
    A barrier film pattern disposed in the opening;
    A conductive pattern disposed on the barrier film pattern and including an oxidized portion extending from the inside of the opening to the outside and a non-oxidized portion located in the opening. And comprising
    The width of the conductive pattern is determined by the thickness of the barrier film pattern ,
    The oxidized portion of the conductive pattern contacts one of a phase change material layer of a phase change memory device (PRAM) and a free layer pattern of a magnetic memory device (MRAM). A semiconductor device characterized by the above.
  2.   The semiconductor device according to claim 1, wherein a width of the conductive pattern is smaller than a width of the opening.
  3.   2. The semiconductor device according to claim 1, wherein the oxidized portion extending to the outside of the opening is thicker than the unoxidized portion in the opening.
  4.   2. The semiconductor device according to claim 1, wherein the width of the oxidized portion is the same as the width of the non-oxidized portion.
  5.   2. The semiconductor device according to claim 1, wherein a width of the oxidized portion is larger than a width of the non-oxidized portion.
  6.   The method of claim 1, further comprising a filling layer pattern disposed in the opening, wherein the conductive pattern is disposed between the barrier film pattern and the filling film pattern. Semiconductor device.
  7.   The semiconductor device according to claim 6, wherein the conductive pattern has a cylindrical shape.
  8.   The semiconductor device according to claim 1, wherein the conductive pattern includes tungsten.
  9.   The semiconductor device according to claim 1, wherein the barrier film pattern includes at least one of titanium and titanium nitride.
  10.   The semiconductor device according to claim 1, wherein the barrier film pattern includes at least one of a nitride and an oxynitride.
  11. The semiconductor device according to claim 1 , wherein the barrier film pattern is in contact with a PN diode disposed under the barrier film pattern.
  12. The semiconductor device according to claim 1 , wherein the barrier film pattern is in electrical contact with a MOS transistor disposed under the barrier film pattern.
  13.   2. The semiconductor device according to claim 1, wherein a size of a cross-sectional area of the oxidized portion on a plane is smaller than a size of a cross-sectional area of the opening on the plane.
  14. 2. The semiconductor device according to claim 1 , wherein the size of the cross-sectional area of the oxidized portion on a plane is determined by the size of the cross-sectional area of the barrier film pattern.
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