DE69031903T2 - Verfahren zum Herstellen von Zwischenschicht-Kontakten - Google Patents

Verfahren zum Herstellen von Zwischenschicht-Kontakten

Info

Publication number
DE69031903T2
DE69031903T2 DE69031903T DE69031903T DE69031903T2 DE 69031903 T2 DE69031903 T2 DE 69031903T2 DE 69031903 T DE69031903 T DE 69031903T DE 69031903 T DE69031903 T DE 69031903T DE 69031903 T2 DE69031903 T2 DE 69031903T2
Authority
DE
Germany
Prior art keywords
interlayer contacts
making interlayer
making
contacts
interlayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69031903T
Other languages
English (en)
Other versions
DE69031903D1 (de
Inventor
Fusen E Chen
Fu-Tai Liou
Timothy Edward Turner
Che-Chia Wei
Yih-Shung Lin
Girish Anant Dixit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69031903D1 publication Critical patent/DE69031903D1/de
Publication of DE69031903T2 publication Critical patent/DE69031903T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE69031903T 1989-11-30 1990-08-30 Verfahren zum Herstellen von Zwischenschicht-Kontakten Expired - Fee Related DE69031903T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US44389889A 1989-11-30 1989-11-30

Publications (2)

Publication Number Publication Date
DE69031903D1 DE69031903D1 (de) 1998-02-12
DE69031903T2 true DE69031903T2 (de) 1998-04-16

Family

ID=23762627

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69031903T Expired - Fee Related DE69031903T2 (de) 1989-11-30 1990-08-30 Verfahren zum Herstellen von Zwischenschicht-Kontakten

Country Status (5)

Country Link
US (1) US6617242B1 (de)
EP (1) EP0430403B1 (de)
JP (1) JPH03220751A (de)
KR (1) KR910008794A (de)
DE (1) DE69031903T2 (de)

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US6271137B1 (en) 1989-11-30 2001-08-07 Stmicroelectronics, Inc. Method of producing an aluminum stacked contact/via for multilayer
DE69031903T2 (de) 1989-11-30 1998-04-16 Sgs Thomson Microelectronics Verfahren zum Herstellen von Zwischenschicht-Kontakten
US6242811B1 (en) 1989-11-30 2001-06-05 Stmicroelectronics, Inc. Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature
US5472912A (en) * 1989-11-30 1995-12-05 Sgs-Thomson Microelectronics, Inc. Method of making an integrated circuit structure by using a non-conductive plug
US5658828A (en) 1989-11-30 1997-08-19 Sgs-Thomson Microelectronics, Inc. Method for forming an aluminum contact through an insulating layer
KR960001601B1 (ko) * 1992-01-23 1996-02-02 삼성전자주식회사 반도체 장치의 접촉구 매몰방법 및 구조
US6287963B1 (en) 1990-11-05 2001-09-11 Stmicroelectronics, Inc. Method for forming a metal contact
KR920010620A (ko) * 1990-11-30 1992-06-26 원본미기재 다층 상호접속선을 위한 알루미늄 적층 접점/통로 형성방법
DE69225082T2 (de) * 1991-02-12 1998-08-20 Matsushita Electronics Corp Halbleiter-Vorrichtung mit Verdrahtung der verbesserten Zuverlässigkeit und Verfahren zu ihner Herstellung
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JP2937613B2 (ja) * 1991-07-16 1999-08-23 日本電気株式会社 薄膜配線およびその製造方法
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US6033534A (en) * 1992-05-20 2000-03-07 Siemens Aktiengesellschaft Method for producing an Al-containing layer with a planar surface on a substrate having hole structures with a high aspect ratio in the surface
DE69323513T2 (de) * 1992-07-27 1999-08-12 St Microelectronics Inc Planaxer Kontakt mit einer Lücke
EP0594300B1 (de) * 1992-09-22 1998-07-29 STMicroelectronics, Inc. Methode zur Herstellung eines Metallkontaktes
KR970001883B1 (ko) * 1992-12-30 1997-02-18 삼성전자 주식회사 반도체장치 및 그 제조방법
US5356836A (en) * 1993-08-19 1994-10-18 Industrial Technology Research Institute Aluminum plug process
US5594278A (en) * 1994-04-22 1997-01-14 Nippon Steel Corporation Semiconductor device having a via hole with an aspect ratio of not less than four, and interconnections therein
DE19515564B4 (de) * 1994-04-28 2008-07-03 Denso Corp., Kariya Elektrode für ein Halbleiterbauelement und Verfahren zur Herstellung derselben
EP0690503A1 (de) * 1994-05-31 1996-01-03 Advanced Micro Devices, Inc. Verbesserte Struktur einer Verbindungsleitung und Verfahren dafür
US5856707A (en) * 1995-09-11 1999-01-05 Stmicroelectronics, Inc. Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in which they are formed
US6307267B1 (en) 1997-12-26 2001-10-23 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof
JP2001060590A (ja) 1999-08-20 2001-03-06 Denso Corp 半導体装置の電気配線及びその製造方法
US6617689B1 (en) * 2000-08-31 2003-09-09 Micron Technology, Inc. Metal line and method of suppressing void formation therein
US20070120199A1 (en) * 2005-11-30 2007-05-31 Advanced Micro Devices, Inc. Low resistivity compound refractory metal silicides with high temperature stability
TWI680535B (zh) * 2016-06-14 2019-12-21 美商應用材料股份有限公司 金屬及含金屬化合物之氧化體積膨脹
US10763207B2 (en) 2017-11-21 2020-09-01 Samsung Electronics Co., Ltd. Interconnects having long grains and methods of manufacturing the same

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Also Published As

Publication number Publication date
US6617242B1 (en) 2003-09-09
EP0430403B1 (de) 1998-01-07
DE69031903D1 (de) 1998-02-12
JPH03220751A (ja) 1991-09-27
EP0430403A2 (de) 1991-06-05
EP0430403A3 (en) 1992-03-11
KR910008794A (ko) 1991-05-31

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee