CN1697127A - 制造半导体器件的方法 - Google Patents

制造半导体器件的方法 Download PDF

Info

Publication number
CN1697127A
CN1697127A CNA200510068821XA CN200510068821A CN1697127A CN 1697127 A CN1697127 A CN 1697127A CN A200510068821X A CNA200510068821X A CN A200510068821XA CN 200510068821 A CN200510068821 A CN 200510068821A CN 1697127 A CN1697127 A CN 1697127A
Authority
CN
China
Prior art keywords
semiconductor device
forms
wiring layer
resin
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA200510068821XA
Other languages
English (en)
Inventor
山野孝治
仓嶋信幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Co Ltd
Original Assignee
Shinko Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Co Ltd filed Critical Shinko Electric Co Ltd
Publication of CN1697127A publication Critical patent/CN1697127A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种用于制造半导体器件的方法，所述半导体器件具有用于在半导体元件和外部连接端子之间布线的堆积层。该方法包括如下步骤：在基片上形成再布线层；将基片放置在可伸展划片带上；将放置在划片带上的基片划开；通过伸展划片带在相邻半导体以及之间形成间隙；通过在半导体以及间隙上形成堆积层来形成半导体器件连续体；以及通过对半导体器件连续体进行划片而形成半导体器件。

Description

制造半导体器件的方法
技术领域
本发明涉及制造半导体器件的方法，具体地涉及制造具有用于在半导体元件和外部连接端子之间连线的堆积(build-up)层的半导体器件的方法。
背景技术
近些年来，作为用于多媒体器件的关键技术的LSI(大规模集成电路)技术朝着提高数据传输速度和容量的方向稳步发展。随着LSI技术的发展，用于LSI和电子设备之间接口的高密度安装技术也已经被开发出来。在半导体封装中，CSP(芯片尺寸封装)的尺寸基本等于芯片尺寸，它可以提供高密度安装的能力。
尽管有多种CSP，但是大多数CSP被配置为在半导体元件和用于外部连接的连接端子(例如，焊料块(solder bump))之间具有插入物。这是因为半导体元件上的焊盘(pad)是通过晶片处理而高精度地形成的，而外部连接端子只需要精确到足以满足基于布线规则的节距，从而不具有与焊盘的精度一样高的精度。因此，在半导体元件和外部连接端子之间提供插入物。
树脂基片已经被用作插入物，并且已经使用引线接合方法或者倒装片接合方法来将半导体元件连接到插入物。但是，由于半导体元件和树脂基片之间有精度差，随着半导体元件的密度的增加和它们的尺寸的减小，越来越难以树脂基片上形成对应于半导体元件的焊盘的电极。结果，树脂基片变得不太适合作为CSP的插入物。
考虑到这些情况，日本专利特开第2002-16173号公报公开了一种半导体器件制造方法，其中通过堆积法形成CSP的插入物。根据该半导体器件制造方法，通过划片(dicing)处理将晶片分割为半导体元件。每个半导体元件被安装在形成在基片上的凹陷部分上。接着，在其上形成具有层间导电部分的绝缘层。另外，通过堆积处理形成电连接到层间导电部分的堆积层。
但是，在如上所述将晶片分割为半导体元件并将半导体元件安装在基片上之后执行堆积处理的情况下，如果半导体元件具有高密度和高精度，则半导体元件需要精确地定位于基片上。因此，半导体元件的定位变得困难。并且，当在堆积处理之前半导体元件被分离时，对分离的半导体元件的操纵也很麻烦。
这些问题的一种解决方法可以是基于晶片级工艺的半导体器件制造方法，该方法被设计来在晶片级，即在分割在晶片上提供的半导体元件之前，形成堆积层。但是，根据该基于晶片级工艺的方法，堆积层的面积与通过划片而被分离的半导体元件的面积尺寸相同，并且不能形成比这更宽的堆积层。这导致堆积层的布线方案的灵活性较低。
发明内容
本发明的总的目的是提供一种用于解决至少一个上述问题的制造半导体器件的方法。本发明的具体目的是提供一种容易地制造允许高度灵活的布线方案的高精度的半导体器件的方法。
为了达到前述和其他的目的，本发明提供了一种制造半导体器件的方法，该方法包括第一布线层形成步骤，该步骤在其上形成多个半导体元件的半导体基片的元件形成表面上形成第一布线层；第一分割步骤，该步骤将半导体基片放置在可伸展的基膜上，其中所述元件形成表面朝上，并且执行第一分割处理，在所述第一分割处理中，被放置在基膜上的半导体基片被分割，使得多个半导体元件彼此分离；间隙形成步骤，该步骤在所述第一分割步骤之后通过伸展所述可伸展基膜，在相邻半导体元件之间形成间隙；半导体元件封装步骤，该步骤利用树脂封装分离的多个半导体元件并且填充相邻的半导体元件之间的间隙；通孔形成步骤，该步骤在树脂上对应于所述第一布线层的位置形成通孔；半导体器件连续体形成步骤，该步骤通过在所述树脂的表面上形成第二布线层，使得第二布线层通过通孔连接到第一布线层，来形成半导体器件连续体；以及第二分割步骤，该步骤执行第二分割处理，在所述第二分割处理中，通过在所述间隙内进行切割而将半导体器件连续体分割为多个半导体器件。
根据本发明，在半导体基片被分割后，可伸展基膜被伸展以在相邻的半导体元件之间形成间隙。在此之后形成第二布线层，使得第二布线层的区域延伸在间隙以及半导体元件之上。因此，提高了第二布线层的设计灵活性。另外，第二布线层的区域的尺寸可容忍半导体元件的尺寸变化。也就是，即使半导体元件的尺寸发生变化，也可以通过调整间隙的长度而容易地适应所述尺寸变化。
在制造半导体器件的该方法中，优选地，可伸展基膜包括可伸展划片带。
利用划片带，可以在第一分割处理之后连续地执行间隙形成步骤，这简化了半导体器件的制造工艺，并且提高了制造效率。
在制造半导体器件的该方法中，优选地，第一布线层形成步骤包括在半导体基片上形成暴露的电极和由含金属的树脂构成的绝缘膜；通过无电镀在电极和绝缘膜上形成种子层；通过使用种子层作为供电层进行电镀来形成金属膜图形；以及通过使用金属膜图形作为掩模，蚀刻所述种子层来形成第一布线层。
利用上述步骤消除了对于用于形成种子层的昂贵的溅射装置的需求。因此，不需要特别的设备投资，在普通的生产线上低成本地形成了种子层。这样，可以显著降低半导体器件的制造成本。
在制造半导体器件的该方法中，优选地，含金属的树脂包括包含钯的环氧树脂。
在制造半导体器件的该方法中，优选地，半导体器件连续体制造步骤包括通过堆积法在树脂上形成具有多个层的第二布线层的步骤，其中在所述树脂上形成通孔。
根据该方法，在封装多个半导体元件并填充间隙的树脂上形成第二布线层。因此，第二布线层能够提供高精度和高可靠性。
在制造半导体器件的该方法中，优选地，在第一和第二分割处理中使用划片工艺。
如果如上所述的第一分割处理和第二分割处理都使用划片工艺，则可以用一个划片装置执行这两个分割处理。结果，降低了分割处理所需的成本。
优选地，制造半导体器件的该方法还包括在第一分割步骤之前研磨半导体基片的与元件形成表面相对的背表面的背面研磨步骤。
研磨半导体基片的背表面降低了半导体基片的厚度，从而能够容易地并有效地切割和分离半导体基片。
附图说明
图1图示了根据作为本发明的实施例的制造半导体器件的方法的第一布线层形成步骤；
图2图示了根据作为本发明的实施例的制造半导体器件的方法的第一布线层形成步骤；
图3图示了根据作为本发明的实施例的制造半导体器件的方法的第一布线层形成步骤；
图4图示了根据作为本发明的实施例的制造半导体器件的方法的第一布线层形成步骤；
图5图示了根据作为本发明的实施例的制造半导体器件的方法的第一布线层形成步骤；
图6图示了根据作为本发明的实施例的制造半导体器件的方法的第一布线层形成步骤；
图7图示了根据作为本发明的实施例的制造半导体器件的方法的背面研磨步骤；
图8图示了根据作为本发明的实施例的制造半导体器件的方法的第一分割步骤；
图9图示了根据作为本发明的实施例的制造半导体器件的方法的第一分割步骤；
图10图示了根据作为本发明的实施例的制造半导体器件的方法的间隙形成步骤；
图11图示了根据作为本发明的实施例的制造半导体器件的方法的半导体器件连续体形成步骤；
图12图示了根据作为本发明的实施例的制造半导体器件的方法的半导体器件连续体形成步骤；
图13图示了根据作为本发明的实施例的制造半导体器件的方法的半导体器件连续体形成步骤；
图14图示了根据作为本发明的实施例的制造半导体器件的方法的半导体器件连续体形成步骤；
图15图示了根据作为本发明的实施例的制造半导体器件的方法的半导体器件连续体形成步骤；
图16图示了根据作为本发明的实施例的制造半导体器件的方法的第二分割步骤；以及
图17图示了根据作为本发明的实施例的制造半导体器件的方法的半导体器件第二分割步骤。
具体实施方式
下面参照附图描述了本发明的优选实施例。
图1到17逐个步骤地图示了作为本发明的实施例的制造半导体器件的方法。根据本发明的制造半导体器件的方法，使用图1中所示的半导体基片1。
半导体基片1是具有多个预先形成的半导体元件的硅晶片(以下称为晶片1)。每个半导体元件用作例如存储器。在元件区域的外侧形成铝电极3。在除了形成铝电极3的区域以外的晶片1的正面(元件形成表面)上形成钝化膜。钝化膜2可以包括氮化硅(SiN)膜。
尽管在晶片1上形成了多个半导体元件，但是，为了简化描述，图1到7只图示了在晶片1上形成的多个半导体元件中的一个半导体元件。基于同样的原因，图8到17图示了在晶片1上形成的多个半导体元件中的相邻的两个半导体元件。
参照图2，通过无电镀在晶片1上的铝电极3上形成镍膜4。这样，在铝电极3上的钝化膜2中的孔被镍膜4覆盖。
接着，在钝化膜2的上表面上涂覆光敏树脂涂层(或者粘附一层膜)以形成具有例如10到20μm的厚度的绝缘膜5。绝缘膜5可以由含金属的树脂或者硅氧烷基树脂(siloxane-based resin)构成。
含金属的树脂可以包括这样的树脂：其中分散了用作镀覆催化剂(plating catalyst)的金属粒子。或者可以使用用作镀覆催化剂的金属的化合物(例如，氯化物、氢氧化物、氧化物)。用作催化剂的金属包括钯和铂等。尤其是，钯化合物，例如氯化钯和硫酸钯是优选的。
所述树脂最好是环氧树脂和聚酰亚胺树脂，但是并不限于此。即，含金属的树脂可以是任何含有某种镀覆催化剂的树脂。含金属的树脂的优选的例子包括光敏环氧基树脂，该光敏环氧基树脂包含用作无电镀中的催化剂的大约1％的钯(Pd)并且具有4GPa的杨氏模量。
硅氧烷基树脂的优选的例子包括负光敏材料(硅氧烷含量：10-70％)，该负光敏材料基于由高耐热芳香族树脂成分构成的硅氧烷树脂，并且具有90到500MPa的杨氏模量。
参照图3，通过使用光刻方法的进行曝光和显影在铝电极3上的绝缘膜5上形成开口5a。接着，通过加热硬化绝缘膜5。从而镍膜4通过开口5a被暴露。
接着，如图4所示，通过无电镀在绝缘膜5和镍膜4上形成具有1μm的厚度的种子层(seed layer)6。在本实施例中的种子层6由镍(Ni)构成。当在如上所述的由含金属的树脂构成的绝缘膜5上形成种子层6时，在含金属的树脂的表面上钯被暴露。随着执行以这样的绝缘膜5作为底层的无电镀，可靠地形成镀层，从而可以获得具有期望的膜特性的种子层6。
在该实施例中，如上解释的，因为在晶片1上形成了包含用作无电镀催化剂的钯的绝缘膜(含金属的树脂)5，所以可以通过无电镀形成种子层6。因此，不需要使用昂贵的溅射装置来形成种子层6，由此显著地降低了制造成本。
虽然在本实施例中通过无电镀在绝缘膜5上形成了种子层6，但是用于形成种子层6的方法不限于此。例如，可以通过溅射法在钝化膜2和镍膜4上形成由铜(Cu)组成的种子层。
在形成种子层6之后，在晶片1上形成具有对应于再布线(rewiring)层7(下面将讨论)的开口的抗蚀剂(未示出)。接着，通过使用种子层6作为供电层进行电镀，在抗蚀剂的开口中形成5到20μm厚度的由铜构成的再布线层7。
当抗蚀剂被移除时，除了形成再布线层7的区域以外的种子层6被暴露(图5)。这样被再布线层7部分遮蔽的种子层6接着被蚀刻，使得除了形成再布线层7的区域以外的绝缘膜5被暴露(图6)。利用所有这些处理，再布线层7完成。参照图1到6描述的处理对应于在权利要求中所说的“第一布线层形成步骤”。
在再布线层7完成之后，在形成再布线层7的晶片1的表面上粘合背面研磨(backgrinding)带。晶片1被装载在研磨机上以进行背面研磨处理。利用背面研磨处理，如图7所示，晶片1的厚度W被减小到例如大约20到50μm。这样，在晶片级进行半导体元件的背面研磨，并且半导体元件的厚度被有效地降低。
当背面研磨处理完成时，如图8所示，晶片1被粘合到划片带10上。划片带10由环形的划片框架9支撑。随着粘合材料被布置在划片带10的正面上，晶片1的背面被粘合到划片带10上。一旦晶片1被粘合到划片带10上，背面研磨带8就被移开。
划片带10是可伸展的，它用作在权利要求中所说的可伸展的基膜。因此，如下面所讨论的，划片带10随着张力的施加而伸展。
在移开背面研磨带8之后，晶片1被装载在划片装置上以在预定的划片位置11被划片刀片12划开(或者分割)(图9)。这样晶片1被分割为多个彼此分离的半导体元件(下面将分离的半导体元件称为半导体元件1A)。
尽管在划片处理期间对晶片1施加了相对较大的力，但是，半导体元件1A被粘合在划片带10上，而没有脱离划片带10。在本实施例中，晶片1在划片处理之前经历背面研磨处理，所以要被切割的晶片1的厚度减小了。因此，划片处理能够被有效地执行。参照图7到9描述的处理对应于在权利要求中所说的“第一分割步骤”。即使在划片处理期间，在划片带10的厚度方向，划片带10的一部分被划片刀片12切割，这也不是问题，这是因为在下面的步骤中划片带10被伸展。
当划片处理完成时，在划片带10的如图10的箭头所指示的向外径向方向上，对划片带10施加张力。因为如前所述划片带10是可伸展的，所以划片带10由于张力而伸展。张力被设置为均匀地施加到划片带10上。
当这样通过在划片带10的向外径向上施加张力而使划片带10伸展时，在相邻的半导体元件1A之间形成间隙13。可以在划片带10的可伸展的范围内按照需要设置间隙13的长度L。可以基于半导体元件1A的尺寸和堆积层16的形成面积来确定间隙13的长度L(下面将讨论)。
在本实施例中，使用划片带10形成间隙13。划片带10执行本来的功能，即，在划片处理中支撑半导体元件1A，并且在伸展处理中用于形成间隙13。
因此，利用划片带10，可以连续地进行划片处理和形成间隙12的处理，从而提高半导体器件的制造效率并且简化了制造工艺。参照图7到10描述的处理对应于在权利要求中所说的“间隙形成步骤”。
如上所述在相邻的半导体元件1A之间形成间隙13之后，在划片带10上形成用于封装半导体元件1A的密封树脂14。通过真空层压处理在划片带10上形成密封树脂14。
例如，由环氧基树脂构成的树脂片被放置在其上布置了半导体元件1A的划片带上，并且进行真空处理。这样，树脂片被紧密地配合(或者层叠)在半导体元件1A上，使得如图11所示形成封装半导体元件1A和间隙13的密封树脂14。在形成密封树脂14之后，可以使密封树脂14的上表面变得光滑和平坦。可以通过诸如施加液体树脂和灌封(potting)法等其他方法形成密封树脂14。
此后，在密封树脂14上的对应于保留再布线层7的位置的预定位置形成通孔15。虽然在本实施例中通过激光加工形成通孔15，但是可以替代地使用蚀刻来形成通孔15。图12示出了在密封树脂14上的预定位置形成的通孔15。
接着，在密封树脂14上形成堆积层16。密封树脂14用作用于形成堆积层16的基板。可以通过包括添加法和减去法的任何公知的堆积法来形成堆积层16。
在本实施例中，使用基于半添加法的堆积法来形成堆积层16。具体而言，通过重复如下处理形成具有预定数目的叠层(laminationlayer)的堆积层16：所述处理包括在密封树脂14上形成铜图形；堆积层的层叠；用于形成通孔的激光束钻孔；无电铜镀(electrolesscopper plating)；以及无电铜镀层的蚀刻。通过堆积法形成的布线层(第二布线层)在填充间隙13的密封树脂14上延伸。
在形成堆积层16之后，在堆积层16上形成阻焊剂17。可以通过印刷法形成阻焊剂17。在使用印刷法的情况下，可以同时形成阻焊剂17和开口18。
在对应于下面将详细讨论的焊料块(外部连接端子)21的位置上形成开口18。在堆积层16的顶层上形成的铜图案通过开口18被暴露。
在形成具有开口18的阻焊剂17之后，在各个开口18内形成阻挡金属部分19。本实施例的阻挡金属部分19是镍(Ni)和金(Au)的叠层。可以通过例如无电镀方法形成阻挡金属部分19。
在形成阻挡金属部分19之后，根据需要在阻焊剂17的上表面上形成诸如芯片电容器20之类的无源元件芯片。图14图示了以上述方式形成了阻焊剂17、阻挡金属部分19和芯片电容器20的状态。
接着，在各个阻挡金属部分19上形成了焊料块21。可以通过在相应的阻挡金属部分19上提供焊球并且将焊球回流到阻挡金属部分19上来形成各个焊料块21。图15图示了形成焊料块21的状态。
利用这些处理，形成了具有联生的多个半导体元件1A的半导体器件连续体25，其中在所述半导体元件1A上形成了堆积层16。参照图11到15描述的处理对应于权利要求中所说的“半导体器件连续体形成步骤”。
在如上所述形成半导体器件连续体25之后，半导体器件连续体25沿着划片线22被划片刀片12划开(或者分割)为半导体器件30。划片线22位于间隙13内。更具体地说，划片线22位于间隙13上的第二布线层的外表面上。这样，半导体器件连续体25被分割为半导体器件30。接着，从划片带10拾取半导体器件30。这样，制造了如图17所示的半导体器件30。
在本实施例中进行了两次划片处理。因为在两次处理中使用同一划片装置，所以不需要对每个处理使用不同的划片装置。从而，低成本地进行划片处理。参照图16和17描述的处理对应于权利要求中所说的“第二分割步骤”。
下面更具体地描述在制造半导体器件30的处理中涉及的在图7到10中图示的在半导体元件1A之间形成间隙13的处理和在图11到15中图示的形成半导体器件连续体25的处理。
根据该实施例，如上所述，通过划片处理(第一分割步骤)将晶片1分割为半导体元件1A，通过伸展划片带10在相邻的半导体元件1A之间形成间隙13。当在半导体元件1A上形成堆积层16时，在划片带10上形成的填充了间隙13的密封树脂14用作形成堆积层16的基板。
下面在不伸展划片带10而形成堆积层16的情况和如在本实施例中那样在伸展划片带10和形成间隙13之后形成堆积层16的情况之间进行一些比较。
在不伸展划片带10而形成堆积层16的情况下，形成堆积层16的区域和形成半导体元件1A的区域(在图15中由箭头S1指出的区域)尺寸相同。即，堆积层16的面积不能比形成半导体元件1A的区域的面积更大。
相反，在本实施例中，通过伸展划片带10在相邻的半导体元件1A之间形成间隙13。接着在作为封装半导体元件1A和填充间隙13的基板的密封树脂14上形成堆积层16。即，在密封树脂14上形成堆积层16，所述密封树脂14不仅形成在半导体元件1A上，还形成在间隙13上，这使得形成堆积层16的区域(在图15中由箭头S2指出的区域)变得大于形成半导体元件1A的区域S1。
因此，堆积层16可以被更灵活地设计并应用于具有高密度的半导体元件1A。即使当晶片1的半导体元件1A的尺寸改变时，也可以通过调整间隙13的长度来容易地适应尺寸的改变。换句话说，形成堆积层16的区域的尺寸的设置可以与半导体元件1A无关，使得可以容易地接受对半导体元件1A的修改。
在半导体元件1A之间形成的间隙13填充有密封树脂14，并且使得密封树脂14的上表面光滑并且平坦。因此，尽管堆积层16在间隙13上延伸，也可以保证堆积层16的精度和可靠性。另外，因为半导体元件1A的侧面被覆盖了密封树脂14，所以半导体器件30的物理强度得以提高。
本申请基于2004年5月11日向日本专利局提交的日本在先申请No.2004-141527，该申请的全部内容在此引为参考。

Claims (7)

1.一种制造半导体器件的方法，包括：
第一布线层形成步骤，该步骤在其上形成多个半导体元件的半导体基片的元件形成表面上形成第一布线层；
第一分割步骤，该步骤将所述半导体基片放置在可伸展的基膜上，其中所述元件形成表面朝上，并且执行第一分割处理，在所述第一分割处理中，被放置在所述基膜上的所述半导体基片被分割，使得所述多个半导体元件彼此分离；
间隙形成步骤，该步骤在所述第一分割步骤之后通过伸展所述可伸展基膜，在相邻的半导体元件之间形成间隙；
半导体元件封装步骤，该步骤利用树脂封装所述分离的多个半导体元件并且填充所述相邻的半导体元件之间的所述间隙；
通孔形成步骤，该步骤在所述树脂上对应于所述第一布线层的位置形成通孔；
半导体器件连续体形成步骤，该步骤通过在所述树脂的表面上形成第二布线层，使得所述第二布线层通过所述通孔连接到所述第一布线层，来形成半导体器件连续体；以及
第二分割步骤，该步骤执行第二分割处理，在所述第二分割处理中，通过在所述间隙内进行切割而将所述半导体器件连续体分割为多个所述半导体器件。
2.如权利要求1所述的制造半导体器件的方法，其中所述可伸展基膜包括可伸展划片带。
3.如权利要求1所述的制造半导体器件的方法，其中所述第一布线层形成步骤包括：
在所述半导体基片上形成暴露的电极和由含金属的树脂构成的绝缘膜；
通过无电镀在所述电极和所述绝缘膜上形成种子层；
通过使用所述种子层作为供电层进行电镀，形成金属膜图形；以及
通过使用所述金属膜图形作为掩模，蚀刻所述种子层来形成所述第一布线层。
4.如权利要求3所述的制造半导体器件的方法，其中所述含金属的树脂包括包含钯的环氧树脂。
5.如权利要求1所述的制造半导体器件的方法，其中所述半导体器件连续体制造步骤包括：
通过堆积法在所述树脂上形成具有多个层的所述第二布线层，其中在所述树脂上形成有所述通孔。
6.如权利要求1所述的制造半导体器件的方法，其中使用划片工艺进行所述第一和第二分割处理。
7.如权利要求1所述的制造半导体器件的方法，还包括：
在所述第一分割步骤之前研磨所述半导体基片的与所述元件形成表面相对的背面的背面研磨步骤。
CNA200510068821XA 2004-05-11 2005-05-11 制造半导体器件的方法 Pending CN1697127A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004141527A JP2005322858A (ja) 2004-05-11 2004-05-11 半導体装置の製造方法
JP2004141527 2004-05-11

Publications (1)

Publication Number Publication Date
CN1697127A true CN1697127A (zh) 2005-11-16

Family

ID=35309971

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA200510068821XA Pending CN1697127A (zh) 2004-05-11 2005-05-11 制造半导体器件的方法

Country Status (5)

Country Link
US (1) US7105423B2 (zh)
JP (1) JP2005322858A (zh)
KR (1) KR20060045975A (zh)
CN (1) CN1697127A (zh)
TW (1) TW200605283A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102714188A (zh) * 2010-01-22 2012-10-03 三洋电机株式会社 半导体模块的制造方法
CN103311216A (zh) * 2013-05-20 2013-09-18 江苏长电科技股份有限公司 新型高密度多层线路芯片倒装封装结构及制作方法
CN105374783A (zh) * 2014-08-15 2016-03-02 美国博通公司 半导体边界保护密封剂

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8217381B2 (en) 2004-06-04 2012-07-10 The Board Of Trustees Of The University Of Illinois Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics
US7521292B2 (en) 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US7799699B2 (en) 2004-06-04 2010-09-21 The Board Of Trustees Of The University Of Illinois Printable semiconductor structures and related methods of making and assembling
JP2008502151A (ja) 2004-06-04 2008-01-24 ザ ボード オブ トラスティーズ オブ ザ ユニヴァーシティー オブ イリノイ 印刷可能半導体素子を製造して組み立てるための方法及びデバイス
US7456104B2 (en) * 2005-05-31 2008-11-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7820495B2 (en) * 2005-06-30 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
CN105826345B (zh) 2007-01-17 2018-07-31 伊利诺伊大学评议会 通过基于印刷的组装制造的光学系统
US7687318B2 (en) 2007-05-04 2010-03-30 Stats Chippac, Ltd. Extended redistribution layers bumped wafer
JP2009099661A (ja) * 2007-10-15 2009-05-07 Shinko Electric Ind Co Ltd 配線基板の個片化方法およびパッケージ用基板
US8389862B2 (en) 2008-10-07 2013-03-05 Mc10, Inc. Extremely stretchable electronics
US8886334B2 (en) 2008-10-07 2014-11-11 Mc10, Inc. Systems, methods, and devices using stretchable or flexible electronics for medical applications
US8097926B2 (en) 2008-10-07 2012-01-17 Mc10, Inc. Systems, methods, and devices having stretchable integrated circuitry for sensing and delivering therapy
US8372726B2 (en) 2008-10-07 2013-02-12 Mc10, Inc. Methods and applications of non-planar imaging arrays
EP2349440B1 (en) 2008-10-07 2019-08-21 Mc10, Inc. Catheter balloon having stretchable integrated circuitry and sensor array
WO2010058646A1 (ja) * 2008-11-21 2010-05-27 インターナショナル・ビジネス・マシーンズ・コーポレーション 半導体パッケージおよびその製造方法
EP2430652B1 (en) 2009-05-12 2019-11-20 The Board of Trustees of the University of Illionis Printed assemblies of ultrathin, microscale inorganic light emitting diodes for deformable and semitransparent displays
FI20095557A0 (fi) 2009-05-19 2009-05-19 Imbera Electronics Oy Valmistusmenetelmä ja elektroniikkamoduuli, joka tarjoaa uusia mahdollisuuksia johdevedoille
US9723122B2 (en) 2009-10-01 2017-08-01 Mc10, Inc. Protective cases with integrated electronics
US10918298B2 (en) 2009-12-16 2021-02-16 The Board Of Trustees Of The University Of Illinois High-speed, high-resolution electrophysiology in-vivo using conformal electronics
US9936574B2 (en) 2009-12-16 2018-04-03 The Board Of Trustees Of The University Of Illinois Waterproof stretchable optoelectronics
US10441185B2 (en) 2009-12-16 2019-10-15 The Board Of Trustees Of The University Of Illinois Flexible and stretchable electronic systems for epidermal electronics
EP2974673B1 (en) 2010-03-17 2017-03-22 The Board of Trustees of the University of Illionis Implantable biomedical devices on bioresorbable substrates
US9442285B2 (en) 2011-01-14 2016-09-13 The Board Of Trustees Of The University Of Illinois Optical component array having adjustable curvature
JP5658582B2 (ja) * 2011-01-31 2015-01-28 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
WO2012158709A1 (en) 2011-05-16 2012-11-22 The Board Of Trustees Of The University Of Illinois Thermally managed led arrays assembled by printing
US9159635B2 (en) 2011-05-27 2015-10-13 Mc10, Inc. Flexible electronic structure
EP2713863B1 (en) 2011-06-03 2020-01-15 The Board of Trustees of the University of Illionis Conformable actively multiplexed high-density surface electrode array for brain interfacing
US9691873B2 (en) 2011-12-01 2017-06-27 The Board Of Trustees Of The University Of Illinois Transient devices designed to undergo programmable transformations
US8685761B2 (en) * 2012-02-02 2014-04-01 Harris Corporation Method for making a redistributed electronic device using a transferrable redistribution layer
US9554484B2 (en) 2012-03-30 2017-01-24 The Board Of Trustees Of The University Of Illinois Appendage mountable electronic devices conformable to surfaces
US9171794B2 (en) 2012-10-09 2015-10-27 Mc10, Inc. Embedding thin chips in polymer
TWI553807B (zh) * 2014-06-13 2016-10-11 思鷺科技股份有限公司 封裝結構
EP3304130B1 (en) 2015-06-01 2021-10-06 The Board of Trustees of the University of Illinois Alternative approach to uv sensing
US10677647B2 (en) 2015-06-01 2020-06-09 The Board Of Trustees Of The University Of Illinois Miniaturized electronic systems with wireless power and near-field communication capabilities
US10925543B2 (en) 2015-11-11 2021-02-23 The Board Of Trustees Of The University Of Illinois Bioresorbable silicon electronics for transient implants
WO2018003312A1 (ja) * 2016-06-30 2018-01-04 リンテック株式会社 半導体加工用シート
US10121765B2 (en) 2017-03-01 2018-11-06 Semiconductor Components Industries, Llc Semiconductor device and method of forming WLCSP
US10665522B2 (en) * 2017-12-22 2020-05-26 Intel IP Corporation Package including an integrated routing layer and a molded routing layer
JP7229641B2 (ja) * 2019-04-25 2023-02-28 株式会社ディスコ パッケージデバイスチップの製造方法
CN114270508A (zh) * 2019-08-23 2022-04-01 塞尔法雷公司 拉伸受体衬底以调节组件的布置的方法及系统

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3816253B2 (ja) * 1999-01-19 2006-08-30 富士通株式会社 半導体装置の製造方法
JP2002016173A (ja) 2000-06-30 2002-01-18 Mitsubishi Electric Corp 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102714188A (zh) * 2010-01-22 2012-10-03 三洋电机株式会社 半导体模块的制造方法
CN103311216A (zh) * 2013-05-20 2013-09-18 江苏长电科技股份有限公司 新型高密度多层线路芯片倒装封装结构及制作方法
CN103311216B (zh) * 2013-05-20 2016-02-24 江苏长电科技股份有限公司 高密度多层线路芯片倒装封装结构及制作方法
CN105374783A (zh) * 2014-08-15 2016-03-02 美国博通公司 半导体边界保护密封剂

Also Published As

Publication number Publication date
US7105423B2 (en) 2006-09-12
JP2005322858A (ja) 2005-11-17
US20050255686A1 (en) 2005-11-17
KR20060045975A (ko) 2006-05-17
TW200605283A (en) 2006-02-01

Similar Documents

Publication Publication Date Title
CN1697127A (zh) 制造半导体器件的方法
US11631611B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
US10128211B2 (en) Thin fan-out multi-chip stacked package structure and manufacturing method thereof
TWI710072B (zh) 半導體裝置封裝體及其製造方法
US10163872B2 (en) Semiconductor packages and methods of forming the same
US9418969B2 (en) Packaged semiconductor devices and packaging methods
US7459729B2 (en) Semiconductor image device package with die receiving through-hole and method of the same
US8178964B2 (en) Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same
US7102238B2 (en) Semiconductor device and manufacturing method thereof
CN1298034C (zh) 半导体封装及其制造方法
US11749651B2 (en) Semiconductor package and manufacturing method thereof
KR20080077934A (ko) 축소된 구조를 갖는 멀티칩 패키지 및 그 형성 방법
US20080083980A1 (en) Cmos image sensor chip scale package with die receiving through-hole and method of the same
US20080211075A1 (en) Image sensor chip scale package having inter-adhesion with gap and method of the same
US20080157358A1 (en) Wafer level package with die receiving through-hole and method of the same
JP2008252087A (ja) 半導体装置パッケージ構造及びその方法
US11205636B2 (en) Semiconductor package and method of manufacturing the same
TWI777358B (zh) 半導體封裝
CN1825590A (zh) 半导体器件及其制造方法
CN1992151A (zh) 半导体装置的制造方法
US11469173B2 (en) Method of manufacturing a semiconductor structure
CN1301542C (zh) 半导体晶片、半导体装置及其制造方法、电路基板及电子机器
CN1790686A (zh) 具有密封膜的芯片尺寸的半导体装置及其制造方法
CN1630072A (zh) 半导体装置及其制造方法、电路基板和电子机器
TWI789608B (zh) 電子封裝件之製法及其承載結構

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication