TWI789608B - 電子封裝件之製法及其承載結構 - Google Patents

電子封裝件之製法及其承載結構 Download PDF

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TWI789608B
TWI789608B TW109124584A TW109124584A TWI789608B TW I789608 B TWI789608 B TW I789608B TW 109124584 A TW109124584 A TW 109124584A TW 109124584 A TW109124584 A TW 109124584A TW I789608 B TWI789608 B TW I789608B
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layer
manufacturing
electronic component
circuit structure
electronic
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TW109124584A
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TW202204515A (zh
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林澤源
廖俊明
陳宏棋
鄭有志
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矽品精密工業股份有限公司
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Priority to TW109124584A priority Critical patent/TWI789608B/zh
Priority to CN202010757602.7A priority patent/CN113964073A/zh
Priority to US17/209,494 priority patent/US11545385B2/en
Publication of TW202204515A publication Critical patent/TW202204515A/zh
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    • B32B17/00—Layered products essentially comprising sheet glass, or glass, slag, or like fibres
    • B32B17/06—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material
    • B32B17/10—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material of synthetic resin
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Abstract

一種承載結構，係包括強化層，其包含聚矽氧烷、二氧化矽及PET薄膜，其中，該聚矽氧烷係於該強化層中佔有5~30重量百分比，該二氧化矽係於該強化層中佔有1~20重量百分比，該聚對苯二甲酸乙二酯薄膜係於該強化層中佔有60~85重量百分比，俾藉由該承載結構進行半導體封裝製程，以提升製程之可靠度。

Description

電子封裝件之製法及其承載結構
本發明係關於一種半導體封裝製程，特別是關於一種電子封裝件之製法及其承載結構。
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係發展出扇出(fan out)型封裝的技術。
如圖1所示，習知半導體封裝件之製法係於一承載件10上進行半導體元件15之封裝製程。具體地，於該承載件10之黏著層100上形成線路結構11，再以覆晶方式藉由導電凸塊16及底膠17配置複數半導體元件15於該線路結構11(包含介電層110與線路部111)上，使該半導體元件15之電極墊150藉由該導電凸塊16電性連接該線路部111。之後，以壓合(lamination)方式形成一包覆層18於該線路結構11上，以包覆該半導體元件15。
於後續製程中，可移除該承載件10及黏著層100，再進行植球及切單製程。
惟，習知半導體封裝件1之製法中，於高溫狀態(如覆晶作業)下，該承載件10與黏著層100之間會發生剝離(peeling)現象，導致後續製程無法順利進行。
因此，如何克服上述習知技術的問題，實已成為目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明係提供一種承載結構，係包括強化層，其包含聚矽氧烷、二氧化矽及聚對苯二甲酸乙二酯薄膜，其中，該聚矽氧烷係於該強化層中佔有5~30重量百分比，該二氧化矽係於該強化層中佔有1~20重量百分比，該聚對苯二甲酸乙二酯薄膜係於該強化層中佔有60~85重量百分比。
前述之承載結構中，復包括承載板，其上依序形成有一離形層、該強化層及一結合層。
本發明復提供一種電子封裝件之製法，係包括：提供一如前述之承載結構；於該承載結構上進行電子元件之封裝製程；以及移除該承載結構。
前述之製法中，該電子元件之封裝製程係包括：形成線路結構於該承載結構上；設置該電子元件於該線路結構上；以及形成包覆層於該線路結構上，使該包覆層包覆該電子元件。進一步，於移除該承載結構後，外露出該線路結構，以形成導電元件於該線路結構上。
前述之製法中，該電子元件之封裝製程係包括：設置該電子元件於該承載結構上；以及形成包覆層於該承載結構上，使該包覆層包覆 該電子元件。例如，於移除該承載結構後，形成線路結構於該包覆層與該電子元件上，使該線路結構電性連接該電子元件。或者，於移除該承載結構前，形成線路結構於該包覆層與該電子元件上，使該線路結構電性連接該電子元件。進一步，可形成導電元件於該線路結構上。
前述之製法中，復包括於移除該承載結構後，進行切單製程。
由上可知，本發明之電子封裝件之製法及其承載結構，主要藉由該強化層之設計，以於高溫狀態下，可避免該承載結構發生剝離現象，故相較於習知技術，本發明之製法能順利進行所需之製程。
1:半導體封裝件
10:承載件
100:黏著層
11,21:線路結構
110:介電層
111:線路部
15:半導體元件
150:電極墊
16:導電凸塊
17:底膠
18,28:包覆層
2,3:電子封裝件
2a:承載結構
20:承載板
200:離形層
201:強化層
202:結合層
21a:第一側
21b:第二側
210:絕緣層
211:線路層
212:電性接觸墊
213:絕緣保護層
214:植球墊
25:電子元件
25a:作用面
25b:非作用面
250:電極墊
26:導電凸塊
27:底膠
28a:表面
29:導電元件
36:導電盲孔
S:切割路徑
圖1係為習知半導體封裝件之製法之剖面示意圖。
圖2A至圖2F係為本發明之電子封裝件之製法之第一實施例之剖面示意圖。
圖2D’係為圖2D之另一實施態樣示意圖。
圖3A至圖3D係為本發明之電子封裝件之製法之第二實施例之剖面示意圖。
圖3B’至圖3D’係為圖3B至圖3D之另一實施態樣示意圖。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一”、“第二”、“第三”、“上”、“下”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
圖2A至圖2F係為本發明之電子封裝件2之製法之第一實施例之剖視示意圖。
如圖2A所示，提供一承載結構2a，其包含一承載板20，且該承載板20上依序形成有一離形(release)層200、一強化層201與一結合層202。
於本實施例中，該承載板20係為半導體材質，如玻璃或其它適當構造，且該結合層202係為黏著層，如貼布(tape)。
再者，該強化層201係為含矽材質，如聚矽氧烷、二氧化矽或其它適當成分等。例如，該強化層201係包含聚矽氧烷、二氧化矽及聚對苯二甲酸乙二酯(PET)薄膜。具體地，該強化層201之成分組成如下表所示：
Figure 109124584-A0101-12-0004-19
又，有關離形層200之種類繁多，並無特別限制。
如圖2B所示，形成一線路結構21於該承載結構2a之結合層202上。
於本實施例中，該線路結構21係定義有相對之第一側21a與第二側21b，且該線路結構21係以其第二側21b結合該結合層202。
再者，該線路結構21係包含至少一絕緣層210與設於該絕緣層210上之線路層211。例如，該線路層211係為扇出(fan out)型線路重佈層(redistribution layer，簡稱RDL)。
再者，該線路結構21之製程方式繁多，例如，可採用晶圓製程製作銅材線路層，而以化學氣相沉積(Chemical vapor deposition，簡稱CVD)形成氮化矽或氧化矽以作為絕緣層210；或者，可採用一般非晶圓製程方式形成銅材線路層211，即採用成本較低之高分子介電材作為絕緣層210，如聚醯亞胺(Polyimide，簡稱PI)、聚對二唑苯(Polybenzoxazole，簡稱PBO)、預浸材(Prepreg，簡稱PP)、封裝膠體(molding compound)、感光型介電層或其它材質等以塗佈方式形成之。
又，於該線路結構21於第一側21a可依需求形成一外露局部該線路層211之絕緣保護層213，如防銲材，以令該線路層211之外露部分作為電性接觸墊212。
如圖2C所示，設置至少一電子元件25於該線路結構21之第一側21a上。
於本實施例中，該電子元件25係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該電子元件25係為半導體晶片，其具有相對之作用面25a與非作用面25b，該作用面25a具有複數電極墊250，且該電子元件25係 採用覆晶方式以其電極墊250藉由複數如銅塊或銲錫材之導電凸塊26電性連接該電性接觸墊212。進一步，可依需求形成底膠27於該作用面25a與該線路結構21之間以包覆該些導電凸塊26。
如圖2D所示，形成一包覆層28於該線路結構21之第一側21a(或絕緣保護層213)上，以令該包覆層28包覆該電子元件25。
於本實施例中，該包覆層28係為絕緣材，如聚醯亞胺(PI)、乾膜(dry film)、如環氧樹脂(epoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)、塗佈(coating)或模壓(molding)之方式形成於該線路結構21之絕緣保護層213上。
進一步，可依需求進行薄化製程，如藉由研磨方式，移除該包覆層28之部分材質，如圖2D’所示，使該電子元件25之非作用面25b外露於該包覆層28。例如，該包覆層28之表面28a齊平該電子元件25之非作用面25b。
如圖2E所示，接續圖2D’所示，於烘烤固化該包覆層28後，移除該承載結構2a，以外露該線路結構21之第二側21b。
如圖2F所示，形成複數如銲球之導電元件29於該線路結構21之第二側21b之植球墊214上，俾供後續接置如封裝結構或如另一封裝件或半導體晶片之電子裝置，再沿如圖2E所示之切割路徑S進行切單製程，以獲取複數電子封裝件2。
因此，本發明之製法中，主要藉由該強化層201阻隔於該承載板20與該結合層202之間，以避免於熱製程(如覆晶製程或烘烤固化該包覆層28)中，該承載板20與該結合層202產生剝離(Peeling)之問題，故相較於習知技術，本發明之製法不僅可避免該承載結構2a損壞，且能避免該絕緣層210隨該結合層202於製程中一併剝離之問題。
圖3A至圖3D係為本發明之電子封裝件3之製法之第二實施例之剖視示意圖。本實施例與第一實施例之差異在於電子元件封裝製程，故以下不再贅述相同處。
如圖3A所示，接續圖2A之製程，設置至少一電子元件25於該承載結構2a之結合層202上。
於本實施例中，該電子元件25係以其作用面25a黏貼於該結合層202上。
如圖3B所示，形成一包覆層28於該承載結構2a之結合層202上，以令該包覆層28包覆該電子元件25。之後，烘烤固化該包覆層28。
於本實施例中，如圖3B’所示，該電子元件25亦可以其非作用面25b黏貼於該結合層202上。
如圖3C至圖3D所示，接續圖3B之製程，先移除該承載結構2a，以外露該電子元件25之作用面25a，再形成一線路結構21於該包覆層28與該電子元件25之作用面25a上。之後，形成複數導電元件29於該線路結構21上，再沿切割路徑S進行切單製程，以獲取複數電子封裝件3。
於本實施例中，該線路結構21之線路層211係藉由導電盲孔36電性連接該電極墊250。
再者，若接續圖3B’之製程，如圖3C’至圖3D’所示，先形成一線路結構21於該包覆層28與該電子元件25之作用面25a上，再移除該承載結構2a，以外露該電子元件25之非作用面25b，且形成複數導電元件29於該線路結構21之第二側21b之植球墊214上，再沿切割路徑S進行切單製程，以獲取複數電子封裝件3。
因此，本發明之製法中，主要藉由該強化層201阻隔於該承載板20與該結合層202之間，以避免於熱製程(如烘烤固化該包覆層28)中， 該承載板20與該結合層202產生剝離之問題，故相較於習知技術，本發明之製法不僅可避免該承載結構2a損壞，且能避免該電子元件25受損(如氧化或刮損)之問題。
應可理解地，有關半導體封裝製程之態樣繁多，並不限於上述第一與第二實施例，特此述明。
綜上所述，本發明之電子封裝件之製法及其承載結構，係藉由該強化層之設計，以於高溫狀態下，可避免該承載結構發生剝離現象，故本發明之製法能順利進行所需之製程，因而能提高本發明之製法之可靠度。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2a:承載結構
20:承載板
200:離形層
201:強化層
202:結合層

Claims (9)

  1. 一種半導體封裝製程用之承載結構，係包括：承載板；離形層，係形成於該承載板上；強化層，係形成於該離形層上，且該強化層包含聚矽氧烷、二氧化矽及聚對苯二甲酸乙二酯薄膜，其中，該聚矽氧烷係於該強化層中佔有5~30重量百分比，該二氧化矽係於該強化層中佔有1~20重量百分比，該聚對苯二甲酸乙二酯薄膜係於該強化層中佔有60~85重量百分比；以及結合層，係形成於該強化層上。
  2. 一種電子封裝件之製法，係包括：提供一如請求項1所述之承載結構；於該承載結構上進行電子元件之封裝製程；以及移除該承載結構。
  3. 如請求項2所述之電子封裝件之製法，其中，該電子元件之封裝製程係包括：形成線路結構於該承載結構上；設置該電子元件於該線路結構上；以及形成包覆層於該線路結構上，使該包覆層包覆該電子元件。
  4. 如請求項3所述之電子封裝件之製法，復包括於移除該承載結構後，外露出該線路結構，以形成導電元件於該線路結構上。
  5. 如請求項2所述之電子封裝件之製法，其中，該電子元件之封裝製程係包括： 設置該電子元件於該承載結構上；以及形成包覆層於該承載結構上，使該包覆層包覆該電子元件。
  6. 如請求項5所述之電子封裝件之製法，復包括於移除該承載結構後，形成線路結構於該包覆層與該電子元件上，使該線路結構電性連接該電子元件。
  7. 如請求項5所述之電子封裝件之製法，復包括於移除該承載結構前，形成線路結構於該包覆層與該電子元件上，使該線路結構電性連接該電子元件。
  8. 如請求項6或7所述之電子封裝件之製法，復包括形成導電元件於該線路結構上。
  9. 如請求項2所述之電子封裝件之製法，復包括於移除該承載結構後，進行切單製程。
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TW200740710A (en) * 2006-02-01 2007-11-01 Momentive Performance Mat Inc Sealant composition having reduced permeability to gas
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