CN102187452B - 具有一体式导通孔及导通孔端子的半导体衬底以及相关联系统及方法 - Google Patents

具有一体式导通孔及导通孔端子的半导体衬底以及相关联系统及方法 Download PDF

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CN102187452B
CN102187452B CN200980140926.8A CN200980140926A CN102187452B CN 102187452 B CN102187452 B CN 102187452B CN 200980140926 A CN200980140926 A CN 200980140926A CN 102187452 B CN102187452 B CN 102187452B
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terminal
electric conducting
conducting material
semiconductor substrate
type surface
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CN102187452A (zh
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凯尔·K·柯比
库纳尔·R·帕雷克
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明揭示具有一体式导通孔及导通孔端子的半导体衬底以及相关联系统及方法。根据特定实施例的代表性方法包含：在半导体衬底中形成盲导通孔(140)；将保护层(122)施加到所述导通孔的侧壁表面；及通过从所述导通孔的端表面选择性地移除衬底材料同时防止移除施加保护涂层所倚靠的衬底材料来形成端子开口(111)。所述方法可进一步包含将导电材料安置于所述导通孔及所述端子开口两者中以形成与所述导通孔中的导电材料为一体的导电端子。可接着移除邻近于所述端子的衬底材料以暴露所述端子，所述端子可接着连接到在所述衬底外部的导电结构。

Description

具有一体式导通孔及导通孔端子的半导体衬底以及相关联系统及方法
技术领域
一般来说，本发明针对具有单一导通孔及导通孔端子的半导体衬底以及相关联系统及方法。
背景技术
包含存储器芯片、微处理器芯片及成像器芯片的经封装半导体裸片通常包含安装到衬底且装纳于塑料保护覆盖物中的半导体裸片。所述裸片包含若干功能性特征，例如，存储器单元、处理器电路、成像器装置及互连电路。所述裸片还通常包含电耦合到所述功能性特征的接合垫。所述接合垫电连接到在所述保护覆盖物外部延伸的引脚或其它类型的端子以用于将所述裸片连接到总线、电路及/或其它微电子组合件。
市场压力不断地驱动制造商减小半导体裸片封装的大小且增加此类封装的功能性能力。用于实现这些结果的一种方法是在单一封装中堆叠多个半导体裸片。此种封装中的裸片通常通过电耦合所述封装中的一个裸片的接合垫而与所述封装中的其它裸片的接合垫互连。
已使用各种方法来使多裸片封装内的裸片电互连。一种现有方法是使用直接连接于相邻裸片的接合垫之间的焊料球。另一方法是熔融相邻裸片的接合垫上的“凸块”。然而，前述过程可具有数个缺点。举例来说，前述结构通常需要许多步骤来形成导通孔、导通孔中的导电材料及在经堆叠裸片之间形成连接的接合垫或其它连接结构。所述步骤中的每一者均花费时间且相应地增加制造经封装装置的成本。另外，在至少一些情况下，所述过程中的每一者可使裸片的温度升高，此可消耗分配给所述封装以用于处理的总热预算的显著部分。因此，仍需要用于使半导体封装内的裸片互连的经改进技术。
发明内容
一种根据本发明的一个方面的用于形成半导体组合件的方法，其包括：在半导体衬底中形成盲导通孔，所述导通孔包含侧壁表面及端表面；将保护层施加到所述导通孔的所述侧壁表面；通过在所述端表面处从所述导通孔选择性地移除衬底材料同时防止移除施加所述保护层所倚靠的衬底材料来形成端子开口；将导电材料安置于所述导通孔及所述端子开口两者中以形成与所述导通孔中的导电材料为一体的导电端子；移除邻近于所述端子的衬底材料以暴露所述端子；及将所述端子电连接到在所述衬底外部的导电结构。
一种根据本发明的另一方面的用于形成半导体组合件的方法，其包括：在半导体衬底的第一主表面中形成开口，所述半导体衬底具有背对所述第一主表面的第二主表面，所述开口具有在所述第一表面处具有第一宽度的导通孔部分，所述开口进一步具有在所述第二表面处具有大于所述第一宽度的第二宽度的端子部分；及在不在所述第二表面处使用遮掩过程的情况下，且在不在所述第二表面处打通所述开口的情况下，在所述导通孔部分及所述端子部分处将导电材料安置于所述开口中，所述导电材料为同质无焊料材料。
一种根据本发明的又一方面的半导体组合件，其包括具有第一主表面、第二主表面及从所述第一主表面延伸到所述第二主表面的开口的半导体衬底材料，所述开口包含大体垂直于所述第一主表面延伸的大体圆柱形部分，所述圆柱形部分具有大体平滑的均匀表面，所述开口进一步包含横切于所述圆柱形部分延伸且与所述第二主表面相交的端子部分，所述端子部分具有大体平行于所述第一主表面的平面的宽度，所述宽度大于所述圆柱形部分的对应宽度；单一均匀同质体积的导电材料，其安置于所述开口的所述圆柱形部分及所述端子部分两者中，所述导电材料在所述圆柱形部分中形成导电路径且在所述端子部分中形成导电端子；及微电子元件，其形成于所述衬底材料中且电耦合到所述导电材料。
附图说明
图1是根据本发明的实施例配置的封装的部分示意性侧面横截面图。
图2A到2I是经历根据本发明的实施例的处理的半导体衬底的部分示意性侧面横截面图。
图2J是根据本发明的特定实施例堆叠的两个半导体衬底的部分示意性侧面横截面图。
图2K是根据本发明的另一实施例堆叠的两个半导体衬底的部分示意性侧面横截面图。
图3A到3F是根据本发明的进一步实施例用于形成具有若干形状的半导体衬底端子的代表性方法的部分示意性侧面横截面图。
图4是根据本发明的特定实施例用于将保护层安置于半导体衬底上的过程的部分示意性侧面横截面图。
图5是可包含根据本发明的数个实施例配置的一个或一个以上封装的系统的示意性图解说明。
具体实施方式
下文参照经封装半导体装置及组合件以及用于形成经封装半导体装置及组合件的方法描述本发明的数个实施例。下文描述关于半导体裸片的某些实施例的许多细节。全文使用术语“半导体裸片”来包含各种制品，包含(例如)个别集成电路裸片、成像器裸片、传感器裸片及/或具有其它半导体特征的裸片。可使用下文所述过程中的数个过程来将个别裸片连接到另一个别裸片，或将个别裸片连接到晶片或晶片的一部分，或将晶片或晶片的一部分接合到另一晶片或晶片的一部分。晶片或晶片部分(例如，晶片形式)可包含未经单个化的晶片或晶片部分或经重新组装的载体晶片。所述经重新组装的载体晶片可包含粘合剂材料(例如，柔性粘合剂)，其由具有与未经单个化的晶片的形状相当的外围形状的大体刚性框架环绕，其中经单个化的元件(例如，裸片)由所述粘合剂承载。全文使用术语“半导体衬底”来包含前述配置中的任一者中的前述制品。
在图1到5中及以下文字中陈述某些实施例的许多具体细节以提供对这些实施例的透彻理解。数个其它实施例可具有不同于本发明中所述的那些配置、组件及/或过程的配置、组件及/或过程。因此，所属领域的技术人员将了解，可在不借助图1到5中所示的实施例的数个细节及/或特征及/或借助额外细节及/或特征的情况下实践额外实施例。
图1是包含根据本发明的实施例配置的半导体封装106的半导体组合件100的部分示意性侧面横截面图。封装106可包含支撑部件102，所述支撑部件承载彼此电互连且机械互连的多个半导体衬底(例如，半导体裸片101)。相应地，半导体裸片101中的每一者可包含连接到相邻裸片101的对应裸片端子110的裸片端子110。支撑部件102可包含连接到半导体裸片101中的一者或一者以上的裸片端子110的支撑部件端子107。支撑部件端子107经由在支撑部件102内部的线连接到封装端子104。整个封装106(或封装106的若干部分)可由囊封剂103环绕以保护半导体裸片101及裸片101之间的相关联连接，而封装端子104保持暴露以将封装106连接到外部装置，例如印刷电路板及/或其它电路元件。以下论述描述用于使相邻裸片101彼此连接的端子110的额外特征，及用于形成此类端子的相关联方法。
图2A是半导体衬底120(例如，晶片、晶片部分、裸片或其它衬底)的部分示意性侧面横截面图，其包含具有第一主表面123及面向相反方向的第二主表面124的衬底材料121。如在图2A中所示，已形成多个导通孔140以便沿对应导通孔轴线V延伸到第一表面123中。接合垫可在导通孔140形成之后添加到半导体衬底120(如稍后参照图2J所述)，或导通孔140可在第一表面123处穿透预形成的接合垫。个别导通孔140可关于对应导通孔轴线V轴线对称(例如，每一导通孔140可具有圆形横截面形状)，或导通孔140可具有紧密环绕所述导通孔轴线V的其它横截面形状(例如，低纵横比椭圆形形状)。导通孔140可使用例如各向异性蚀刻技术等技术形成。每一导通孔140可包含一个或一个以上侧壁表面141及一端表面142。在一些实施例中，侧壁表面141(例如)可(例如)通过使用逐步博希(Bosch)蚀刻过程而呈扇形。在此类情况下，导通孔140可经后处理(例如，使用SF6或另一各向同性蚀刻剂)以平滑所述扇形。然而，在特定实施例中，用于形成导通孔140的蚀刻过程可为产生大体平滑非扇形侧壁表面141的大体连续过程。侧壁表面141可相应地具有大体平滑圆柱形形状。用于形成导通孔140的合适过程包含湿式蚀刻过程、稳态干式蚀刻过程、激光钻孔、微放电机加工、微珠喷砂及其它过程。
导通孔140用于容纳连接到半导体材料121内的半导体特征(未在图2A中显示)的导电结构，及用于将半导体衬底120电连接到其它半导体衬底及/或支撑部件的端子。以下图描述这些端子的形成的进一步细节。
如在图2B中所示，保护层122已安置于半导体衬底120上以便覆盖导通孔140的侧壁表面141及端表面142。保护层122可包含C4F8钝化层、CVD沉积氧化物或氮化物或其它合适材料。在图2C中，已移除保护层122覆盖个别导通孔140的端表面142的部分以便重新暴露端表面142。可选择性地移除保护层122在端表面142上方的部分，例如，不移除保护层122邻近于侧壁表面141的部分。举例来说，可使用各向异性移除过程来选择性地移除此材料。代表性移除过程包含间隔物蚀刻，或选择性地移除水平定向的材料的其它蚀刻过程。
在图2D中，已在个别导通孔140的端处形成端子开口111。一般来说，由于覆盖侧壁表面141的保护层122所发挥的保护功能，在不影响上方导通孔140的形状的情况下形成端子开口111。端子开口111可具有不同于导通孔140的那些形状的形状。举例来说，虽然导通孔140可具有大体圆柱形形状，但端子开口111可具有大体球形形状。举例来说，通过使用与各向异性移除过程相反的各向同性移除过程，端子开口111也可横向延伸超过导通孔140的宽度。用于形成此类结构的进一步代表性技术包含于题为“硅中的掩埋式微沟道的微机加工(Micromachining of Buried Micro Channelsin Silicon)”(德波尔(de Boer)等人，微电机系统期刊，2000年3月，第9卷，第1期)的文章中，其以引用方式并入本文中。在形成端子开口111之后，在用于将导电材料施加于导通孔140及端子开口111两者中的随后步骤之前移除保护层122的延伸到导通孔140中且在导通孔140之间的部分，如下文所述。
图2E图解说明在额外材料已安置于其上之后的半导体衬底120。举例来说，如在图2E中所示，电介质层125已安置于衬底材料121的第一表面123上，以及导通孔140及端子开口111中。障壁层126已安置于电介质层125上，且任选种晶层127已安置于障壁层126上。合适的电介质材料包含TEOS、聚对二甲苯基、氮化物、氧化物及/或其它合适材料。合适的障壁材料包含钨、氮化钛、钽、前述材料的化合物及/或其它合适材料。在一些实施例中，种晶层127用于促进填充导通孔140及端子开口111的过程。在其它实施例中，可使用直接在障壁上镀覆过程来实现相同结果。
图2F图解说明在导电材料112已安置于导通孔140及端子开口111中之后的半导体衬底120。导电材料112可使用从底部向上的沉积过程或其它合适过程安置于导通孔140及端子开口111两者中以形成填充导通孔140及端子开口111两者的一体式导电结构119。可在不在于导通孔140中形成导电材料112的操作与于端子开口111中形成导电材料112的操作之间重新对准半导体衬底120的情况下执行此单步骤过程。也可在不需要在导通孔140的端处形成通风孔的情况下执行此操作，此进一步减少处理时间。
用于将导电材料112引入到导通孔140及端子开口111中的合适技术包含(但不限于)：脉冲化学气相沉积(pCVD)、离子物理气相沉积(iPVD)、原子层沉积(ALD)、电接枝、从底部向上的ECD镀覆及无电镀覆。合适的导电材料包含铜、铝、钨、金及/或前述成分的合金。在特定实施例中，将导电材料112选择为电解铜，其在与无电沉积材料相比较且与焊料相比较时具有增强的纯度。举例来说，所述导电材料可为至少90％的铜，且在一些情况下99％铜。
在另外其它特定实施例中，导电材料112不具有焊料，例如其不包含焊料或包含不多于微量的焊料。预期此种材料选择可产生具有增强的导电性及/或结构特性的导电结构。
在另外其它实施例中，导电材料112可在安置于导通孔140及端子开口111中之前执行(至少部分地)。举例来说，导电材料112可包含使用线接合过程插入到导通孔140中的预形成的线。在此情况下，下文所述用于从衬底120的第二表面124移除材料的过程可在将导电材料112沉积于导通孔140中之前而非之后执行。
当导电材料112已使用内建技术(例如镀覆)引入到导通孔140及端子开口111中时，所述过程可接下来包含从第二表面124移除材料以暴露端子开口111中的导电材料112。举例来说，在特定实施例中，可移除衬底材料121(例如，在背向研磨或其它移除过程中)直到图2F中所示的虚线。
图2G图解说明当衬底材料121已从第二表面124移除之后的图2F中所示的衬底120的一部分，其包含单一导通孔140。如在图2G中所示，移除衬底材料121可暴露导电材料112以形成第一端子110a。所得第一端子110a可具有大于导通孔140的对应宽度W1的宽度W2。相应地，第一端子110a可包含用于连接到邻近结构的额外暴露表面积。钝化层128可接着安置于第二表面124上以在前述背向研磨操作之后保护第二表面124。
可依据衬底120的特性选择导通孔140及第一端子110a的尺寸以形成高度导电紧凑电路径。举例来说，对于初始800μ厚衬底120来说，导通孔140可经选择以具有小于100μ(例如，50μ或25μ)的深度D1。可背向研磨剩余衬底材料121，如上所述。宽度W1可为20μ或更小(例如，10μ或5μ)。
在图2G中所示的实施例的特定方面中，第一端子110a可具有与衬底材料121的第二表面124大体齐平的暴露导电表面118。相应地，导通孔140及端子开口111中的所得导电结构119从第一表面123延伸穿过衬底材料121到达第二表面124。在其它实施例中，可移除额外衬底材料121以便进一步暴露第一端子110a的表面(例如)以形成“凸块”。举例来说，图2H图解说明第二端子110b，其通过从环绕第二端子110b的区域中的衬底120的第二表面124移除额外材料来形成。可使用湿式蚀刻过程或等离子干式蚀刻过程(例如，借助SF6O2化学品)移除衬底材料121。也可移除此区域中的电介质材料125。此过程可产生导电、面向外的表面113，所述导电、面向外的表面从导通孔轴线V在横向上面向外，且以渐缩方式远离第二表面124轴向突出。相应地，面向外的表面113可增加可用于建立与邻近装置的连接的第二端子110b的暴露表面积(相对于第二端子110b的横截面积)。在其它实施例中，面向外的表面113可突出或以其它方式轴向延伸到邻近装置的结构中或邻近装置的结构上以建立电连接及物理连接。
第二端子110b可包含除填充导通孔140的导电材料112以外的导电材料。举例来说，第二端子110b可包含施加到暴露表面118的薄镀涂层114。薄镀涂层114可促进与邻近装置的电连接。在特定实施例中，所述薄镀涂层可包含锡、金、铟或其它合适导电材料。一般来说，薄镀涂层114可使用不需要使用掩模的无电处理施加。
图2I图解说明还包含除导电填充材料112以外的导电材料的代表性第三端子110c。在此特定实施例中，额外材料可包含焊料球115。焊料球115可接触导电材料112的面向下的暴露表面118以及面向外的表面113。此布置可给予端子110c用于连接到邻近结构的增加的表面积。由于焊料球115围绕面向外的表面113延伸，因此其可提供与导电材料112的增加的物理连续性及电连续性两者。
图2J示意性图解说明包含电连接到堆叠式布置中的第二裸片101b的第一裸片101a的半导体组合件100的一部分。裸片101a、101b可包含借助线131连接到接合垫132的掩埋式微电子元件130(例如，电容器或晶体管)。接合垫132又电连接到导通孔140中的导电结构119。第一裸片101a可包含在配置上大体类似于上文参照图2G所述的那些端子的第一端子110a。第二裸片101b可包含在配置上大体类似于上文中参照图2H所述的那些端子的第二端子110b。两个裸片101a、101b可借助第一端子110a接触第二端子110b而装配在一起。在一个实施例中，个别第一端子110a的暴露表面118可接触对应个别第二端子110b的暴露表面118。在另一实施例中，第一端子及第二端子110a、110b中的一者或两者可包含接触另一端子的薄镀涂层114(图2H)。端子110a、110b可使用热、压力及/或其它形式的能量(例如，超声波能量)连接以使对应第一端子及第二端子110a、110b彼此熔合。举例来说，可在不使端子成分回流(例如，通过施加压力或压力与超声波能量组合)的情况下附接端子110a、110b。合适的代表性过程包含超声波、热声波及/或热压缩过程。在一个实施例中，第二端子110b可轴向突出超过第二裸片101b的对应第二表面124以与第一裸片101a的对应第一端子110a啮合。在一些情况下，间隙105可在所述附接过程完成之后保留于端子110a、110b当中的裂隙中的裸片101a、101b之间。间隙105可(例如)在囊封堆叠式结构之前以底填充材料或其它合适材料填充。在特定实施例中，完成的组合件可具有大体类似于图1中所示的配置的配置。
在图2J中，第一及第二裸片101a、101b经堆叠以使得第一端子110a的暴露表面118接触第二端子110b的暴露端子118。在其它实施例中，一个或两个裸片101a、101b的相对定向可反转。举例来说，在一个实施例中，裸片101a、101b两者均可反转(与图3J中所示的定向相比较)以使得第一裸片101a的接合垫132接触第二裸片101b的对应接合垫132，且每一裸片101a、101b的暴露表面118面向外(例如，在图2J中向上并向下)。
在图2K中所示的另一实例中，第二裸片101b的定向相对于图2J中所示的定向反转，而第一裸片101a保持其定向。相应地，第一裸片101a的暴露表面118接触第二裸片101b的接合垫132。在特定实施例中，此定向可用于堆叠多于两个裸片。在其它实施例中，(例如)当所述组合件包含多于两个经堆叠裸片时，可组合上文参照图2J到2K所述的前述定向。举例来说，第三裸片可堆叠于图2J中所示的第二裸片101b的顶部上，其中第三裸片端子的暴露表面与第二裸片101b的接合垫132接触。
上文参照图1到2K所述的前述实施例中的至少一些实施例的一个特征是，穿过导通孔140的导电路径可与在导通孔140的端处形成端子110同时形成。因此，在导通孔140内且在端子110处的总体导电结构119可大体为一体式且同质。特定来说，相同导电材料可在不在总体结构119内形成材料边界的情况下填充导通孔140及端子开口111。相应地，当与在导通孔与对应接合垫之间具有边界的现有结构相比较时，此过程可产生具有增加的连续性的总体导电结构119。因此，当与现有结构相比较时，这些结构可具有增加的可靠性。
另外，导通孔140及端子110可在不需要在第二表面124处使用遮掩/光刻过程的情况下形成，所述遮掩/光刻过程通常用于在导通孔的端处形成接合垫或凸块。替代地，可使用耗时较少且较不昂贵的沉积及选择性蚀刻过程来形成所述结构。此又可减少形成导电结构119所需的时间量且因此可减少在其中形成导通孔的裸片或其它产品的成本。
前述过程的至少一些实施例的另一特征是，不需要在填充导通孔140的操作与形成端子110的操作之间重新对准半导体衬底120。替代地，如上所论述，两个结构均可作为相同操作的一部分而形成。更进一步，如上所论述，导通孔140可使用产生非扇形、大体均匀、平坦的圆柱形壁的过程而形成。举例来说，可使用连续各向异性蚀刻过程来产生导通孔140。因此，形成导通孔140可比使用交替蚀刻过程的导通孔消耗更少的时间，且可比产生有轮廓的及/或非均匀壁的过程更有效地使用在衬底120中可用的有限体积。
图3A到3F根据本发明的进一步实施例图解说明用于形成具有若干形状的导电端子的代表性过程。首先参照图3A，使用大体类似于上述那些过程的过程在衬底120中形成导通孔140。可接着使用可形成除上述大体球形形状以外的形状的过程在导通孔140的底部处形成端子开口311。举例来说，可使用各向异性蚀刻过程以与衬底材料121的晶面对准的方式来移除衬底材料121，从而产生具有大体平坦侧壁的端子开口311。用于形成此类开口的代表性过程论述于先前以引用方式并入的德波尔等人(2000年3月)的文章中。
在图3B中，已将电介质层125、障壁层126及任选种晶层127安置于导通孔140及端子开口311中。接着使用上文参照图2F所述的前述过程中的任一者以导电材料112填充导通孔140及端子开口311。接着移除来自衬底120的第二表面124的材料以形成具有暴露表面318的第一端子310a。
图3C图解说明通过以大体类似于上文参照图2H所述方式的方式移除额外衬底材料121形成的第二端子310b。相应地，第二端子310b可包含突出超过第二表面124的面向外的表面313。第二端子310b可包含额外导电材料，例如，薄镀涂层(如上文参照图2H所述)或焊料球(如上文参照图2I所述)。
图3D图解说明根据本发明的另一实施例配置的第三端子310c。在此实施例中，已在移除端子开口311内的导电材料112中的任一者之前停止了背向研磨过程。已从在端子开口311中的导电材料112周围选择性地移除了衬底材料121从而形成所图解说明的结构。举例来说，可将衬底120暴露到优先移除衬底材料121(且可能是电介质材料125及障壁层126)而不移除导电材料112且任选地种晶层127的蚀刻剂。此布置可产生突出超过第二表面124一额外量的第三端子310c，且在第三端子310c处提供额外体积的导电材料112以用于将衬底120连接到邻近结构。
图3E及3F根据本发明的另一实施例图解说明用于形成端子的另一过程。如在图3E中所示，在一些情况下，施加到端子开口311及导通孔140的表面的导电材料112可在(例如)端子开口311中留下空隙316。虽然在大多数半导体处理操作中通常不期望空隙，但可容易地适应及/或计及图3E中所示的空隙316。举例来说，如在图3F中所示，当从第二表面124移除衬底材料121以露出暴露表面318时，也暴露空隙316。任选地，可接着以第二导电材料317填充空隙316。举例来说，空隙316可以薄镀涂层填充或部分地填充，且空隙316的形状及额外表面积可促进与所述涂层的强物理连接及电连接。在另一实施例中，空隙316可保持完整且可用于从相邻(例如，经堆叠)衬底的对应端子结构接收导电材料。举例来说，空隙316可接收来自相邻衬底的焊料球或其它端子(例如，分别在图2H、2I中所示的第二端子110b或第三端子110c)并与其连接。
图4图解说明用于在衬底120中形成导通孔140的另一实施例。在此实施例中，将保护层422施加到衬底120的第一表面123，且施加到导通孔140的侧壁表面141。在一些情况下，导通孔140可具有高纵横比(例如，相对长的长度及/或相对小的宽度)，此可致使保护层422与附接到端表面142相比较更容易地附接到侧壁表面141。因此，端表面142可几乎不接收保护材料422。此布置可消除从端表面142移除保护层422的需要，且替代地，可在施加保护层422之后立即形成端子开口。因此，预期此过程的实施例减少形成导电端子所需的时间量，且因此可减少从衬底120形成裸片或其它最终产品的成本。
由根据上文参照图1到4所述的方法结合衬底所产生的半导体封装中的任一者可并入到众多较大及/或较复杂的系统中，其代表性实例是图5中示意性地显示的系统500。系统500可包含处理器552、存储器554(例如，SRAM、DRAM、快闪存储器及/或其它存储器装置)、输入/输出装置556(例如，传感器及/或传输器)及/或其它子系统或组件558。具有上文参照图1到4所述的特征中的任一者或组合的半导体封装可包含于图5中所示的装置中的任一者中。所得系统500可执行各种各样的计算、处理、存储、感测、成像及/或其它功能中的任一者。因此，代表性系统500可包含(但不限于)：计算机及/或其它数据处理器，例如，桌上型计算机、膝上型计算机、因特网器具、手持式装置(例如，掌上型计算机、可穿戴式计算机、蜂窝式电话或移动电话、个人数字系统、音乐播放器、相机等等)、多处理器系统、基于处理器的或可编程的消费电子产品、网络计算机及微型计算机。其它代表性系统500可容纳于单一单元中或分布于多个互连式单元上方(例如，经由通信网络)。系统500的组件可相应地包含本地及/或远程存储装置及各种各样的计算机可读媒体中的任一者。
根据前述内容将了解，已出于图解说明目的描述了本发明的特定实施例，但前述系统及方法也可具有其它实施例。举例来说，虽然在具有两个或三个经堆叠裸片的半导体封装的上下文中描述了上述实施例中的某些实施例，但在其它实施例中，所述封装可包含其它数目的经堆叠裸片。在一些情况下，(例如)如果衬底形成图1中所示的最顶部裸片，那么导通孔140可不完全延伸穿过所述衬底。在此类情况下，导通孔140仍可出于热目的用于(例如)充当热导管或散热片。可使用上文所述的相同过程来形成导通孔及端子，但不在所述衬底的第二表面处暴露所述端子。此类衬底也可用于平面(未经堆叠)裸片。在其它实施例中，所述端子可经暴露以将平面(未经堆叠)裸片连接到PCB或其它支撑部件或衬底。用于形成前述经连接结构且连接不同半导体衬底的配合结构的过程中的许多过程可在裸片级(例如，在单个化裸片之后)、晶片级(例如，在单个化裸片之前)及/或在其它处理阶段实施。
在其它实施例中，可组合或消除在特定实施例的上下文中所描述的某些特征。举例来说，上文参照图4所述的涂覆侧壁表面的过程可应用于与其它图式中的任一者中所示的导电结构相关联地形成的导通孔。如在图3C及3D中所示，从整个端子开口周围移除衬底材料的过程可应用于在图2E或2H中所示的端子开口。此外，虽然已在那些实施例的上下文中描述了与某些实施例相关联的特征及结果，但其它实施例也可展现此类特征及结果，且并非所有实施例均必须要展现此类特征及结果。相应地，本发明可包含上文未明确显示或描述的其它实施例。

Claims (34)

1.一种用于形成半导体组合件的方法，其包括：
在半导体衬底中形成盲导通孔，所述导通孔包含侧壁表面及端表面，其中所述半导体衬底具有第一表面及与所述第一表面面向相反方向的第二表面，且其中所述导通孔从所述第一表面延伸到所述半导体衬底中；
将保护层施加到所述导通孔的所述侧壁表面；
通过在所述端表面处从所述导通孔选择性地移除衬底材料同时防止移除施加所述保护层所倚靠的衬底材料来形成端子开口；
在不在所述第二表面处打通所述端子开口的情况下，将导电材料安置于所述导通孔及所述端子开口两者中以形成与所述导通孔中的导电材料为一体的导电端子，其中所述导电材料为至少填充所述导通孔和所述端子开口的无焊料材料；
移除邻近于所述端子的衬底材料以暴露所述端子；及
将所述端子电连接到在所述衬底外部的导电结构。
2.根据权利要求1所述的方法：
其中安置导电材料包含在不在导通孔安置过程与端子安置过程之间相对于无焊料导电材料的源重新对准所述半导体衬底的情况下形成同质导电结构；
其中在不从所述保护层移除衬底材料的情况下执行所述在所述端表面处从所述导通孔移除衬底材料的过程；
其中所述半导体衬底包含第一半导体裸片，且其中将所述端子电连接到导电结构包含将所述端子连接到其中一个裸片面向另一裸片的堆叠式布置中的第二半导体裸片；
其中所述导通孔沿导通孔轴线伸长；
其中移除邻近于所述端子的衬底材料包含暴露所述端子的在横向上面向外的表面；且
其中所述方法进一步包括在不在所述半导体衬底靠近所述端子的表面上使用掩模的情况下将额外导电材料施加到所述端子。
3.根据权利要求1所述的方法，其中形成导电端子包含在不在所述第二表面处使用掩模的情况下形成所述导电端子。
4.根据权利要求1所述的方法，其中安置导电材料包含在不在导通孔安置过程与端子安置过程之间相对于所述导电材料的源重新对准所述半导体衬底的情况下，在所述导通孔安置过程期间将所述导电材料安置于所述导通孔中且在所述端子安置过程期间将所述导电材料安置于所述端子开口中。
5.根据权利要求1所述的方法，其中所述半导体衬底包含半导体裸片，且其中将所述端子电连接到导电结构包含将所述端子连接到支撑部件。
6.根据权利要求1所述的方法，其中所述半导体衬底包含第一半导体裸片，且其中将所述端子电连接到导电结构包含将所述端子连接到第二半导体裸片。
7.根据权利要求1所述的方法，其中施加所述保护层包含将所述保护层施加到侧壁表面及所述端表面两者，且其中所述方法进一步包括在形成所述端子开口之前从所述端表面移除所述保护层。
8.根据权利要求1所述的方法，其中施加所述保护层包含在不将所述保护层施加到所述导通孔的所述端表面的情况下完成所述保护层到所述侧壁表面的施加。
9.根据权利要求1所述的方法，其中所述导电材料为第一导电材料，且其中所述方法进一步包括在将所述端子电连接到所述导电结构之前将第二导电材料施加到所述第一导电材料。
10.根据权利要求9所述的方法，其中施加所述第二导电材料包含施加薄镀涂层。
11.根据权利要求9所述的方法，其中施加所述第二导电材料包含施加焊料球。
12.根据权利要求11所述的方法，其中所述导通孔沿导通孔轴线伸长，且其中移除衬底材料包含暴露所述端子的在横向上面向外的表面，且其中施加所述焊料球包含施加所述焊料球以使得其接触所述端子的所述暴露的在横向上面向外的表面。
13.根据权利要求1所述的方法，其中形成端子开口包含形成具有沿所述衬底材料的晶面定位的平坦侧的端子开口。
14.根据权利要求1所述的方法，其中形成端子开口包含形成凹面杯形开口。
15.根据权利要求1所述的方法，其中形成导通孔包含形成具有平滑的非扇形侧壁的导通孔。
16.根据权利要求1所述的方法，其中安置导电材料包含安置具有至少90%的纯度的铜中的至少一者。
17.根据权利要求1所述的方法，其中电连接所述端子包含在不使所述导电材料回流的情况下电连接所述端子。
18.根据权利要求1所述的方法，其中所述端子的暴露的导电材料具有横向向外突出、越过所述半导体衬底的最外表面的最外边界。
19.一种用于形成半导体组合件的方法，其包括：
在半导体衬底的第一主表面中形成开口，所述半导体衬底具有背对所述第一主表面的第二主表面，所述开口具有在所述第一主表面处具有第一宽度的导通孔部分，所述开口进一步具有在靠近所述第二主表面处具有大于所述第一宽度的第二宽度的端子部分；及
在不在所述第二主表面处使用遮掩过程的情况下，且在不在所述第二主表面处打通所述开口的情况下，在所述导通孔部分及所述端子部分处将导电材料安置于所述开口中，所述导电材料为同质无焊料材料。
20.根据权利要求19所述的方法，其中所述半导体衬底为第一半导体衬底，且其中所述方法进一步包括相对于所述第一半导体衬底堆叠第二半导体衬底且将所述第一半导体衬底的所述端子部分处的所述导电材料电连接到所述第二半导体衬底的端子。
21.根据权利要求19所述的方法，其中形成开口包含形成具有侧壁表面及端表面的导通孔部分，将保护层施加到所述侧壁表面，及从所述端表面移除材料以形成所述端子部分。
22.根据权利要求19所述的方法，其进一步包括从所述第二主表面移除衬底材料以暴露所述导电材料的横向面向外的表面，以便界定导电端子，其中所述导电端子具有最外边界，所述最外边界横向向外突出、越过所述半导体衬底的与所述第一主表面相反的最外表面。
23.一种半导体组合件，其包括：
半导体衬底，其包括衬底材料，所述半导体衬底具有第一主表面、第二主表面及从所述第一主表面延伸到所述第二主表面的开口，所述开口包含垂直于所述第一主表面延伸的圆柱形部分，所述圆柱形部分具有平滑的均匀表面，所述开口进一步包含横切于所述圆柱形部分延伸且与所述第二主表面相交的端子部分，所述端子部分具有平行于所述第一主表面的平面的宽度，所述宽度大于所述圆柱形部分的对应宽度；
单一均匀同质体积的导电材料，其安置于所述开口的所述圆柱形部分及所述端子部分两者中，所述导电材料为无焊料材料，且在所述圆柱形部分中形成导电路径，并且在所述端子部分中形成导电端子的至少一部分，所述导电端子具有凸圆状的横截面，其中所述横截面是在所述第二主表面的平面法线上取得的，其中凸圆状的导电端子在远离所述第一主表面的方向上远离所述第二主表面突出，所述导电端子具有第一横截面积和大于所述第一横截面积的第二横截面积，其中所述第一横截面积在平行于所述第二主表面的第一平面中并且包括所述半导体衬底的最外表面，并且所述第二横截面积在平行于所述第一平面并且定位在越过所述最外表面的第二平面中；及
微电子元件，其形成于所述衬底材料中且电耦合到所述导电材料。
24.根据权利要求23所述的组合件：
其中所述导电材料在所述端子部分处具有外表面，所述外表面具有大于所述开口在所述端子部分处的横截面积的表面积；
其中所述端子部分处的所述导电材料的外边界沿远离所述第二主表面的方向横向向外渐缩；且
其中所述组合件进一步包括附接到所述端子部分处的所述导电材料的焊料球，所述焊料球与所述导电材料的所述渐缩外边界接触。
25.根据权利要求23所述的组合件，其中所述导电材料在所述端子部分处具有外表面，所述外表面具有大于所述开口在所述端子部分处的横截面积的表面积。
26.根据权利要求23所述的组合件，其中所述圆柱形部分不具有扇形内表面。
27.根据权利要求23所述的组合件，其中所述导电材料为具有至少90%的纯度的铜。
28.根据权利要求23所述的组合件，其中所述导电材料沿远离所述第一主表面的方向远离所述第二主表面突出。
29.根据权利要求28所述的组合件，其中所述端子部分处的所述导电材料的外边界沿远离所述第二主表面的方向横向向外渐缩。
30.根据权利要求23所述的组合件，其中所述导电材料具有凹面杯形空隙。
31.根据权利要求23所述的组合件，其中所述衬底材料形成第一半导体裸片的一部分，且其中所述导电铜材料的纯度为至少90%，且其中所述半导体组合件进一步包括第二半导体裸片，所述第二半导体裸片具有电连接到所述第一半导体裸片的所述端子部分处的所述导电材料的导电端子。
32.根据权利要求23所述的组合件，其中所述端子部分具有球形形状。
33.根据权利要求23所述的组合件，其中所述端子部分具有与所述半导体衬底材料的晶面对准的平坦壁。
34.根据权利要求23所述的组合件，其进一步包括：
晶种层，其在所述端子部分处的所述导电材料的外边界上；以及
障壁层，其在所述端子部分处的所述晶种层的外边界上，其中所述晶种层和所述障壁层向外突出越过所述半导体衬底的最外表面，并且其中所述导电端子包括所述晶种层、所述障壁层和所述导电材料。
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