TWI552264B - 具單一穿孔和穿孔端子之半導體基板，及相關系統和方法 - Google Patents

具單一穿孔和穿孔端子之半導體基板，及相關系統和方法 Download PDF

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TWI552264B
TWI552264B TW098135151A TW98135151A TWI552264B TW I552264 B TWI552264 B TW I552264B TW 098135151 A TW098135151 A TW 098135151A TW 98135151 A TW98135151 A TW 98135151A TW I552264 B TWI552264 B TW I552264B
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terminal
conductive material
conductive
semiconductor substrate
substrate
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TW098135151A
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TW201029111A (en
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凱爾Ｋ 克比
庫諾Ｒ 派瑞克
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美光科技公司
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Description

具單一穿孔和穿孔端子之半導體基板，及相關系統和方法
一般而言，本發明係針對具單一穿孔及穿孔端子之半導體基板及相關系統和方法。
包含記憶體晶片、微處理器晶片及成像器晶片之經封裝半導體晶粒通常包含安裝至一基板且封閉於一塑膠保護覆蓋物中之一半導體晶粒。該晶粒包含若干功能性特徵，例如，記憶體胞、處理器電路、成像器裝置及互連電路。該晶粒亦通常包含電耦合至該等功能性特徵之接合墊。該等接合墊電連接至在該保護覆蓋物外部延伸之插針或其他類型之端子以用於將該晶粒連接至匯流排、電路及/或其他微電子總成。
市場壓力不斷地驅動製造商減小半導體晶粒封裝之大小且增加此等封裝之功能性能力。用於達成此等結果之一種方法係在一單個封裝中堆疊多個半導體晶粒。此一封裝中之晶粒通常藉由電耦合該封裝中之一個晶粒之接合墊而與該封裝中之其他晶粒之接合墊互連。
已使用各種方法來使一多晶粒封裝內之晶粒電互連。一種現有方法係使用直接連接於相鄰晶粒之接合墊之間的焊料球。另一方法係熔化相鄰晶粒之接合墊上之「凸塊」。然而，前述過程可具有數個缺點。舉例而言，前述結構通常需要許多步驟來形成穿孔、穿孔中之導電材料及在經堆疊晶粒之間形成連接之接合墊或其他連接結構。該等步驟中之每一者皆花費時間且因此增加製造經封裝裝置之成本。另外，在至少某些情形中，該等過程中之每一者可提升晶粒之溫度，此可消耗分配至該封裝以供處理之總熱預算之一顯著部分。因此，仍需要用於使一半導體封裝內之晶粒互連之經改良技術。
下文參照經封裝半導體裝置及總成以及用於形成經封裝半導體裝置及總成之方法闡述本發明之數個實施例。下文闡述關於半導體晶粒之某些實施例之許多細節。全文使用術語「半導體晶粒」來包含各種製品，包含(例如)個別積體電路晶粒、成像器晶粒、感測器晶粒及/或具有其他半導體特徵之晶粒。可使用下文所述過程中之數個過程來將一個別晶粒連接至另一個別晶粒，或將一個別晶粒連接至一晶圓或一晶圓之一部分，或將一晶圓或一晶圓之一部分接合至另一晶圓或一晶圓之一部分。晶圓或晶圓部分(例如，晶圓形式)可包含一未經單片化之晶圓或晶圓部分或一經重新組裝之載體晶圓。該經重新組裝之載體晶圓可包含一黏合劑材料(例如，一撓性黏合劑)，其由具有可與一未經單片化之晶圓之形狀相比較的一週邊形狀之一大致剛性框架環繞，其中經單片化之元件(例如，晶粒)由該黏合劑承載。全文使用術語「半導體基板」來包含前述組態中之任一者中之前述製品。
在圖1至5中及以下文字中陳述某些實施例之諸多具體細節以提供對此等實施例之一透徹理解。數個其他實施例可具有不同於本發明中所述之彼等組態、組件及/或過程之組態、組件及/或過程。因此，熟習相關技術者將瞭解，可於不藉助圖1至5中所示之實施例之數個細節及/或特徵且/或藉助額外細節及/或特徵之情形下實踐額外實施例。
圖1係包含根據本發明之一實施例組態之一半導體封裝106之一半導體總成100之一局部示意性側面橫截面圖。封裝106可包含一支撐構件102，該支撐構件承載彼此電互連及機械互連之多個半導體基板(例如，半導體晶粒101)。因此，半導體晶粒101中之每一者可包含連接至相鄰晶粒101之對應晶粒端子110之晶粒端子110。支撐構件102可包含連接至半導體晶粒101中之一者或多者之晶粒端子110之支撐構件端子107。支撐構件端子107經由在支撐構件102內部之線連接至封裝端子104。整個封裝106(或封裝106之部分)可由一囊封劑103環繞以保護半導體晶粒101及晶粒101之間的相關連接，而封裝端子104保持曝露以將封裝106連接至外部裝置，例如印刷電路板及/或其他電路元件。以下論述闡述用於使相鄰晶粒101彼此連接之端子110之額外特徵，及用於形成此等端子之相關方法。
圖2A係一半導體基板120(例如，一晶圓、晶圓部分、晶粒或其他基板)之一局部示意性側面橫截面圖，其包含具有一第一主表面123及一背對第二主表面124之一基板材料121。如在圖2A中所示，已形成多個穿孔140以便沿對應穿孔軸V延伸至第一表面123中。一接合墊可在穿孔140形成之後添加至半導體基板120(如稍後參照圖2J所述)，或穿孔140可在第一表面123處穿透預形成之接合墊。個別穿孔140可關於對應穿孔軸V軸對稱(例如，每一穿孔140可具有一圓形橫截面形狀)，或穿孔140可具有緊密環繞該穿孔軸V之其他橫截面形狀(例如，一低縱橫比橢圓形形狀)。穿孔140可使用例如各向異性蝕刻技術等技術形成。每一穿孔140可包含一個或多個側壁表面141及一端表面142。在某些實施例中，側壁表面141(例如)可(例如)藉由使用逐步Bosch蝕刻過程而呈扇形。在此等情形中，穿孔140可經後處理(例如，使用SF6或另一各向同性蝕刻劑)以使扇形平滑。然而，在特定實施例中，用於形成穿孔140之蝕刻過程可係產生大致平滑非扇形側壁表面141之一大致連續過程。側壁表面141可因此具有一大致平滑圓柱形形狀。用於形成穿孔140之合適過程包含一濕式蝕刻過程、一穩態乾式蝕刻過程、雷射鑽孔、微放電機加工、微珠噴砂及其他過程。
穿孔140用於容納連接至半導體材料121內之半導體特徵(未在圖2A中顯示)之導電結構，及用於將半導體基板120電連接至其他半導體基板及/或支撐構件之端子。以下圖闡述此等端子之形成之進一步細節。
如在圖2B中所示，一保護層122已設置於半導體基板120上以便覆蓋穿孔140之側壁表面141及端表面142。保護層122可包含一C4F8鈍化層、CVD沈積氧化物或氮化物或其他適合材料。在圖2C中，已移除保護層122覆蓋個別穿孔140之端表面142之部分以便重新曝露端表面142。可選擇性地移除保護層122在端表面142上方之部分，例如，不移除保護層122毗鄰於側壁表面141之部分。舉例而言，可使用一各向異性移除過程來選擇性地移除此材料。一代表性移除過程包含一間隔蝕刻，或選擇性地移除水平定向之材料之其他蝕刻過程。
在圖2D中，已在個別穿孔140之端部形成端子開口111。一般而言，形成端子開口111而不影響上方穿孔140之形狀，此乃因由覆蓋側壁表面141之保護層122執行之保護功能。端子開口111可具有不同於穿孔140之彼等形狀之形狀。舉例而言，雖然穿孔140可具有一大致圓柱形形狀，但端子開口111可具有一大致球形形狀。舉例而言，藉由使用與一各向異性移除過程相反的一各向同性移除過程，端子開口111亦可側向延伸超過穿孔140之寬度。用於形成此等結構之進一步代表性技術包含於一題為「Micromachining of Buried Micro Channels in Silicon」(de Boer等人，Journal of Micro Electromechanical Systems，第9卷，第1號，2000年3月)之文章中，其以引用方式併入本文中。在端子開口111形成之後，在用於將導電材料施加於穿孔140及端子開口111兩者中之隨後步驟之前移除保護層122延伸至穿孔140中且在穿孔140之間的部分，如下文所述。
圖2E圖解說明在額外材料已設置於其上之後之半導體基板120。舉例而言，如在圖2E中所示，一介電層125已設置於基板材料121之第一表面123上，以及在穿孔140及端子開口111中。一障壁層126已設置於介電層125上，且一可選種晶層127已設置於障壁層126上。適合介電材料包含TEOS、聚對二甲苯基、氮化物、氧化物及/或其他適合材料。適合障壁材料包含鎢、氮化鈦、鉭，前述材料之化合物及/或其他適合材料。在某些實施例中，種晶層127用於促進填充穿孔140及端子開口111之過程。在其他實施例中，可使用一直接在障壁上鍍覆過程來達成相同結果。
圖2F圖解說明在一導電材料112已設置於通孔140及端子開口111中之後之半導體基板120。導電材料112可使用一自底向上沈積過程或其他適合過程設置於穿孔140及端子開口111兩者中以形成填充穿孔140及端子開口111兩者之一單一導電材料結構119。可執行此單步驟過程，而不在在穿孔140中形成導電材料112之操作與在端子開口111中形成導電材料112之操作之間重新對準半導體基板120。亦可執行此操作，而無需在穿孔140之端部處形成一通風孔，此進一步減少處理時間。
用於將導電材料112引入至穿孔140及端子開口111中之適合技術包含(但不限於)：脈衝化學氣相沈積(pCVD)、離子物理氣相沈積(iPVD)、原子層沈積(ALD)、電接枝、自底向上ECD鍍覆及無電鍍覆。適合導電材料包含銅、鋁、鎢、金及/或前述成分之合金。在特定實施例中，將導電材料112選擇電解銅，其在與無電沈積材料相比較且與焊料相比較時具有增強之純度。舉例而言，該導電材料可係至少90%銅，且在某些情形中99%銅。
在再進一步特定實施例中，導電材料112不具有焊料，例如其不包含焊料或不再包含一痕量之焊料。期盼此一材料選擇可產生具有增強之導電性及/或結構特性之導電結構。
在再進一步實施例中，導電材料112可在設置於穿孔140及端子開口111中之前執行(至少部分地)。舉例而言，導電材料112可包含使用一線結合過程插入至穿孔140中之一預形成之線。在此情形中，下文所述用於自基板120之第二表面124移除材料之過程可在將導電材料112沈積於穿孔140中之前而非之後執行。
當導電材料112已使用一內建技術(例如鍍覆)引入至穿孔140及端子開口111中時，該過程可接著包含自第二表面124移除材料以曝露端子開口111中之導電材料112。舉例而言，在一特定實施例中，可移除基板材料121(例如，在一背向研磨或其他移除過程中)直到圖2F中所示之虛線。
圖2G圖解說明當基板材料121已自第二表面124移除之後之圖2F中所示之基板120之一部分，其包含一單個穿孔140。如在圖2G中所示，移除基板材料121可曝露導電材料112以形成一第一端子110a。所得第一端子110a可具有大於穿孔140之一對應寬度W1之一寬度W2。因此，第一端子110a可包含用於連接至毗鄰結構之額外曝露表面積。一鈍化層128可然後設置於第二表面124上以在前述背向研磨操作之後保護第二表面124。
可端視基板120之特性選擇穿孔140及第一端子110a之尺寸以形成高度導電小型電路徑。舉例而言，對於一初始800μ厚基板120而言，穿孔140可經選擇以具有小於100μ(例如，50μ或25μ)之一深度D1。可背向研磨剩餘基板材料121，如上所述。寬度W1可係20μ或更小(例如，10μ或5μ)。
在圖2G中所示之一實施例之一特定態樣中，第一端子110a可具有與基板材料121之第二表面124大致齊平之一曝露導電表面118。因此，穿孔140及端子開口111中之所得導電結構119自第一表面123延伸穿過基板材料121到達第二表面124。在其他實施例中，可移除額外基板材料121以便進一步曝露第一端子110a之表面(例如)以形成一「凸塊」。舉例而言，圖2H圖解說明一第二端子110b，其係藉由自環繞第二端子110b之區域中之基板120之第二表面124移除額外材料形成。可使用一濕式蝕刻過程或一電漿乾式蝕刻過程(例如，藉助一SF6O2化學品)移除基板材料121。亦可移除此區域中之介電材料125。此過程可產生導電面向外表面113，該等導電面向外表面自穿孔軸V側向面向外，且以一漸縮方式遠離第二表面124軸向突出。因此，面向外表面113可增加可用於建立與毗鄰裝置之連接之第二端子110b之曝露表面積(相對於第二端子110b之橫截面積)。在其他實施例中，面向外表面113可突出或以其他方式軸向延伸至毗鄰裝置之結構中或在毗鄰裝置之結構上延伸以建立電連接及實體連接。
第二端子110b可包含除填充穿孔140之導電材料112以外的導電材料。舉例而言，第二端子110b可包含施加至曝露表面118之一薄鍍塗層114。薄鍍塗層114可促進與毗鄰裝置之電連接。在一特定實施例中，該薄鍍塗層可包含錫、金、銦或其他適合導電材料。一般而言，薄鍍塗層114可使用不需要使用一遮罩之一無電處理施加。
圖2I圖解說明亦包含除導電填充材料112以外的導電材料之一代表性第三端子110c。在此特定實施例中，額外材料可包含一焊料球115。焊料球115可接觸導電材料112之面向下曝露表面118以及面向外表面113。此配置可給予端子110c增加之表面積以供連接至毗鄰結構。由於焊料球115圍繞面向外表面113延伸，因此其可提供與導電材料112之增加之實體連續性及電連續性兩者。
圖2J示意性圖解說明包含電連接至一經堆疊配置中之一第二晶粒101b之一第一晶粒101a之一半導體總成100之一部分。晶粒101a、101b可包含藉助線131連接至接合墊132之掩埋微電子元件130(例如，電容器或電晶體)。接合墊132又電連接至穿孔140中之導電結構119。第一晶粒101a可包含在組態上大致類似於上文參照圖2G所述之彼等端子之第一端子110a。第二晶粒101b可包含在組態上大致類似於上文中參照圖2H所述之彼等端子之第二端子110b。兩個晶粒101a、101b可藉助第一端子110a接觸第二端子110b而組合在一起。在一個實施例中，個別第一端子110a之曝露表面118可接觸對應個別第二端子110b之曝露表面118。在另一實施例中，第一端子及第二端子110a、110b中之一者或兩者可包含接觸另一端子之一薄鍍塗層114(圖2H)。端子110a、110b可使用熱、壓力及/或其他形式之能量(例如，超音波能量)連接以使對應第一端子及第二端子110a、110b彼此熔合。舉例而言，可於不回流端子成分(例如，藉由施加壓力或組合有超音波能量之壓力)之情形下附接端子110a、110b。適合代表性過程包含超音波、熱音波及/或熱壓縮過程。在一個實施例中，第二端子110b可軸向突出超過第二晶粒101b之對應第二表面124以與第一晶粒101a之對應第一端子110a嚙合。在某些情形中，一間隙105可在該附裝過程完成之後保留於端子110a、110b之中的隙縫中之晶粒101a、101b之間。間隙105可(例如)在囊封經堆疊結構之前以一底填充材料或其他合適材料填充。在特定實施例中，所完整之總成可具有大致類似於圖1中所示之組態之一組態。
在圖2J中，第一及第二晶粒101a、101b經堆疊以使得第一端子110a之曝露表面118接觸第二端子110b之曝露表面118。在其他實施例中，晶粒101a、101b中之一者或兩者之相對定向可反轉。舉例而言，在一個實施例中，晶粒101a、101b兩者皆可反轉(與圖2J中所示之定向相比較)以使得第一晶粒101a之接合墊132接觸第二晶粒101b之對應接合墊132，且每一晶粒101a、101b之曝露表面118面向外(例如，在圖2J中向上並向下)。
在圖2K中所示之另一實例中，第二晶粒101b之定向相對於圖2J中所示之定向反轉，而第一晶粒101a保持其定向。因此，第一晶粒101a之曝露表面118接觸第二晶粒101b之 接合墊132。在特定實施例中，此定向可用於堆疊多於兩個晶粒。在其他實施例中，(例如)當該總成包含多於兩個經堆疊晶粒時，可組合上文參照圖2J至2K所述之前述定向。舉例而言，一第三晶粒可堆疊於圖2J中所示之第二晶粒101b之頂部上，其中第三晶粒端子之曝露表面與第二晶粒101b之接合墊132相接觸。
上文參照圖1至2K所述之前述實施例中之至少某些之一個特徵係穿過穿孔140之導電路徑可與在穿孔140之端部處形成端子110同時形成。因此，在穿孔140內且在端子110處之總體導電結構119可大致單一及均質。特定而言，相同導電材料可填充穿孔140及端子開口111，而不在總體結構119內形成一材料邊界。因此，當與在穿孔與對應接合墊之間具有邊界之現有結構相比較時，此過程可產生具有一增加之連續性之一總體導電結構119。因此，當與現有結構相比較時，此等結構可具有增加之可靠性。
另外，穿孔140及端子110可在無需在第二表面124處使用一遮罩/微影過程之情形下形成，該遮罩/微影過程通常用於在一穿孔之端部處形成一結合墊或凸塊。替代地，可使用較不耗時且較不昂貴的沈積及選擇性蝕刻過程來形成該結構。此又可減少形成導電材料119所需之時間量且因此其中形成穿孔之晶粒或其他產品之成本。
前述過程之至少某些實施例之另一特徵係無需在填充穿孔140之操作與形成端子110之操作之間重新對準半導體基板120。替代地，如上所論述，兩個結構皆可形成為相同操作之一部分。更進一步，如上所論述，穿孔140可使用產生非扇形、大致均勻扁平圓柱形壁之過程形成。舉例而言，可使用一連續各向異性蝕刻過程來產生穿孔140。因此，形成穿孔140可比使用交替蝕刻過程之穿孔消耗較少時間，且比產生成形及/或非均勻壁之過程可更有效地使用在基板120中可用之有限體積。
圖3A至3F根據本發明之進一步實施例圖解說明用於形成具有若干形狀之導電端子之代表性過程。首先參照圖3A，使用大致類似於上述彼等過程之過程在一基板120中形成一穿孔140。然後，可使用可形成除上述大致球形形狀以外的形狀之過程在穿孔140之底部處形成一端子開口311。舉例而言，可使用一各向異性蝕刻過程以與基板材料121之晶面對準之一方式來移除基板材料121，從而產生具有大致扁平側壁之一端子開口311。用於形成此等開口之代表性過程論述於de Boer等人(2000年3月)之先前以引用方式併入之論文中。
在圖3B中，已將一介電層125、一障壁層126及一可選種晶層127設置於穿孔140及端子開口311中。然後使用上文參照圖2F所述之前述過程中之任一者以一導電材料112填充穿孔140及端子開口311。然後移除來自基板120之第二表面124之材料以形成具有一曝露表面318之一第一端子310a。
圖3C圖解說明藉由以大致類似於上文參照圖2H所述方式之一方式移除額外基板材料121形成之一第二端子310b。因此，第二端子310b可包含突出超過第二表面124之面向外表面313。第二端子310b可包含一額外導電材料，例如，一薄鍍塗層(如上文參照圖2H所述)或一焊料球(如上文參照圖2I所述)。
圖3D圖解說明根據本發明之另一實施例組態之一第三端子310c。在此實施例中，已在移除端子開口311內之導電材料112中之任一者之前停止了背向研磨過程。已自在端子開口311中之導電材料112周圍選擇性地移除了基板材料121從而形成所圖解說明之結構。舉例而言，可將基板120曝露至擇優移除基板材料121(且可能係介電材料125及障壁層126)而不移除導電材料112且視情形種晶層127之一蝕刻劑。此配置可產生突出超過第二表面124一額外量之一第三端子310c，且在第三端子310c處提供一額外體積之導電材料112以供將基板120連接至毗鄰結構。
圖3E及3F根據本發明之另一實施例圖解說明用於形成一端子之另一過程。如在圖3E中所示，在某些情形中，施加至端子開口311及穿孔140之表面之導電材料112可在(例如)端子開口311中留下一空隙316。雖然在大多數半導體處理操作中通常不期望空隙，但可易於容許及/或計及圖3E中所示之空隙316。舉例而言，如在圖3F中所示，當自第二表面124移除基板材料121以露出曝露表面318時，亦曝露空隙316。視情形，然後可以一第二導電材料317填充空隙316。舉例而言，空隙316可以一薄鍍塗層填充或部分地填充，且空隙316之形狀及額外表面積可促進與該塗層之一強實體連接及電連接。在另一實施例中，空隙316可保持完整且可用於自一相鄰(例如，經堆疊)基板之一對應端子結構接收導電材料。舉例而言，空隙316可接收來自一相鄰基板之一焊料球或其他端子(例如，分別在圖2H、2I中所示之第二端子110b或第三端子110c)並與其連接。
圖4圖解說明用於在基板120中形成穿孔140之另一實施例。在此實施例中，將一保護層422施加至基板120之第一表面123，且施加至穿孔140之側壁表面141。在某些情形中，穿孔140可具有一高縱橫比(例如，一相對長的長度及/或相對小的寬度)，此可致使保護層422較附裝至端表面142更易於附裝至側壁表面141。因此，端表面142可幾乎不接收保護材料422。此配置可消除自端表面142移除保護層422之需要，且替代地，可在施加保護層422之後立即形成一端子開口。因此，期盼此過程之實施例減少形成導電端子所需之時間量，且從而可減少自基板120形成晶粒或其他最後產品之成本。
由根據上文參照圖1至4所述之方法結合基板所產生之半導體封裝中之任一者可併入至眾多較大及/或更複雜系統中，其一代表性實例係圖5中示意性地顯示之一系統500。系統500可包含：一處理器552、一記憶體554(例如，SRAM、DRAM、快閃記憶體及/或其他記憶體裝置)、輸入/輸出裝置556(例如，一感測器及/或傳輸器)及/或其他子系統或組件558。具有上文參照圖1至4所述之特徵中之任一者或一組合之半導體封裝可包含於圖5中所示之裝置中之任一者中。所得系統500可執行各種各樣的計算、處理、儲存、感測、成像及/或其他功能中之任一者。因此，代表性系統500可包含(但不限於)：電腦及/或其他資料處理器，例如，桌上型電腦、膝上型電腦、網際網路器具、手持式裝置(例如，掌上型電腦、可穿戴式電腦、蜂巢式電話或行動電話、個人數位系統、音樂播放器、相機等等)、多處理器系統、基於處理器或可程式化消費者電子裝置、網路電腦及微型電腦。其他代表性系統500可容納於一單個單元中或分佈於多個互連式單元上方(例如，透過一通信網路)。因此，系統500之組件可包含本端及/或遠端儲存裝置及各種各樣的電腦可讀媒體中之任一者。
自前述內容將瞭解，已出於圖解說明目的闡述了本發明之特定實施例，但前述系統及方法亦可具有其他實施例。舉例而言，雖然在具有兩個或三個經堆疊晶粒之半導體封裝之上下文中闡述了上述實施例中之某些實施例，但在其他實施例中，該等封裝可包含其他數目之經堆疊晶粒。在某些情形中，(例如)若基板形成圖1中所示之最頂部晶粒，則穿孔140可不完全延伸穿過該基板。在此等情形中，穿孔140仍可出於熱目的用於(例如)充當一熱導管或散熱片。可使用上文所述之相同過程來形成穿孔及端子，但不在該基板之第二表面處曝露該端子。此等基板亦可用於平坦(未經堆疊)晶粒。在其他實施例中，該端子可經曝露以將平坦(未經堆疊)晶粒連接至PCB或其他支撐構件或基板。用於形成前述經連接結構且連接不同半導體基板之配合結構之過程中之諸多過程可在晶粒級(例如，在單片化晶粒之後)、晶圓級(例如，在單片化晶粒之前)及/或在其他處理階段實施。
在其他實施例中，可組合或消除在特定實施例之上下文中所闡述之某些特徵。舉例而言，上文參照圖4所述之塗佈側壁表面之過程可應用於與在其他圖式中之任一者中所示之導電結構相關地形成之穿孔。如在圖3C及3D中所示，自整個端子開口周圍移除基板材料之過程可應用於在圖2E或2H中所示之端子開口。此外，雖然已在彼等實施例之上下文中闡述了與某些實施例相關之特徵及結果，但其他實施例亦可展現此等特徵及結果，且並非所有實施例皆必須要展現此等特徵及結果。因此，本發明可包含上文未明確顯示或描述之其他實施例。
100．．．半導體總成
101．．．半導體晶粒
101a．．．第一晶粒
101b．．．第二晶粒
102．．．支撐構件
103．．．囊封劑
104．．．封裝端子
105．．．間隙
106．．．封裝
107．．．支撐構件端子
110．．．晶粒端子
110a．．．第一端子
110b．．．第二端子
111．．．端子開口
112．．．導電材料
113．．．導電面向外表面
114．．．薄鍍塗層
118．．．曝露導電表面
119．．．單一導電材料結構
120．．．半導體基板
121．．．基板材料
122．．．保護層
123．．．第一主表面
124．．．第二主表面
125．．．介電層
126．．．障壁層
127．．．可選種晶層
128．．．鈍化層
130．．．掩埋微電子元件
131．．．線
132．．．接合墊
140．．．穿孔
141．．．側壁層
142．．．端表面
310a．．．第一端子
310b．．．第二端子
310c．．．第三端子
310d．．．第四端子
311．．．端子開口
313．．．面向外表面
316．．．空隙
317．．．第二導電材料
318．．．曝露表面
422．．．保護層
500．．．系統
552．．．處理器
554．．．記憶體
556．．．輸入/輸出裝置
558．．．子系統或組件
圖1係根據本發明之一實施例組態之一封裝之一局部示意性側面橫截面圖；
圖2A至2I係根據本發明之一實施例經歷處理之半導體基板之局部示意性側面橫截面圖；
圖2J係根據本發明之一特定實施例堆疊之兩個半導體基板之一局部示意性側面橫截面圖；
圖2K係根據本發明之另一實施例堆疊之兩個半導體基板之一局部示意性側面橫截面圖；
圖3A至3F係根據本發明之進一步實施例用於形成具有若干形狀之半導體基板端子之代表性方法之局部示意性側面橫截面圖；
圖4係根據本發明之一特定實施例用於將一保護層設置於一半導體基板上之一過程之一局部示意性側面橫截面圖；及
圖5係可包含根據本發明之數個實施例組態之一個或多個封裝之一系統之一示意性圖解說明。
100．．．半導體總成
101a．．．第一晶粒
101b．．．第二晶粒
105．．．間隙
118．．．曝露導電表面
119．．．單一導電材料結構
110a．．．第一端子
110b．．．第二端子
124．．．第二表面
128．．．鈍化層
130．．．掩埋微電子元件
131．．．線
132．．．接合墊

Claims (32)

  1. 一種用於形成一半導體總成之方法，其包括：在一半導體基板中形成一盲穿孔，該穿孔包含一側壁表面及一端表面；將一保護層施加至該穿孔之該側壁表面；藉由自該穿孔在該端表面處選擇性地移除基板材料同時保護免於移除該保護層施加於其上之基板材料來形成一端子開口；將一導電材料設置於該穿孔及該端子開口兩者中以形成與該穿孔中之導電材料形成整體之一導電端子；移除毗鄰於該端子之基板材料以曝露該端子；及將該端子電連接至該基板外部之一導電結構，其中該端子之該經曝露導電材料具有自該穿孔之該側壁表面突出側向向外且軸向超過該半導體基板之一最外表面之一最外邊界。
  2. 如請求項1之方法：其中設置一導電材料包含藉由在一穿孔設置過程期間將一無焊料導電材料設置於該穿孔中且在一端子設置過程期間將該無焊料導電材料設置於該端子開口中來形成一均質導電結構，而不在該穿孔設置過程與該端子設置過程之間相對於該導電材料之一源重新對準該半導體基板；其中於不自該側壁層移除基板材料之情形下執行自該穿孔在該端表面處移除基板材料之該過程； 其中該半導體基板包含一第一半導體晶粒，且其中將該端子電連接至一導電結構包含將該端子連接至一經堆疊配置中之一第二半導體晶粒，其中一個晶粒面朝向另一個晶粒；其中該穿孔沿一穿孔軸伸長；及其中該方法進一步包括於不使用一遮罩之情形下在鄰近該端子之該半導體基板之一表面上將一額外導電材料施加至該端子。
  3. 如請求項1之方法，其中該半導體基板具有一第一表面及背對該第一表面之一第二表面，且其中該穿孔自該第一表面延伸至該半導體基板中，進一步其中形成一導電端子包含於不在該第二表面處使用一遮罩之情形下形成該導電端子。
  4. 如請求項1之方法，其中設置一導電材料包含在一穿孔設置過程期間將該導電材料設置於該穿孔中且在一端子設置過程期間將該導電材料設置於該端子開口中，而不在該穿孔設置過程與該端子設置過程之間相對於該導電材料之一源重新對準該半導體基板。
  5. 如請求項1之方法，其中該半導體基板包含一半導體晶粒且其中將該端子電連接至一導電結構包含將該端子連接至一支撐構件。
  6. 如請求項1之方法，其中該半導體基板包含一第一半導體晶粒且其中將該端子電連接至一導電結構包含將該端子連接至一第二半導體晶粒。
  7. 如請求項1之方法，其中施加該保護層包含將該保護層施加至該側壁表面及該端表面兩者，且其中該方法進一步包括在形成該端子開口之前自該端表面移除該保護層。
  8. 如請求項1之方法，其中施加該保護層包含於不將該保護層施加至該穿孔之該端表面之情形下完成該保護層至該側壁表面之施加。
  9. 如請求項1之方法，其中該導電材料係一第一導電材料且其中該方法進一步包括在將該端子電連接至該導電結構之前將一第二導電材料施加至該第一導電材料。
  10. 如請求項9之方法，其中施加該第二導電材料包含施加一薄鍍塗層。
  11. 如請求項9之方法，其中施加該第二導電材料包含施加一焊料球。
  12. 如請求項11之方法，其中該穿孔沿一穿孔軸伸長，且其中移除基板材料包含曝露該端子之一側向面向外表面，且其中施加該焊料球包含施加該焊料球以使其接觸該端子之該曝露側向面向外表面。
  13. 如請求項1之方法，其中形成一端子開口包含形成具有沿該基板材料之晶面定位之大致扁平側之一端子開口。
  14. 如請求項1之方法，其中形成一端子開口包含形成一凹陷杯形開口。
  15. 如請求項1之方法，其中形成一穿孔包含形成具有大致平滑非扇形側壁之一穿孔。
  16. 如請求項1之方法，其中設置一導電材料包含設置具有至少90%之一純度之銅。
  17. 如請求項1之方法，其中電連接該端子包含於不回流該導電材料之情形下電連接該端子。
  18. 如請求項1之方法，其中該半導體基板具有一第一表面及背對該第一表面之一第二表面，其中該穿孔自該第一表面延伸至該半導體基板中，且其中：將一導電材料設置於該穿孔及該端子開口兩者中包含於不在該第二主表面處打通該端子開口之情形下設置該導電材料，其中該導電材料為至少實質上填充該穿孔及端子開口之一實質無焊料材料。
  19. 一種用於形成一半導體總成之方法，其包括：在一半導體基板之一第一主表面中形成一開口，該半導體基板具有面離該第一主表面之一第二主表面，該開口具有在該第一主表面處帶有第一寬度之一穿孔部分，該開口進一步具有在鄰近該第二主表面處帶有大於該第一寬度之一第二寬度之一端子部分，其中形成該開口包含在該第一主表面中形成一盲穿孔以定義該穿孔部分；將一保護層施加至該穿孔部分之一側壁；及藉由選擇性地移除在該穿孔部分之一端表面之基板材料同時保護免於移除該保護層施加於其上之基板材料來形成該端子部分；於不在該第二表面處使用一遮掩過程之情形下，且於 不在該第二主表面處打通該開口之情形下，將一導電材料於該穿孔部分及該端子部分處設置於該開口中，該導電材料係一均質無焊料材料；及自該第二主表面移除基板材料以曝露該導電材料之一側向面向外表面以定義一導電端子，其中該導電端子具有自該穿孔部分之該側壁突出側向向外且軸向超過背對該第一主表面之該半導體基板之一最外表面之一最外邊界。
  20. 如請求項19之方法，其中該半導體基板係一第一半導體基板，且其中該方法進一步包括相對於該第一半導體基板堆疊一第二半導體基板且將該第一半導體基板之該端子部分處之該導電材料電連接至該第二半導體基板之一端子。
  21. 一種半導體總成，其包括：一半導體基板，其包括一基板材料，該基板材料具有一第一主表面、一第二主表面及自該第一主表面延伸至該第二主表面之一開口，該開口包含大致垂直於該第一主表面延伸之一大致圓柱形部分，該圓柱形部分具有一大致平滑均勻表面，該開口進一步包含橫向於該圓柱形部分延伸且橫貫該第二主表面之一端子部分，該端子部分具有大致平行於該第一主表面之平面之一寬度，該寬度大於該圓柱形部分之一對應寬度；一單個均勻均質體積之導電材料，其設置於該開口之該圓柱形部分及該端子部分兩者中，該導電材料在該圓 柱形部分中形成一導電路徑且在該端子部分中形成一導電端子之至少一部份，該導電端子具有一凸面圓形之橫截面，其中該橫截面係以一垂直於該第二主表面之一平面截取，其中該凸面圓形導電端子自該第二主表面沿遠離該第一主表面之一方向遠離突出，該導電端子具有一第一橫截面積及一大於該第一橫截面積之第二橫截面積，其中該第一橫截面積在一大致平行於該第二主表面之第一平面中且包括該半導體基板之一最外表面且該第二橫截面積在一大致平行於該第一平面之第二平面中且處於超過該最外表面的位置；及一微電子元件，其形成於該基板材料中且電耦合至該導電材料。
  22. 如請求項21之總成：其中該等導電端子包括一無焊料材料；其中該導電端子之一外邊界沿遠離該第二主表面之一方向側向向外漸縮；且其中該總成進一步包括附裝至該導電端子之一焊料球，該焊料球與該導電端子之該漸縮外邊界相接觸。
  23. 如請求項21之總成，其中該導電端子在該端子部分處具有一最外邊界，該最外邊界具有大於該端子部分處該開口之一橫截面積之一橫截面積。
  24. 如請求項21之總成，其中該導電材料係一無焊料材料。
  25. 如請求項21之總成，其中該圓柱形部分不具有一呈扇形的內表面。
  26. 如請求項21之總成，其中該導電材料係至少90%銅。
  27. 如請求項21之總成，其中該導電端子之一外邊界沿遠離該半導體基板之該最外表面之一方向側向向外突出。
  28. 如請求項21之總成，其中該導電材料具有一凹陷杯形空隙。
  29. 如請求項21之總成，其中該基板材料形成一第一半導體晶粒之一部分，且其中該導電材料係至少90%銅且其中該半導體總成進一步包括一第二半導體晶粒，該第二半導體晶粒具有電連接至該第一半導體晶粒之該導電端子之一導電端子。
  30. 如請求項21之總成，其中該導電端子具有一大致呈扇形的形狀，其橫貫該基板材料之該第二主表面且超過該半導體基板之該最外表面。
  31. 如請求項21之總成，其中該端子部分具有與該半導體基板材料之晶面對準之大致扁平壁。
  32. 如請求項21之總成，其進一步包含：在該端子部分處之該導電材料之一外邊界上之一種晶層；及在該端子部分處之該種晶層之一外邊界上之一障壁層，其中該種晶層及該障壁層突出向外超過該半導體基板之該最外表面，且其中該導電端子包含該種晶層、該障壁層、及該導電材料。
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US8030780B2 (en) 2011-10-04
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US20170077067A1 (en) 2017-03-16
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