TWI387052B - 用於形成一穿透一半導體裝置結構之導電通孔之方法，用於製造一半導體裝置結構之方法，半導體裝置結構及電子裝置 - Google Patents

用於形成一穿透一半導體裝置結構之導電通孔之方法，用於製造一半導體裝置結構之方法，半導體裝置結構及電子裝置 Download PDF

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TWI387052B
TWI387052B TW098118448A TW98118448A TWI387052B TW I387052 B TWI387052 B TW I387052B TW 098118448 A TW098118448 A TW 098118448A TW 98118448 A TW98118448 A TW 98118448A TW I387052 B TWI387052 B TW I387052B
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semiconductor device
forming
conductive
device structure
substrate
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TW098118448A
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TW201010005A (en
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Chad A Cobbley
Jonathon G Greenwood
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Micron Technology Inc
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Description

用於形成一穿透一半導體裝置結構之導電通孔之方法，用於製造一半 導體裝置結構之方法，半導體裝置結構及電子裝置
本發明呈現各種實施例，大體而言係關於用於形成穿透半導體裝置結構之導電通孔的過程，且更具體言之，係關於在半導體裝置之第一表面上的主動組件之電互連之前或期間形成導電通孔之第一端及在已電互連該等主動組件之後形成導電通孔之第二端的過程。
本申請案主張正在申請中之於2008年6月3日申請之美國專利申請案第12/052,418號的權利，該案之揭示內容以全文引用之方式併入。
呈「穿透基板之通孔」(TSV)或「穿透晶圓之互連件」(TWI)的形式之導電通孔通常與半導體裝置之前側或主動表面上的電路互連，且延伸至在該半導體裝置之相對背面側上的可與主動表面上之電路建立電連接之位置(例如，至接觸襯墊，諸如，球形襯墊、促進晶粒與晶粒互連之襯墊、結合襯墊等)。TSV適用於組合呈緊密堆疊或三維(3D)配置之半導體裝置。
已開發出許多現有過程來製造結構化為穿透晶圓之互連件之導電通孔，以經由半導體裝置投送電信號。通常，視在半導體裝置製造期間實現此等過程之點而將其分為兩類。更具體言之，導電通孔製造過程之習知分類視在所謂的「線背面端」(BEOL)處理之前或期間還是在BEOL處理之後製造導電通孔而定。BEOL處理涉及半導體裝置之主動組件之互連，且包括介電層、導電互連件或插塞、導電跡線或佈線、及電極或接觸襯墊(半導體裝置可藉由其與其他電子組件外部連接)的製造。
在BEOL處理之前或期間製造之導電通孔通常具有約3μm至約5μm之直徑(或非圓柱形通孔之其他等效橫向尺寸)。使用當前之乾式蝕刻製程，可達成具有達約5:1之高度縱橫比(例如，直徑比深度)的通孔，此意謂通孔僅可延伸至正製造之半導體基板之主動表面中約25μm。遺憾地，使用當前之技術，僅25μm厚之此等製造基板不可支持許多類型之半導體裝置，包括動態隨機存取記憶體(DRAM)裝置。
可在BEOL處理之後製造長得多(例如，150μm)之導電通孔。此等導電通孔通常具有約3:1之高度縱橫比。因此，其直徑(或其他等效橫向尺寸)相對較大(例如，150μm長之通孔之直徑為約50μm)。因此，此等導電通孔在製造基板之主動表面上消耗不良的大量表面積或「實用區域(real estate)」，且不必要地限制或複雜化待製造於半導體裝置之主動表面上之積體電路的設計規則。
本發明之實施例包括用於製造延伸穿透製造基板之導電通孔的方法，該製造基板具有一適於支持製造於該基板之主動表面或前表面上之積體電路的厚度(例如，約6μm、約25μm、約35μm、約50μm、約100μm、約150μm等)而不會在該基板之主動表面上消耗不良的大量實用區域。參看圖1至圖7A描述此過程的實施例，其中圖1至圖3A描繪一或多個第一導電通孔端30(圖3及圖3A)之製造，且圖5至圖7A說明一或多個第二導電通孔端40(圖6及圖7A)之製造。
在圖1中，提供一包含一半導體材料且包括一載運複數個主動組件14(例如，電晶體、電阻器等)之主動表面12的製造基板10之示意性表示。在主動表面12中形成與主動組件14橫向偏移之至少一通孔或「第一通孔」20之第一端。在不限制本發明之範疇的情形下，可結合遮罩(例如，光罩)使用已知濕式蝕刻製程或乾式蝕刻製程(例如，反應性離子蝕刻或RIE)以自製造基板10之主動表面12移除材料。替代地，可使用雷射切除製程來形成一或多個第一通孔20。每一第一通孔20均為此材料移除之結果。在一些實施例中，跨越每一第一通孔20之距離(例如，其直徑)可為約3μm至6μm。在每一第一通孔20具有約5:1之高度縱橫比的實施例中，每一第一通孔20之深度可為約15μm至約30μm。
本發明包括在BEOL處理之前或期間(例如，作為其部分、與其同時進行等)製造第一通孔20及導電通孔之其他特徵中之一些特徵的實施例，在該BEOL處理中製造了互連主動組件14之導電元件(例如，接觸插塞、導電跡線、接觸襯墊等)。在此等實施例中，第一通孔20可與已藉由已知技術穿透介電薄膜16(例如，硼磷矽(BPSG)薄膜、磷矽(PSG)薄膜)而形成之孔18連通。
圖2描繪每一第一通孔20之表面21上之一或多個介電層22及視情況障壁層24的製造。介電層22可生長於(例如，未經摻雜之二氧化矽等)上、沈積至(例如，低K介電材料、氮化矽、氮氧化矽等)上或以其他方式塗覆至表面21上。在一些實施例中，可藉由已知合適沈積技術(諸如化學氣相沈積(CVD)(包括脈衝化學氣相沈積(PCVD)及原子層沈積(ALD))、物理氣相沈積(PVD)(例如，濺鍍))或其他導電薄膜形成技術在介電層22上製造一或多個障壁層24(例如，銅障壁、鋁障壁等)。
介電層22及其相關聯層(例如，障壁層24)中之全部層均具有小於跨越每一第一通孔20之距離的一半(例如，半徑)之組合薄膜厚度，以便留下開口25以用於在每一第一通孔20內接收導電材料。
在BEOL處理之前製造一或多個第一導電通孔端30(圖3及圖3A)之實施例中，介電層22及與其相關聯之任何可選層(包括障壁層24)可保持於製造基板10的主動表面12上，直至導電材料已被引入至每一第一通孔20(圖1)內之開口25(圖2)中後為止，如圖2中所展示。
可作為BEOL處理之部分或與其同時實現每一介電層22及障壁層24(若存在)之形成，在該BEOL處理中形成了用於導電互連件及/或導電跡線的相應介電薄膜及可選障壁。在作為BEOL處理之部分而沈積介電層22、任何障壁層24及任何其他相關聯層的情形下，可藉由已知技術圖案化此等層中之一或多者(若需要)。此等圖案化技術可包括(但不限於)遮罩及蝕刻製程，其中介電層22及/或介電薄膜16以及任何相關聯黏著或障壁層可經圖案化以形成暴露下伏結構27(例如，主動裝置或導電性摻雜區域、導電結構等)之孔26(例如，接觸孔)，如圖2A中所展示。下伏結構27之暴露使得能夠進行與該等下伏結構之後續電連接。
在其他實施例中，可研磨或平坦化(例如，藉由化學機械研磨或平坦化(CMP))介電層22及障壁層24(若存在)以及任何相關聯黏著層，如圖2B中所展示。
在已形成介電層22及任何其他可選層後，可將導電材料28(諸如，鋁、銅或任何其他合適TSV材料)引入至每一第一通孔20之剩餘物中(亦即，開口25(圖2)內)，如圖2至圖2B所說明。可使用已知技術(在各種非限制性實施例中，包括CVD及PVD製程)將導電材料28引入至每一第一通孔20中及製造基板10之其他位置上。在正作為BEOL處理之部分進行此處理的實施例中(如圖2A及圖2B中所描繪)，亦可引入導電材料28以使其與任何先前製造之結構27(例如，主動裝置或導電性摻雜區域、導電結構等)接觸。
如圖3說明，在BEOL處理之前進行第一導電通孔端30之處理的實施例中，可藉由已知技術(包括但不限於研磨或平坦化製程)自製造基板10之主動表面12完全移除導電材料28及位於導電材料28與基板10之上述主動表面12之間的任何層(例如，介電層22、障壁層24等)。當同時實現第一導電通孔端30處理及BEOL處理時(如圖2A及圖2B中所展示)，可使用已知技術自位於製造基板10之主動表面12上之導電材料28(圖2A及圖2B)圖案化導電結構(諸如，所描繪之導電插塞29P及導線29L)。由圖3及圖3A中所展示之過程產生一或多個第一導電通孔端30。
一旦已製造出第一導電通孔端30，便可完成BEOL處理，如此項技術中已知且如圖4中所展示。
一旦已完成主動表面12上之積體電路及其保護層之製造，便可藉由自製造基板10之背面側13移除材料來減小該製造基板10之厚度(亦即，可薄化製造基板10)。可使用濕式蝕刻劑藉由已知技術(諸如，背面研磨製程)或此項技術中已知之其他技術自背面側13移除材料。在一些實施例中，可將製造基板10之厚度自約700μm至約800μm之初始厚度減小至約150μm或更小(例如，120μm、100μm等)之成品厚度(不包括製造於主動表面12上或上覆主動表面12之任何結構的厚度)。在圖5中以倒置定向展示所得結構。
繼續參看圖5，處理繼續進行至自製造基板10之背面側13製造第二導電通孔端40(圖6至圖6B)。
最初，在背面側13中形成一或多個第二通孔32。可在能夠與單一對應第一導電通孔端30連通(如圖5中所展示)或與複數個對應第一導電通孔端30連通(如圖5A中所展示)之位置處形成每一第二通孔32。除用於其他可能目的外，後一實施例尤其適用於經由背面側13處之電極將功率傳遞至由主動表面12所載運之積體電路。單一第二導電通孔端40與複數個第一導電通孔端30之連接可減少用於特定目的(例如，功率傳遞)所需要的接觸襯墊(例如，球形襯墊、促進晶粒與晶粒互連之襯墊、結合襯墊等)之數目，此情況可使得能夠減小併有此特徵之半導體裝置的整體大小。
可藉由此項技術中已知之任何合適技術在背面側13中形成一或多個第二通孔32(一或多個第一導電通孔端30暴露於其每一者)。在一些實施例中，可藉由雷射切除形成每一第二通孔32。在其他實施例中，可使用已知遮罩(例如，光罩)及蝕刻(例如，濕式蝕刻、乾式蝕刻等)製程在穿透基板10之背面側13之所要位置處形成一或多個第二通孔32。在各種實施例中，在不限制本發明之範疇之情形下，每一所得第二通孔32可具有小至約3:1或甚至小至約2:1的高度縱橫比。在更多特定實施例中，跨越一延伸至基板10之背面側13中約80μm至約90μm之第二通孔32的距離(例如，其直徑)可為約50μm。因為跨越每一第二通孔32之距離(例如，其直徑)可比跨越對應第一通孔20(或若干通孔20)(對應第一導電通孔端30位於其中)之對應距離大得多，所以第二通孔32將未與其對應第一通孔20(或若干通孔20)對準之可能性顯著降低。
在形成每一第二通孔32後，其表面33可塗覆有一或多個材料層，如圖6至圖6B中所展示。包括於此等材料層中者為一或多個介電層34。介電層34可生長於(例如，未經摻雜之二氧化矽等)上、沈積至(例如，低K介電材料、氮化矽、氮氧化矽等)上或以其他方式塗覆至表面33。在一些實施例中，可藉由已知合適沈積技術(諸如CVD、PVD)或其他導電薄膜形成技術在介電層34上製造一或多個障壁層35(例如，銅障壁、鋁障壁等)。在一些實施例中，亦可在每一第二通孔32之表面33上製造可使得能夠使用一或多個所要類型之介電及/或障壁材料的一或多個可選黏著層。
繼續參看圖6至圖6B，可將導電材料37引入至每一第二通孔32中。當將導電材料37引入至每一第二通孔32中時，在一些實施例中亦可將導電材料37引入於基板10之背面側13上。在其他實施例中，可在基板10之處理期間之稍遲點處，在基板10的背面側13之至少部分上(例如，在每一第二通孔32內之材料上)形成一導電材料塗層，如圖6B中所展示之實施例。
在一些實施例中，在已形成介電層34及障壁層35及任何其他可選層(諸如，電鍍晶種層)後，可以完全或大體上填充保持於第二通孔32內之開口的方式將導電材料37引入至每一第二通孔32中。在其他實施例中，導電材料37可僅內襯或塗覆保持於每一第二通孔32內之開口36之表面。導電材料37填充每一開口之程度至少部分地取決於所使用之導電材料引入技術。
可使用各種已知技術將導電材料37引入至保持於每一第二通孔32內之開口中。此等導電材料引入過程包括(但不限於)電鍍過程(例如，無電極電鍍、浸漬式電鍍、電解電鍍等)、CVD、PVD、將導電膏(例如，金屬膏、焊錫膏、膏或另一焊錫合金等)施加至每一開口中、接著回焊該導電膏、將熔融導電材料(例如，熔融金屬、熔融焊錫、另一熔融合金等)引入至每一開口中、接著允許其凝固、將可流動導電聚合物或填充有導體之聚合物引入至每一開口中、接著將其固化或以其他方式使其或允許其凝固)，以及用於將導電材料37引入至盲端通孔中之任何其他合適技術。在將導電材料37引入至每一開口中後，形成一第二導電通孔端40。在一些實施例中，亦可在基板10之背面側13上形成導電層42。
在將導電材料37引入至開口36中後保持於第二通孔32內之任何空間可保持開放(見圖6B)或完全或部分地填充有另一材料(例如，額外導電材料、電絕緣材料、導熱材料等)(見圖6及圖6A)。
繼續參看圖6至圖6B，在一些實施例中，可藉由已知技術移除或圖案化跨越基板10之背面側13延伸之任何導電層37(以及任何下伏障壁層35等)及可能的任何下伏層(例如，介電層34等)。合適移除過程包括(但不限於)CMP及濕式蝕刻製程，從而產生諸如圖7及圖7A中所展示之實施例之半導體裝置結構。圖案化技術包括(但不限於)遮罩及蝕刻製程，從而(在一些實施例中)產生包括諸如背面側13上之導電跡線44及電極46(存在於圖6至圖6B中所描繪之實施例中)之導電特徵的半導體裝置結構。
若需要，則可藉由已知技術在每一第二導電通孔端40(圖7)或對應電極46(圖6及圖6A)上形成凸塊下金屬化(UBM)或限制焊球冶金(BLM)。
在圖6、圖6A、圖6B及圖7所展示之實施例中，UBM或BLM可在基板10之背面側13上形成一或多個接觸襯墊48(在本文中亦被稱為「底部接觸襯墊」)。每一接觸襯墊48促進離散導電元件50(圖6至圖6B)或橫向延伸之中間導電元件52(圖7)與對應第二導電通孔端40(圖7)或電極46之電連接(例如，在接觸襯墊48上形成離散導電元件50、確保離散導電元件50或橫向延伸之中間導電元件52接觸襯墊48等)(圖6至圖6B)。
在其他實施例(諸如圖7A中所展示之實施例)中，可在內襯背面側13中之一或多個開口36之表面的導電材料37上形成UBM或BLM，以在該導電材料37上提供黏著層48'。黏著層48'黏著至一已經引入至彼開口之離散導電元件50並在離散導電元件50與導電材料37之間建立電連通。
在不限制本發明之範疇的情形下，每一離散導電元件50可包含一由合適導電材料(諸如，焊料、另一金屬或金屬合金、導電聚合物或填充有導體之聚合物或其類似者)形成之球、凸塊、柱、桿、管柱、針或其他結構。中間導電元件52包括(但不限於)結合線、引線(包括晶片上引線(LOC)類型之引線(如在捲帶式自動結合(TAB)類型之配置中的由可撓性介電材料載運之導電元件)、熱壓引線等)及其類似者。
可經緊固至底部接觸襯墊48、黏著層48'之離散導電元件50及/或中間導電元件52、或頂部接觸襯墊49可將根據本發明之半導體裝置100、100'、100''、100'''(分別在圖6至圖7A中)電連接至另一電子組件(諸如，載體基板(例如，電路板、插入器、可撓性基板等)引線)或另一半導體裝置。
已根據本發明之一或多個實施例製造之半導體裝置100、100'、100''、100'''包括一具有一厚度(例如，約100μm至約150μm)之基板10，該厚度為已製造於主動表面12上之積體電路提供適當結構支持。半導體裝置100、100'、100''、100'''之導電通孔端30/40使得能夠使用背面側13上的接觸襯墊48、48'及中間導電元件50、52以與由主動表面12所載運之積體電路進行電連通，而不會佔用主動表面12上之重要面積或實用區域且因此不會減小主動表面12上之積體電路的最佳密度。
在一些實施例中，可由基板10之背面側13載運半導體裝置結構100、100'、100''、100'''之所有接觸襯墊48。在半導體裝置結構100、100'、100''、100'''之接觸襯墊48中之全部均位於基板10之背面側13上的實施例中，不需要將其定位於主動表面之「盲」區上，此情況釋放用於積體電路的在主動表面12上之額外面積或實用區域且增加可用電路設計之數目。
在其他實施例中，頂部接觸襯墊49可位於基板10之主動表面12上，而與該頂部接觸襯墊連通同一電路之另一對應底部接觸襯墊48由背面側13載運。僅可經由頂部接觸襯墊或僅可經由底部接觸襯墊實現測試或預燒，從而保留另一接觸襯墊組以用於將半導體裝置100、100'、100''、100'''連接至其他電子組件(諸如，引線、電路板或其類似者)。
此外，當接觸襯墊48定位於背面側13上時，該等接觸襯墊48亦與主動表面12上之積體電路分隔基板10之厚度而非薄得多的介電層(該等介電層原本隔開位於主動表面12上之結合襯墊與積體電路)。因此，當施加壓力至由背面側13載運之接觸襯墊48(可能發生於測試及/或預燒過程期間，其中將探針元件按壓於與接觸襯墊相抵)時，損壞積體電路之可能可降低。
對於一般熟習此項技術者而言，本發明之各種實施例之許多其他優勢將亦為顯而易見的。與穿透基板形成相對大直徑之通孔的習知穿透晶圓過程相比而言，此等優勢可包括(但不限於)：最小化污染、且使互連處理實體遠離半導體裝置電路；且因此最小化或消除對電路(及對半導體基板)之損壞及由導電通孔引發的對半導體裝置之鄰近電路之應力。此外，可藉由使用僅部分延伸穿透基板之大直徑通孔來減小由完全延伸穿透半導體裝置之多列通孔引發的對基板之應力以及由於基板與完全延伸穿透基板之導電通孔之材料的熱膨脹係數(CTE)失配而產生之應力。自半導體基板之主動表面所載運之電路區域消除至少一些相對大直徑的導電通孔亦可放鬆設計規則及/或使得能夠改良配置此等電路之密度。此外，與完全穿透半導體裝置延伸之具有可比直徑之導電通孔相比，僅部分延伸穿透基板之大直徑導電通孔可較快速地形成，且歸因於其較小縱橫比更快速且更可靠地接收導電材料。此外，在半導體裝置之背面側處包括大直徑導電通孔可使得能夠使用標準總成設備以在背面側上形成再分布電路，而歸因於此設備識別較小直徑、緊密配置之導電通孔的有限能力，使用小直徑之導電通孔將不可能形成再分布電路。當與使用習知製程形成完全穿透半導體裝置之導電通孔時可達成的工業可調能力、產品產量及可靠性相比時，此等預期優勢中之任一者可導致改良之工業可調能力、產品產量及可靠性。
現轉至圖8，描繪包括至少一半導體裝置100、100'、100''、100'''之電子裝置200(諸如，電腦、控制器、蜂巢式電話、攜帶型數位音樂播放器、數位相機或其類似者)，該至少一半導體裝置100、100'、100''、100'''包括根據本發明之實施例的一或多個通孔110(見圖6至圖7B)。
總之，本發明包括具有一或多個導電通孔之半導體裝置，該一或多個導電通孔包括一延伸至製造基板之主動表面中的相對小直徑之部分及一延伸至製造基板之背面側中的對應的相對大直徑之部分。在一些實施例中，可藉由在BEOL處理之前或期間形成相對小直徑部分而可在完成BEOL處理之後製造每一導電通孔的大直徑部分來製造此類型之導電通孔。亦揭示包括具有此等導電通孔之一或多個半導體裝置之電子裝置。
雖然前述描述含有許多細節，但此等細節不應被解釋為限制本發明之範疇，而是僅解釋為提供一些實施例之說明。類似地，可設計處於本發明之範疇內的本發明之其他實施例。可結合使用來自不同實施例之特徵。因此，本發明之範疇僅由附加之申請專利範圍及其合法等效物來指示及限制，而非由前述描述來指示及限制。藉此，待涵蓋落入申請專利範圍之意義及範疇內的對如本文中所揭示之本發明之所有添加、刪除及修改。
10‧‧‧基板
12‧‧‧主動表面
13‧‧‧背面側
14‧‧‧主動組件
16‧‧‧介電薄膜
18‧‧‧孔
20‧‧‧第一通孔
21‧‧‧表面
22‧‧‧介電層
24‧‧‧障壁層
25‧‧‧開口
26‧‧‧孔
27‧‧‧結構
28‧‧‧導電材料
29L‧‧‧導線
29P‧‧‧導電插塞
30‧‧‧第一導電通孔端
32‧‧‧第二通孔
33‧‧‧表面
34‧‧‧介電層
35‧‧‧障壁層
36‧‧‧開口
37‧‧‧導電材料
40‧‧‧第二導電通孔端
42‧‧‧導電層
44‧‧‧導電跡線
46‧‧‧電極
48‧‧‧接觸襯墊
48'‧‧‧黏著層
49‧‧‧頂部接觸襯墊
50‧‧‧導電元件
52‧‧‧導電元件
100‧‧‧半導體裝置
100'‧‧‧半導體裝置
100"‧‧‧半導體裝置
100'''．．．半導體裝置
110．．．通孔
200．．．電子裝置
圖1至圖3A描繪用於在BEOL處理之前或期間在一製造基板的主動表面中形成導電通孔之第一端之過程的實施例；圖4展示包括導電通孔之至少一第一端且已經受BEOL處理的半導體裝置結構之實施例；圖5至圖7A說明用於在一半導體裝置之基板的背面側中形成導電通孔之第二端之過程的實施例；及圖8示意性地描繪根據本發明之實施例的包括一具有至少一通孔之半導體裝置的電子裝置。
10‧‧‧基板
12‧‧‧主動表面
13‧‧‧背面側
30‧‧‧第一導電通孔端
33‧‧‧表面
34‧‧‧介電層
35‧‧‧障壁層
36‧‧‧開口
37‧‧‧導電材料
40‧‧‧第二導電通孔端
42‧‧‧導電層
44‧‧‧導電跡線
46‧‧‧電極
48‧‧‧接觸襯墊
49‧‧‧頂部接觸襯墊
50‧‧‧離散導電元件
100‧‧‧半導體裝置
110‧‧‧通孔

Claims (20)

  1. 一種形成一穿透一半導體裝置結構之導電通孔之方法，其包含：在一包含一半導體材料之製造基板之一主動表面處形成主動組件；形成至少一第一通孔至該主動表面中；在製造互連電路以互連該等主動組件之同時將導電材料引入至該至少一第一通孔中；在製造該互連電路後從該製造基板之一背面側薄化該製造基板；在已薄化該製造基板後形成一第二通孔至該製造基板之該背面側中，該第二通孔具有一大於一第一端之直徑且與該第一端連通；及將導電材料引入至該第二通孔中且與該至少一第一通孔內之導電材料接觸。
  2. 如請求項1之方法，其中：形成該至少一第一通孔包含形成複數個第一通孔；且形成該第二通孔包含形成與該複數個第一通孔連通之該第二通孔。
  3. 如請求項1之方法，其中形成該至少一第一通孔係在製造該等主動組件後進行。
  4. 一種製造一半導體裝置結構之方法，其包含：形成至少一第一通孔至一包含一半導體材料之製造基板之一主動表面中； 在形成該至少一第一通孔之後或同時，製造至在該製造基板之該主動表面處之主動組件的導電元件；及在製造導電元件後，形成一第二通孔至該製造基板之一背面側中以與該至少一第一通孔之一第一端連通。
  5. 如請求項4之方法，其中製造導電元件包含製造接觸插塞、線路及接觸襯墊中之至少一者。
  6. 如請求項4之方法，其進一步包含：將導電材料引入至該至少一通孔之至少一部分中。
  7. 如請求項6之方法，其中引入包括在互連該等主動組件之同時將導電材料引入至該至少一第一通孔中。
  8. 如請求項6之方法，其中引入包括以下各者中之至少一者：用導電材料電鍍該第二通孔之一表面；將導電材料沈積至該第二通孔之該表面上；及將熔融導電材料引入至該第二通孔中。
  9. 如請求項4之方法，其中形成該第二通孔包含形成一具有一大於該至少一第一通孔之橫向尺寸的第二通孔。
  10. 如請求項4之方法，其中形成該第二通孔包含形成一具有一大於該至少一第一通孔之一長度之長度的第二通孔。
  11. 如請求項4之方法，其進一步包含：在形成該第二通孔至該製造基板之該背面側中之前自該製造基板之該背面側移除材料。
  12. 一種藉由如請求項1至11中任一項之方法製造之半導體裝置結構，該半導體裝置結構包含： 一基板，其包含一半導體材料且包括：一主動表面，其載運主動組件；及一背面側；至少一通孔，其包括：一至少一第一通孔，其延伸至該主動表面中；及一第二通孔，其與該至少一第一通孔對準，延伸至該背面側中且與該至少一第一通孔連通；及互連電路及至少一用於互連電路之絕緣層中之至少一者，二者定位於該至少一第一通孔上方。
  13. 如請求項12之半導體裝置結構，其中該至少一第一通孔具有一至多約6 μm之直徑。
  14. 如請求項13之半導體裝置結構，其中該至少一第一通孔延伸至該主動表面中至多約30 μm。
  15. 如請求項12之半導體裝置結構，其中該第二通孔具有一至多約50 μm之直徑。
  16. 如請求項12之半導體裝置結構，其中該第二通孔延伸至該背面側中至多約150 μm。
  17. 如請求項12之半導體裝置結構，其進一步包含：一導電材料，其延伸穿透該至少一通孔。
  18. 如請求項17之半導體裝置結構，其包含與在該至少一第一通孔內之該導電材料的至少一第一端整合之互連電路。
  19. 如請求項17之半導體裝置結構，其中在該至少一通孔之該第二通孔內或鄰近於該至少一通孔之該第二通孔的該 導電材料之至少一端包含焊料。
  20. 一種電子裝置其包含：如請求項12至19中任一項之至少一半導體裝置結構。
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