JP5209075B2 - 電子デバイス及びその製造方法 - Google Patents
電子デバイス及びその製造方法 Download PDFInfo
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- JP5209075B2 JP5209075B2 JP2011056556A JP2011056556A JP5209075B2 JP 5209075 B2 JP5209075 B2 JP 5209075B2 JP 2011056556 A JP2011056556 A JP 2011056556A JP 2011056556 A JP2011056556 A JP 2011056556A JP 5209075 B2 JP5209075 B2 JP 5209075B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
- H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Description
本発明本発明の他の目的、構成及び利点については、添付図面を参照し、更に詳しく説明する。但し、添付図面は、単なる例示に過ぎない。
2 縦導体
20 縦孔
3 絶縁物充填層
Claims (6)
- 半導体基板と、絶縁物充填層と、縦導体とを含む電子デバイスであって、
前記半導体基板は、その厚み方向に貫通する縦孔を有しており、
前記絶縁物充填層は、前記縦孔内にその内周面を覆うように充填してなる環状層であって、ガラスを主成分とする無機絶縁物と、セラミックとからなり、前記セラミックを含有する液状ガラスを充填し硬化させたものでなり、
前記セラミックは、ナノコンポジット構造を有し、常温比抵抗が1014Ω・cmを超え、比誘電率が4〜9の範囲にあり、
前記縦導体は、前記絶縁物充填層によって囲まれ、前記絶縁物充填層を貫通する領域内に充填された金属体でなる、
電子デバイス。 - 請求項1に記載された電子デバイスであって、更に、電磁シールド層を含み、前記電磁シールド層は、前記絶縁物充填層の層厚の中間部に埋設され、前記縦導体の周りを包囲している、電子デバイス。
- 請求項1又は2に記載された電子デバイスであって、三次元システム・パッケージ(3D-SiP)である、電子デバイス。
- 請求項1乃至3の何れかに記載された電子デバイスであって、発光ダイオードを含む、電子デバイス。
- 請求項1乃至4の何れかに記載された電子デバイスの製造方法であって、
半導体基板を含む基板に、その厚み方向に向かう縦孔を形成し、
前記縦孔の内部に絶縁物を充填し硬化させ、前記絶縁物は、ガラスを主成分とする無機絶縁物と、セラミックとからなり、前記ガラスは液状ガラスであり、前記セラミックは、常温比抵抗が1014Ω・cmを超え、比誘電率が4〜9の範囲にあり、
前記絶縁物に縦孔を形成し、
前記絶縁物の前記縦孔内に溶融金属を充填する、
工程を含む電子デバイスの製造方法。 - 請求項1乃至4の何れかに記載された電子デバイスの製造方法であって、
半導体基板を含む基板に、その厚み方向に向かう縦孔を形成し、
前記縦孔の内部に絶縁物を充填し硬化させ、前記絶縁物は、ガラスを主成分とする無機絶縁物と、セラミックとからなり、前記ガラスは、液状ガラスであり、前記セラミックは、常温比抵抗が1014Ω・cmを超え、比誘電率が4〜9の範囲にあり、
前記絶縁物に第1縦孔を形成し、
前記絶縁物の前記第1縦孔の内壁面に、電磁シールド膜を形成し、
前記電磁シールド膜によって囲まれた第2縦孔内に、更に第2絶縁物を充填し、
前記第2絶縁物に第3縦孔を形成し、
前記第2絶縁物の前記第3縦孔内に溶融金属を充填する、
工程を含む電子デバイスの製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011056556A JP5209075B2 (ja) | 2010-05-21 | 2011-03-15 | 電子デバイス及びその製造方法 |
US13/106,933 US9685394B2 (en) | 2010-05-21 | 2011-05-13 | Electronic device and manufacturing method therefor |
TW100117549A TWI422003B (zh) | 2010-05-21 | 2011-05-19 | 電子裝置及其製造方法 |
EP11250541.7A EP2388814B1 (en) | 2010-05-21 | 2011-05-20 | Electronic device and manufacturing method therefor |
CN201110132426.9A CN102254896B (zh) | 2010-05-21 | 2011-05-20 | 电子器件及其制造方法 |
KR1020110047695A KR101368524B1 (ko) | 2010-05-21 | 2011-05-20 | 전자 디바이스 및 그 제조방법 |
HK12102996.6A HK1162746A1 (en) | 2010-05-21 | 2012-03-27 | Electronic device and manufacturing method therefor |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010117008 | 2010-05-21 | ||
JP2010117008 | 2010-05-21 | ||
JP2011056556A JP5209075B2 (ja) | 2010-05-21 | 2011-03-15 | 電子デバイス及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012009820A JP2012009820A (ja) | 2012-01-12 |
JP5209075B2 true JP5209075B2 (ja) | 2013-06-12 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011056556A Expired - Fee Related JP5209075B2 (ja) | 2010-05-21 | 2011-03-15 | 電子デバイス及びその製造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9685394B2 (ja) |
EP (1) | EP2388814B1 (ja) |
JP (1) | JP5209075B2 (ja) |
KR (1) | KR101368524B1 (ja) |
CN (1) | CN102254896B (ja) |
HK (1) | HK1162746A1 (ja) |
TW (1) | TWI422003B (ja) |
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2011
- 2011-03-15 JP JP2011056556A patent/JP5209075B2/ja not_active Expired - Fee Related
- 2011-05-13 US US13/106,933 patent/US9685394B2/en active Active
- 2011-05-19 TW TW100117549A patent/TWI422003B/zh not_active IP Right Cessation
- 2011-05-20 KR KR1020110047695A patent/KR101368524B1/ko active IP Right Grant
- 2011-05-20 CN CN201110132426.9A patent/CN102254896B/zh active Active
- 2011-05-20 EP EP11250541.7A patent/EP2388814B1/en not_active Not-in-force
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2012
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Also Published As
Publication number | Publication date |
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CN102254896B (zh) | 2014-12-31 |
EP2388814A2 (en) | 2011-11-23 |
EP2388814B1 (en) | 2017-10-18 |
US20110284912A1 (en) | 2011-11-24 |
EP2388814A3 (en) | 2014-04-23 |
JP2012009820A (ja) | 2012-01-12 |
CN102254896A (zh) | 2011-11-23 |
KR101368524B1 (ko) | 2014-02-27 |
KR20110128247A (ko) | 2011-11-29 |
US9685394B2 (en) | 2017-06-20 |
TW201214646A (en) | 2012-04-01 |
HK1162746A1 (en) | 2012-08-31 |
TWI422003B (zh) | 2014-01-01 |
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