JP5124693B1 - 電子機器 - Google Patents

電子機器 Download PDF

Info

Publication number
JP5124693B1
JP5124693B1 JP2012098837A JP2012098837A JP5124693B1 JP 5124693 B1 JP5124693 B1 JP 5124693B1 JP 2012098837 A JP2012098837 A JP 2012098837A JP 2012098837 A JP2012098837 A JP 2012098837A JP 5124693 B1 JP5124693 B1 JP 5124693B1
Authority
JP
Japan
Prior art keywords
melting point
point metal
metallized
metal component
synthetic resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012098837A
Other languages
English (en)
Other versions
JP2013229376A (ja
Inventor
重信 関根
由莉奈 関根
Original Assignee
有限会社 ナプラ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2012098837A priority Critical patent/JP5124693B1/ja
Application filed by 有限会社 ナプラ filed Critical 有限会社 ナプラ
Publication of JP5124693B1 publication Critical patent/JP5124693B1/ja
Application granted granted Critical
Priority to US13/859,175 priority patent/US20130277850A1/en
Priority to SG2013026984A priority patent/SG194295A1/en
Priority to EP13275090.2A priority patent/EP2657962A1/en
Priority to KR1020130043756A priority patent/KR101355748B1/ko
Priority to TW102113877A priority patent/TWI529853B/zh
Priority to CN2013101444077A priority patent/CN103378051A/zh
Publication of JP2013229376A publication Critical patent/JP2013229376A/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/20—Conductive material dispersed in non-conductive organic material
    • H01B1/22—Conductive material dispersed in non-conductive organic material the conductive material comprising metals or alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/06—Arrangements of circuit components or wiring on supporting structure on insulating boards, e.g. wiring harnesses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/033—Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0331—Manufacturing methods by local deposition of the material of the bonding area in liquid form
    • H01L2224/0332—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0341—Manufacturing methods by blanket deposition of the material of the bonding area in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05199—Material of the matrix
    • H01L2224/052—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05205—Gallium [Ga] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05199—Material of the matrix
    • H01L2224/052—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05209—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05199—Material of the matrix
    • H01L2224/052—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05211—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05199—Material of the matrix
    • H01L2224/052—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05213—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05317—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05318—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05317—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05324—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05347—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05355—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/0536—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05366—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
    • H01L2224/05299—Base material
    • H01L2224/053—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05369—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/0569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8136—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/81375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81395—Bonding interfaces outside the semiconductor or solid-state body having an external coating, e.g. protective bond-through coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499—Material of the matrix
    • H01L2224/815—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81501—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81505—Gallium [Ga] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499—Material of the matrix
    • H01L2224/815—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81501—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81509—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499—Material of the matrix
    • H01L2224/815—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81501—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81511—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499—Material of the matrix
    • H01L2224/815—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81501—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81513—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81617—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81618—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81617—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/81624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/8166—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81663—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/81498—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598—Fillers
    • H01L2224/81599—Base material
    • H01L2224/816—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81663—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/81669—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Sustainable Development (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Sustainable Energy (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Dispersion Chemistry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Non-Insulated Conductors (AREA)
  • Led Device Packages (AREA)

Abstract

【課題】メタライズ配線に外部導体や電子部品を接続する際、耐酸化性を確保するとともに、両者間の電気的導通を確実に確保し得る電気機器を提供すること。
【解決手段】基板１１は、メタライズ配線１２を有している。メタライズ配線１２は、メタライズ層１２１と、合成樹脂膜１２２とを含んでいる。メタライズ層１２１は、高融点金属成分と低融点金属成分とを含み、高融点金属成分及び低融点金属成分が互いに拡散接合している。合成樹脂膜１２２は、メタライズ層１２１の表面を覆い、膜厚が５ｎｍ〜１０００ｎｍの範囲にある。
【選択図】図２

Description

本発明は、電子機器、即ち、電子工学の技術を応用した電気製品に関する。
電子機器は、周知のように、基板の一面上に、所定のパターンを有する配線パターンを形成し、この配線パターン上に能動部品や受動部品等の電子部品をはんだ付けする。配線パターンは、基板上に予め形成されているＣｕ箔に、エッチング・レジストを塗布した後、Ｃｕ箔をフォト・リソグラフィ工程によってパターン化することによって得られる。配線パターンのうち、電子部品をはんだ付けするのに必要な部分だけ、Ｃｕ箔が露出し、はんだ付けの不要な部分にはんだが付かないように、基板上に熱硬化性エポキシ樹脂などでなるソルダ・レジスト皮膜を形成する。そして、露出したＣｕ箔に電子部品をはんだ付けする。
このように、従来の電子機器では、銅貼基板の準備、エッチング・レジスト塗布工程、フォト・リソグラフィ工程、ソルダ・レジスト塗布工程及び部品実装工程という多数の工程を経て製造しなければならなかった。このため、コスト低減や、量産性向上に限界があった。
上述した手法とは異なって、基板上に、導電ペーストを直接にスクリーン印刷する手法がとられることもある。このときに用いられる導電性ペーストは、導電成分となる金属粉末又は合金粉末を、有機ビヒクル中に分散させたものである。有機ビヒクルは、熱硬化性樹脂、又は、熱可塑性樹脂などの樹脂及び溶剤を含んでいる。場合によっては、金属粉末の分散性向上、或いは、難燃性確保のために、第３成分が添加されることもある。
こうして得られた配線パターンは、樹脂中に金属粉末が分散した構成になる。このため、金属導体そのものによる場合と比較して、導電性が悪くなる。
そこで、導電性を向上させるために、粒径の小さい金属粉末を用いて、充てん率を増加させることが考えられる。しかし、金属粉末は、粒径の小さいほど凝集しやすいため、導電性ペースト中に均一に分散させるのが難しい。また、隣り合う金属粒子間の接触部分が増加して、接続抵抗が増加する分、充てん率の増加に見合う導電性向上の効果が得られない。
上記金属粉末として、銀粉またはＣｕ粉を用いると、導電性の良好な配線が得られることが知られている。しかし、銀粉を含有する導電性ペーストは、高温多湿の雰囲気下で電界が印加されると、電気回路や電極にマイグレーションと称する銀の電析を生じ、配線パターンによって形成される電極間または配線間に短絡現象が発生するという欠点が生じる。このマイグレーションを防止するための対策手段として、例えば、銀粉の表面に防湿塗料を塗布することや、導電性ペーストに窒素化合物などの腐食抑制剤を添加する等の手法が知られているが、十分な効果の得られるものではなかった（特許文献１参照）。また、導電性の高い導体を得るには銀粉の配合量を増加しなければならず、銀粉が高価であることから、電子機器が高価になるという欠点があった。
また、Ｃｕ粉を含有する導電性ペーストは、加熱硬化後のＣｕの酸化性が高いため、空気中及びバインダ中に含まれる酸素とＣｕ粉が反応し、その表面に酸化膜を形成し、導電性を著しく低下させる。その対策として、特許文献２には、各種添加剤を加えて、Ｃｕ粉の酸化を防止し、導電性を安定させたＣｕペーストが開示されている。しかし、その導電
性が銀ペーストには及ばず、また保存・安定性にも欠点があった。
マイグレーションを改善し、安価な導電性ペーストを得るために、銀メッキＣｕ粉を使用した導電性ペーストが提案されている（特許文献３、特許文献４参照）。しかし、銀を均一に、かつ、厚く被膜すると、マイグレーションの改善効果が十分に得られない場合がある。逆に、薄く被膜すると、良好な導電性確保のために導電粉の充てん量を増加させる必要があり、その結果、相対的なバインダ成分の減少に伴う接着力（接着強度）の低下が起こるという問題が生じる場合があった。
更に、屋外で使用される電子機器、例えば、太陽電池では、長期間にわたって、過酷な環境変動に耐え得る耐久性が要求される。特に、太陽電池が、日照時間の長い砂漠等に設置された場合には、設置場所の温度変動幅が１００℃を超えることがある。ところが、上述した技術によって電極を形成した従来の太陽電池は、このような厳しい自然環境におかれた場合、数年程度で電極が酸化によって劣化してしまうという問題があった。
上述した問題点を解決する手段として、特許文献５は、高融点金属成分及び低融点金属成分を、互いに拡散接合させてメタライズ層を形成するとともに、このメタライズ層を合成樹脂膜の表面を、合成樹脂膜によって覆う技術を開示している。
この技術によれば、導電性、電気化学的安定性、耐酸化性、充填性、緻密性、機械的・物理的強度に優れ、しかも基板に対する接着力・密着力の高い高品質・高信頼度のメタライズ配線を有する電子機器を実現することができる。
ただ、メタライズ層を絶縁層によって覆う構造であるので、上述した優れた効果が得られる半面、メタライズ配線上に電子部品の端子電極を接続する場合、または、他の外部導体を接続する場合、接続作業の巧拙によっては、絶縁層が、メタライズ層と端子電極との間に残り、電気的接続の信頼性を低下させてしまうことがある。
特開２００１−１８９１０７号公報 特開平５−２１２５７９号公報 特開平７−１３８５４９号公報 特開平１０−１３４６３６号公報 特許第４７７８１２０号公報
本発明の課題は、耐酸化性に優れた高品質・高信頼度のメタライズ配線を有する電子機器を提供することである。
本発明のもう一つの課題は、耐酸化性を確保しつつ、メタライズ配線に外部導体や、電子部品を接続する際、両者間の電気的導通を、確実に確保することができる電気機器を提供することである。
上述した課題を解決するため、本発明に係る電子機器は、基板を含み、前記基板は、メタライズ配線を有している。前記メタライズ配線は、メタライズ層と、合成樹脂膜とを含んでいる。前記メタライズ層は、高融点金属成分と低融点金属成分とを含み、前記高融点金属成分及び前記低融点金属成分が互いに拡散接合している。前記合成樹脂膜は、前記メ
タライズ層の表面を覆い、膜厚が５ｎｍ〜１０００ｎｍの範囲にある。
上述のように、高融点金属成分及び低融点金属成分は互いに拡散接合しているので、電気化学的安定性、耐酸化性に優れ、マイグレーションや酸化膜等を生じにくいメタライズ層を有する電子機器を実現することができる。
また、高融点金属成分及び低融点金属成分の拡散接合により、ポアや、断線のほとんどない連続するメタライズ層となるので、メタライズ層の充填度、緻密性が上がり、導電性が高く、機械的・物理的強度の高いメタライズ層を有する電子機器を得ることができる。しかも、高融点金属成分と低融点金属成分とを含んでいるので、その材料選定により、導電性の高いメタライズ層を有する電子機器を得ることができる。
また、合成樹脂膜が、メタライズ層の表面を覆っているから、メタライズ層の外的損傷を回避することができるほか、耐酸化性、耐久性、耐候性が向上する。しかも、基板に対するメタライズ層自体の密着力・接着力の他に、合成樹脂膜による密着力・接着力も発生するので、メタライズ配線の全体としての密着力・接着力が向上する。
上述した作用効果の総合として、導電性、電気化学的安定性、耐酸化性、充填性、緻密性、機械的・物理的強度に優れ、しかも基板に対する接着力・密着力の高い高品質・高信頼度のメタライズ配線を有する電子機器が得られる。
更に、合成樹脂膜は、メタライズ層の表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っている。５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜であれば、メタライズ配線に外部導体や、電子部品を接続する際の熱処理により、合成樹脂膜が軟化もしくは流動化して接続領域の外側に流れ出し、または、融解して焼失する。このため、メタライズ層と、外部導体や、電子部品との間には、合成樹脂膜がなくなり、メタライズ層に対して、外部導体や、電子部品が直接に接続されることになる。仮に、合成樹脂膜がメタライズ層と、外部導体又は電子部品の端子電極との間に残存したとしても、５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜であれば、トンネル効果等を期待することもできるから、両者間の電気的導通を確保することができる。接続部分の外側は、合成樹脂膜によって覆われているから、合成樹脂膜による酸化防止機能が損なわれることがない。即ち、本発明によれば、メタライズ層に対する外部導体及び電子部品の電気的接続の信頼性が高く、しかも、メタライズ層に対する酸化防止機能を有するメタライズ配線を実現することができる。
合成樹脂膜が５ｎｍよりも薄くなると、酸化防止機能が低くなり、１０００ｎｍを超過すると、絶縁膜としての性質が強く現れるようになる。こうした酸化防止機能及び導電性確保の観点からみて、合成樹脂膜の好ましい膜厚の範囲は、５ｎｍ〜５００ｎｍの範囲である。
合成樹脂膜は、メタライズ層の表面の全体に拡がっていて、その表面の全体を連続して完全に覆うのが理想であるが、合成樹脂膜の膜面内に、メタライズ層の露出する露出部分を含んでいてもよい。もっとも、露出部分の面積は、酸化防止機能を損なわない範囲に設定する。
好ましくは、合成樹脂膜は、メタライズ層と同時に形成する。この場合には、メタライズ層と樹脂層とを異時に形成したものと異なって、メタライズ層が空気に触れることがない。よって、酸化を受けない高品質のメタライズ層を有する電子機器を得ることができる。
メタライズ配線は、Ｃｕ膜（Ｃｕ箔）等の金属または合金膜の上に形成されていてもよい。高融点金属成分及び低融点金属成分でなるメタライズ配線を、Ｃｕ膜の上に形成すれば、Ｃｕ箔の厚みは変えないままで、メタライズ配線全体としての断面積を増大させ、電気抵抗を低減することができる。また、Ｃｕ箔を薄くしたままで、メタライズ配線全体としての断面積を増大させ、電気抵抗を低減することができる。
本発明において、電子機器には、電子工学の技術を応用した電気製品の全てを含むことができる。本発明では、それらのうち、コンピュータ、携帯電話機、積層電子装置、電子機器、電子部品、太陽電池、発光ダイオード、発光装置、照明装置、信号灯及び液晶ディスプレイについて開示する。これらは、具体的な名称によって特定されているが、電子工学の技術を応用した電気製品であるという点で、本発明にいう電子機器のカテゴリに含まれる。
上述したように、本発明によれば、次のような効果を得ることができる。
（ａ）耐酸化性、導電性、電気化学的安定性、充填性、緻密性、機械的・物理的強度に優れ、しかも基板に対する接着力・密着力の高い高品質・高信頼度のメタライズ配線を有する電子機器を提供することができる。
（ｂ）メタライズ配線に外部導体や電子部品を接続する際、耐酸化性を確保しつつ、両者間の電気的導通を確実に確保し得る電気機器を提供することができる。
本発明の他の目的、構成及び利点については、添付図面を参照し、更に詳しく説明する。添付図面は、単なる例示に過ぎない。
本発明に係る電子機器の一例を示す図である。 図１に示した電子機器に用いられているメタライズ配線の一部を示す断面図である。 図１に示した電子機器に用いられているメタライズ配線の別の位置における断面図である。 メタライズ配線形成用導電ペーストを示す図である。 図４に示した導電ペーストの塗布状態を示す図である。 本発明に係る電子機器に用いられるメタライズ配線の別の例を示す断面図である。 本発明に係る電子機器の一例たる積層電子装置を示す図である。 本発明に係る電子機器の他の例である太陽電池の平面図である。 図８に示した太陽電池の底面図（光入射側とは反対側）である。 本発明に係る電子機器の他の例である発光ダイオードの断面図である。 図１０に示した発光ダイオードを用いた発光装置、照明装置又は信号灯を示す図である。 図１１に示した発光ダイオードをバックライトして用いた液晶ディスプレイの部分断面図である。
図１を参照すると、本発明に係る電子機器は、基板１１と、電子部品１４１〜１４６とを含む。これらは、一般に、外装体２の内部に配置される。基板１１は、所定のパターンを有するメタライズ配線１２を有している。基板１１は、有機基板であってもよいし、無機基板であってもよい。また、半導体回路を構成し得る基板、例えばＳｉ基板であってもよいし、単なる絶縁基板であってもよい。
電子部品１４１〜１４６は、基板１１上でメタライズ配線１２に電気的に接続されている。図１には、電子部品１４１〜１４６を、群として表示する参照符号１４が付されている。電子部品１４１〜１４６のそれぞれは、能動部品、受動部品又はそれらの複合部品であり、その個数、種類、形状等は電子機器の機能、設計に応じて変化する。電子部品１４１〜１４６は、電子システム内で電子の振る舞いやそれに関わる力場に決まった形で影響を与え、システムが意図した機能を果たすようにするものである。電子部品１４１〜１４６は、メタライズ配線１２で相互に接続され、特定の機能を持った電子回路を構成する。電子部品１４１〜１４６は個別にパッケージングされる場合と、集積回路の形で複合的にパッケージングされ、モジュール化される場合がある。
更に、本発明の電子機器に含まれるものとしては、基板１１と電子部品１４１〜１４６との明確な区分をもたず、基板１１が電子部品１４１〜１４６としての機能を担う電子機器、例えば太陽電池等もある。
メタライズ配線１２は、図２及び図３に図示されているように、メタライズ層１２１と、合成樹脂膜１２２とを含んでいる。メタライズ層１２１は、低融点金属成分１２３と、高融点金属成分１２４とを含み、高融点金属成分１２４及び低融点金属成分１２３は互いに拡散接合し、充填密度の高い一連の連続する金属層を構成している。高融点金属成分１２４は、Ａｇ、Ｃｕ、Ａｕ、Ｐｔ、Ｔｉ、Ｚｎ、Ａｌ、Ｆｅ、Ｓｉ、または、Ｎｉの群から選択された少なくても１種を含むことができ、低融点金属成分１２３は、Ｓｎ、Ｉｎ、ＢｉまたはＧａの群から選択された少なくても１種を含むことができる。
合成樹脂膜１２２は、メタライズ層１２１の表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っている。合成樹脂膜１２２が、５ｎｍよりも薄くなると、酸化防止機能が低くなり、１０００ｎｍを超過すると、絶縁膜としての性質が強く現れるようになる。酸化防止機能及び導電性確保の観点から、合成樹脂膜１２２の好ましい膜厚の範囲は、５ｎｍ〜５００ｎｍの範囲である。
合成樹脂膜１２２は、メタライズ層１２１の表面のみならず、線幅方向の両側面及び長さ方向の端面を連続して覆っていてもよい。電子部品１４１〜１４６は、図３に図示するように、その端子電極１３が、合成樹脂膜１２２を突き抜け、その下側のメタライズ層１２１に食い込むようにして、接続されている。
合成樹脂膜１２２を構成する樹脂は、熱硬化性樹脂、または、熱可塑製樹脂を含むもので構成することができる。熱硬化性樹脂を使用する場合、その硬化点は、低融点金属成分１２３の融点より高く、高融点金属成分１２４の融点より低いものが好ましい。
好ましくは、樹脂は、エポキシ樹脂、アクリレート樹脂又はフェノール樹脂から選択された少なくとも１種を含む。ペースト化のための溶剤としては、ブチルカルビトール、ブチルカルビトールアセテート、ブチルセロソルブ、メチルイソブチルケトン、トルエン、または、キシレンのような公知の有機溶媒を使用することができる。
合成樹脂膜１２２は、メタライズ層１２１の表面の全体に拡がっていて、その表面の全体を連続して完全に覆っているのが理想であるが、その一部に、メタライズ層１２１の露出する露出部分Ｂ１、Ｂ２を含んでいてもよい。メタライズ層１２１は、高融点金属成分１２４と低融点金属成分１２３とを含んでいるから、例えば、低融点金属微粒子１２３を溶解させて、高融点金属微粒子１２４と拡散接合させた場合、高融点金属微粒子１２４は溶けずに、微粒子状態を保っていることがある。このような場合には、メタライズ層１２１の表面は、高融点金属微粒子１２４の突出する凸部と、低融点金属微粒子１２３の溶解した凹部とが入り組んだ複雑な凹凸面となる可能性がある。この結果、合成樹脂膜１２２は、メタライズ層１２１の表面を、完璧に覆う構造をとらず、特に、高融点金属微粒子１２４の突出する凸部分に、メタライズ層１２１の露出する露出部分Ｂ１，Ｂ２が発生しがちである。露出部分Ｂ１，Ｂ２の面積は、酸化防止機能を損なわない範囲に設定する。そのような設定は、合成樹脂と、低融点金属成分１２３及び高融点金属成分１２４との組成比率を調整する等によって可能である。
上述したように、メタライズ層１２１は、高融点金属成分１２４と低融点金属成分１２３とを含んでいて、高融点金属成分１２４及び低融点金属成分１２３が互いに拡散接合しているので、以下に述べるような作用効果が得られる。
まず、高融点金属成分１２４及び低融点金属成分１２３が互いに拡散接合しているので、電気化学的安定性、耐酸化性に優れたメタライズ層１２１を有する電子機器を実現することができる。
例えば、融点金属成分としてＡｇを使用した場合、メタライズ層１２１では、Ａｇと低融点金属成分１２３との間で拡散接合が生じることにより、その電気化学的安定性が増し、Ａｇのマイグレーションが確実に防止される。高融点金属成分１２４としてＣｕを使用した場合にも、Ｃｕと低融点金属成分１２３との間に拡散接合が生じ、Ｃｕの酸化が防止される。
次に、高融点金属成分１２４及び低融点金属成分１２３の拡散接合により、ポアや、断線のない連続するメタライズ層１２１となるので、メタライズ層１２１の充填度、緻密性が上がり、導電性が高くなるとともに、機械的・物理的強度が増す。しかも、高融点金属成分１２４と低融点金属成分１２３とを含んでいるので、その材料選定により、導電性の高いメタライズ層１２１を有する電子機器を得ることができる。
本発明においては、更に、合成樹脂膜１２２が、メタライズ層１２１の表面を覆っているから、メタライズ層１２１の外的損傷を回避することができるほか、耐酸化性が向上する。更に、耐久性、耐候性も向上する。しかも、基板に対するメタライズ層１２１自体の密着力・接着力の他に、合成樹脂膜１２２による密着力・接着力も発生するので、メタライズ配線１２の全体としての密着力・接着力が向上する。
合成樹脂膜１２２は、メタライズ層１２１の表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っている。５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜１２２であれば、メタライズ配線１２に、電子部品１４１〜１４６の端子電極１３を接続する際の熱処理により、合成樹脂膜１２２が、軟化もしくは流動化して接続領域の外側に流れ出し、または、融解して焼失する。このため、メタライズ層１２１と、電子部品１４１〜１４６の端子電極１３との間には、合成樹脂膜がなくなり、メタライズ層１２１に対して、電子部品１４１〜１４６の端子電極１３が直接に接続されることになる。仮に、合成樹脂膜１２２が、メタライズ層１２１と、電子部品１４１〜１４６の端子電極１３との間に残存したとしても、５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜１２２であれば、トンネル効果等を期待することもできるから、両者間の電気的導通を確保することができる。接続部分の外側は、合成樹脂膜１２２によって覆われているから、合成樹脂膜１２２による酸化防止機能が損なわれることがない。即ち、本発明によれば、メタライズ層１２１に対する電子部品１４１〜１４６の端子電極１３の電気的接続の信頼性が高く、しかも、メタライズ層１２１に対する酸化防止機能を有するメタライズ配線１２を実現することができる。
また、上記膜厚であれば、合成樹脂膜１２２を、化学的、または、機械的に部分的に除去し、メタライズ層１２１に対し、外部導体又は電子部品１４１〜１４６の端子電極１３を直接に接合することも容易である。
好ましくは、合成樹脂膜１２２は、メタライズ層１２１と同時に形成する。この場合には、メタライズ層１２１と樹脂層とを異時に形成したものと異なって、メタライズ層１２１が空気に触れることがない。よって、酸化を受けない高品質のメタライズ層１２１を有する電子機器を得ることができる。
メタライズ層１２１及び合成樹脂膜１２２は、樹脂と、金属成分と、溶剤とを含む導電ペーストを用いて、同時に形成することができる。
メタライズ層１２１及び合成樹脂膜１２２は、図４に示すように、金属微粒子たる高融点金属成分１２４及び金属微粒子たる低融点金属成分１２３よりなる金属成分と、樹脂１２２とを含む導電ペーストを、スクリーン印刷、グラビア印刷技術等を用いて、図５に図示するように、所定のパターンとなるように、基板１１に塗布し、熱処理し、拡散接合を生じさせることによって得られる。したがって、従来必須であった銅貼基板の準備、エッチング・レジスト塗布工程及びフォト・リソグラフィ工程が不要になり、著しいコスト低減及び量産性向上の効果が得られる。金属微粒子は、球状であってもよいし、扁平状であってもよい。ナノコンポジット構造のものが特に好ましい。ナノコンポジット構造とは、母材に結晶または非結晶のナノ粒子を混合または生成させた構造をいう。
拡散接合を生じさせる手法には、２つの手法が含まれる。一つは、低融点金属材料の持つ低融点を利用する方法であり、もう一つは、ナノサイズ効果、特に、量子サイズ効果を利用する方法である。前者の場合は、低融点金属成分１２３を、材料の持つ低い融点で溶解させ、高融点金属成分１２４と拡散接合させる。後者の場合は、高融点金属材料として、粒径又は厚みが、例えば、１００ｎｍ以下に微小化された高融点金属微粒子１２４を用い、ナノサイズ効果を利用して、高融点金属材料自体が持つ融点（初期融点）よりも、低い温度で溶解させ、拡散接合を生じさせる。
上記２つの手法のうち、低融点金属材料の持つ低融点を利用する場合は、熱処理にあたって、低融点金属成分１２３の融点より高く、高融点金属成分１２４の融点より低い温度、例えば１００〜３００℃で加熱することが望ましい。この熱処理により、低融点金属成分１２３が溶解し、高融点金属成分１２４及び低融点金属成分１２３が凝集し、高融点金属成分１２４の相互間が、溶解した低融点金属成分１２３によって埋めた充てん構造が得られるとともに、低融点金属成分１２３と高融点金属成分１２４との間に拡散接合（金属間結合）が生じる。この拡散接合により、樹脂を含有しないメタライズ層１２１が形成される。メタライズ層１２１は、その比重差によって樹脂層１２２よりも下側に沈降する。これによって、基板１１に付着したメタライズ層１２１の表面（表面及び側面）を、合成樹脂膜１２２で覆ったメタライズ配線１２が形成される。合成樹脂膜１２２は、メタライズ層１２１の表面（表面、側面）を覆う合成樹脂膜１２２を構成するから、合成樹脂膜１２２を塗布するための別工程が不要である。
また、高融点金属成分１２４としてＡｇを使用した場合も、メタライズ層１２１では、Ａｇと低融点金属成分１２３との間で、拡散接合が生じ、更に、導電性組成物全体では、メタライズ層１２１を合成樹脂膜１２２が被覆する。この構成により、Ａｇのマイグレーションを確実に防止することができる。同様に、高融点金属成分１２４として、Ｃｕを使用した場合にも、Ｃｕと低融点金属成分１２３との間に拡散接合が生じ、更にメタライズ層１２１が合成樹脂膜１２２によって被覆されるから、Ｃｕの酸化が防止される。
低融点金属微粒子１２３及び高融点金属微粒子１２４は、球状であってもよいし、扁平状であってもよい。扁平状である場合には、一例であるが、最大厚みが５０ｎｍ以下で、最大差し渡し径が厚みの２倍以上であるようなものが適している。
導電ペーストの別の例としては、高融点金属微粒子１２４の表面を、低融点金属膜１２３で覆った金属微粒子を用いたものであってもよいし、あるいはこれとは逆に、低融点金属微粒子１２３の表面を高融点金属膜で覆った金属微粒子を用いたものであってもよい。
高融点金属成分１２４及び低融点金属成分１２３でなるメタライズ配線１２は、図６に例示するように、Ｃｕ膜等の金属膜１２５の上に形成されていてもよい。高融点金属成分１２４及び低融点金属成分１２３でなるメタライズ層１２１を、Ｃｕ膜１２５（Ｃｕ箔）の上に形成すれば、Ｃｕ膜１２５の厚みは変えないままで、メタライズ配線１２全体としての断面積を増大させ、電気抵抗を低減することができる。或いは、Ｃｕ膜１２５の厚みを薄くしながら、その上に付着される高融点金属成分１２４及び低融点金属成分１２３でなるメタライズ層１２１を、厚く形成することによって、メタライズ配線１２の全体としての断面積を増大させ、電気抵抗を低減することができる。
本発明における電子機器には、電子工学の技術を応用した電気製品の全てを含むことができる。代表的に例示すると、例えば、コンピュータ、モバイル情報機器、コンピュータ周辺端末装置、ＯＡ機器、通信機器、業務用情報端末・自動認識装置、カーエレクトロニクス機器、産業用機械、エンターテインメント機器、音響機器、映像機器又は家庭用電気機器等である。限定するものではないが、その具体例として、液晶ディスプレイ、パーソナルコンピュータ、カーナビゲーション、携帯電話機、積層電子装置、太陽電池、太陽光発電装置、発光ダイオード、発光装置、照明装置、信号灯、ゲーム機、デジタルカメラ、テレビジョン受像機、ＤＶＤプレイヤー、電子手帳、電子辞書、ハードディスクレコーダ、携帯情報端末（ＰＤＡ)、ビデオカメラ、プリンタ、プラズマディスプレイ、ラジオ等を例示することができる。紙面に限りがあることから、上述した電子機器の一例として、積層電子装置、太陽電池、発光ダイオード、発光装置、照明装置、信号灯、及び、液晶ディスプレイを例にとって説明する。
＜積層電子装置＞
まず、図７を参照すると、第１のチップ部品１４Ａと、第２のチップ部品１４Ｂと、第３のチップ部品１４Ｃとを積層した積層電子装置が図示されている。第１のチップ部品１４Ａ及び第３のチップ部品１４Ｃは、例えばたコンピュータにおいて、メイン・メモリのチップ及びそれに接続されるロジックＩＣチップ等である。第２のチップ部品１４Ｂは、例えばインターポーザであり、メイン・メモリ・チップを構成する第１のチップ部品１４Ａと、ロジックＩＣチップを構成する第３のチップ部品１４Ｃとの間にあって、両者間に所定の配線を形成するものである。第２のチップ部品１４Ｂと第３のチップ部品１４Ｃとの間、及び、第２のチップ部品１４Ｂと第１のチップ部品１４Ａとの間には、所定のパターンを有するメタライズ配線１２が形成されている。メタライズ配線１２には、第１のチップ部品１４Ａの端子電極１３及び第２のチップ部品１４Ｂの端子電極１３が接続されている。第１のチップ部品１４Ａと第２のチップ部品１４Ｂとの間、及び、第２のチップ部品１４Ｂと第３のチップ部品１４Ｃとの間には、絶縁層１３２が設けられている。
メタライズ配線１２は、本発明に係るものであって、メタライズ層１２１と、合成樹脂膜１２２とを含んでいる（図２、図３等参照）。メタライズ層１２１は、高融点金属成分１２４と低融点金属成分１２３とを含み、高融点金属成分１２４及び低融点金属成分１２３が互いに拡散接合し、一連の連続するメタライズ層１２１を形成している。合成樹脂膜１２２は、メタライズ層１２１と同時に形成され、メタライズ層１２１の表面を、５ｎｍ〜１０００ｎｍの範囲の厚みで覆っている。
これにより、導電性、電気化学的安定性、耐酸化性、充填性、緻密性、機械的・物理的強度に優れ、しかも基板相互間の接着力の高い高品質・高信頼度のメタライズ配線１２を
有する積層電子装置が得られる。
合成樹脂膜１２２は、メタライズ層１２１の表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っているから、メタライズ層１２１に対する酸化防止膜としての機能を確保しつつ、実質的に導電性を有する膜として機能させることもできる。５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜１２２であれば、メタライズ配線１２に、第１のチップ部品１４Ａ、第２のチップ部品１４Ｂ及び第３のチップ部品１４Ｃを接続する際の熱処理により、合成樹脂膜１２２が、軟化もしくは流動化して接続領域の外側に流れ出し、または、融解して焼失する。このため、メタライズ層１２１と、第１のチップ部品１４Ａ、第２のチップ部品１４Ｂ及び第３のチップ部品１４Ｃの端子電極との間には、合成樹脂膜がなくなり、メタライズ層１２１に対して、第１のチップ部品１４Ａ、第２のチップ部品１４Ｂ及び第３のチップ部品１４Ｃの端子電極が直接に接続されることになる。仮に、合成樹脂膜１２２が、メタライズ層１２１と、第１のチップ部品１４Ａ、第２のチップ部品１４Ｂ及び第３のチップ部品１４Ｃの端子電極との間に残存したとしても、５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜１２２であれば、トンネル効果等を期待することもできるから、両者間の電気的導通を確保することができる。接続部分の外側は、合成樹脂膜１２２によって覆われるから、合成樹脂膜１２２による酸化防止機能が損なわれることがない。即ち、本発明によれば、メタライズ層１２１に対する第１のチップ部品１４Ａ、第２のチップ部品１４Ｂ及び第３のチップ部品１４Ｃの端子電極の電気的接続の信頼性が高く、しかも、メタライズ層１２１に対する酸化防止機能を有するメタライズ配線１２を実現することができる。
また、上記膜厚であれば、合成樹脂膜１２２を、化学的、または、機械的に部分的に除去し、メタライズ層１２１に対し、第１のチップ部品１４Ａ、第２のチップ部品１４Ｂ及び第３のチップ部品１４Ｃの端子電極を直接に接合することも容易である。
第２のチップ部品１４Ｂが、インターポーザである場合、いわゆるＴＳＶ（Through Silicon Via）技術を適用し、厚み方向に貫通電極を形成したものであることが望ましい。これにより、三次元回路配置構造を実現し、線幅の微細化とは異なる手法で、大容量化、転送速度の高速化、高周波特性の改善などに資することができる。
ＴＳＶ構造の実現において、中心的な役割を担う縦導体は、流動性導電材充填法によって形成した導体であることが好ましい。流動性導電材充填法によって縦導体（貫通電極）を形成するには、例えば、予め、基板に開けられた微細孔内に流動性導電材を充填し、充填された流動性導電材に、押圧板を用いたプレス、インジェクション射出圧又は転圧を印加したままで、冷却し、硬化させる。この流動性導電材充填法によれば、めっきなどに比較して、極めて短時間に、空洞等のない高品質の縦導体（貫通電極）を形成することができる。したがって、線幅の微細化とは異なる手法で、大容量化、転送速度の高速化、高周波特性の改善などを図った高品質の三次元構造の電子機器が実現される。
別の形態として、メモリや論理ＩＣ等の電子部品１４１〜１４６そのものに、ＴＳＶ 技術を適用して、三次元構造を実現してもよい。
＜太陽電池＞
図８及び図９を参照すると、シリコン基板１１の裏面（光入射面とは反対側）のｐ+半導体層１４ｐおよびｎ+半導体層１４ｎとの電気的接続を行なうために、シリコン基板１１の裏面に形成されたパッシベーション膜１２６が所望のパターン形状に除去され、パッシベーション膜１２６が除去された部分に合わせて、ｐ+半導体層１４ｐ上にｐ電極コンタクト１５ｐが形成されるとともに、ｎ+半導体層１４ｎ上にｎ電極コンタクト１５ｐが形成される。また、パッシベーション膜１２６及びｎ電極コンタクト１５ｎの上に、メタ
ライズ配線１２ｎが形成されるとともに、パッシベーション膜１２６及びｐ電極コンタクト１５ｐの上にメタライズ配線１２ｐが形成される。メタライズ配線１２ｐおよびメタライズ配線１２ｎは、主に太陽電池セルに発生した電流を収集する電極であり、これらは、インター・デジタル電極として形成されている。一枚のシリコン基板１１上に、多数の太陽電池セルを配列してゆく場合には、メタライズ配線１２ｐおよびメタライズ配線１２ｎの何れか一方に、太陽電池セル間を接続するバス電極としての役割を担わせることができる。
ここで、図２〜図３に示したように、メタライズ配線１２ｐは、メタライズ層１２１ｐと、合成樹脂膜１２２ｐとを含んでいる。メタライズ層１２１ｐは、高融点金属成分１２４と低融点金属成分１２３とを含んでいる。高融点金属成分１２４及び低融点金属成分１２３は互いに拡散接合している。合成樹脂膜１２２ｐは、メタライズ層１２１ｐと同時に形成され、メタライズ層１２１ｐの表面を、５ｎｍ〜１０００ｎｍの範囲の厚みで覆っている。
メタライズ配線１２ｎも同様であって、メタライズ層１２１ｎと、合成樹脂膜１２２ｎとを含んでいる。メタライズ層１２１ｎは、高融点金属成分１２４と低融点金属成分１２３とを含んでいる。高融点金属成分１２４及び低融点金属成分１２３は互いに拡散接合し、メタライズ層１２１ｎを構成している。合成樹脂膜１２２ｎは、メタライズ層１２１ｎと同時に形成され、メタライズ層１２１ｎの表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っている。その形成方法については、既に述べたとおりである。
合成樹脂膜１２２ｐ、１２２ｎは、メタライズ配線１２ｐ、１２ｎの表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っているから、メタライズ層１２１ｐ、１２１ｎに対する酸化防止膜としての機能を確保しつつ、実質的に導電性を有する膜として機能させることもできる。５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜１２２ｐ、１２２ｎであれば、メタライズ配線１２ｐ、１２ｎに、外部導体（図示しない）を接続する際の熱処理により、合成樹脂膜１２２ｐ、１２２ｎが、軟化もしくは流動化して接続領域の外側に流れ出し、または、融解して焼失する。このため、メタライズ層１２１ｐ、１２１ｎと、外部導体との間には、合成樹脂膜がなくなり、メタライズ層１２１ｐ、１２１ｎに対して、外部導体が直接に接続されることになる。仮に、合成樹脂膜１２２ｐ、１２２ｎが、メタライズ層１２１ｐ、１２１ｎと、外部導体との間に残存したとしても、５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜１２２ｐ、１２２ｎであれば、トンネル効果等を期待することもできるから、両者間の電気的導通を確保することができる。接続部分の外側は、合成樹脂膜１２２ｐ、１２２ｎによって覆われるから、合成樹脂膜１２２ｐ、１２２ｎによる酸化防止機能が損なわれることがない。即ち、本発明によれば、メタライズ層１２１ｐ、１２１ｎに対する外部導体の電気的接続の信頼性が高く、しかも、メタライズ層１２１ｐ、１２１ｎに対する酸化防止機能を有するメタライズ配線１２ｐ、１２ｎを実現することができる。
また、上記膜厚であれば、合成樹脂膜１２２ｐ、１２２ｎを、化学的、または、機械的に部分的に除去し、メタライズ層１２１ｐ、１２１ｎに対し、外部導体を直接に接触させることも容易である。
本発明に係るメタライズ配線１２は、図示の太陽電池のみならず、他のタイプの太陽電池にも適用することができる。例えば、太陽光入射側にＩＴＯ等の透明電極を有する太陽電池において、透明電極を形成する場合や、色素増感型太陽電池において、電極を形成する場合等である。
＜発光ダイオード＞
次に、図１０を参照すると、本発明に係る発光ダイオードが図示されている。図１０に例示された発光ダイオードは、発光素子１４０と、ｎメタライズ配線（第１メタライズ配線）１２ｎと、ｐメタライズ配線（第２メタライズ配線）１２ｐとを含んでいる。発光素子１４０は、透明結晶基板１６１に積層されている。透明結晶基板１６１は、サファイヤ等で構成されたもので、表面が光出射面であり、発光素子１４０は透明結晶基板１６１の光出射面とは反対側の他面に積層されている。
発光素子１４０は、透明結晶基板１６１に積層したバッファ層１６２の上に、ｎ型半導体層１４ｎを形成し、ｎ型半導体層１４ｎの上に、活性層１４ａを介して、ｐ型半導体層１４ｐを積層した構造になっている。透明結晶基板１６１の側に位置するｎ型半導体層１４ｎは、Ｐ型半導体層１４ｐと重ならない部分１６４を有しており、この部分１６４の段差が金属導電層１６５によって埋められている。
メタライズ配線１２ｎは、ｎ型半導体層１４ｎに接続され、メタライズ配線１２ｐは、ｐ型半導体層１４ｐに接続されている。メタライズ配線１２ｎは、メタライズ層１２１ｎと合成樹脂膜１２２ｎとを含み、メタライズ層１２１ｎが金属導電層１６５の表面に接合されている。メタライズ配線１２ｐのメタライズ層１２１ｐは、メタライズ配線１２ｎと同じ側の面に設けられ、反射膜１６３を介して、ｐ型半導体層１４ｐに接続されている。
メタライズ層１２１ｎ及びメタライズ層１２１ｐには、支持基板１１及び合成樹脂膜１２２ｎ、１２２ｐを貫通する第１及び第２貫通電極１７ＮＴ、１７ＰＴが接続されている。
メタライズ配線１２ｎは、樹脂と金属成分とを含む同一導電ペーストを用いて同時に形成されたものである。金属成分は、高融点金属成分１２４と低融点金属成分１２３とを含み、高融点金属成分１２４及び低融点金属成分１２３は互いに拡散接合して、メタライズ層１２１ｎを構成している。合成樹脂膜１２２ｎは、樹脂からなり、メタライズ層１２１ｎの表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っている。メタライズ層１２１ｎは、ｎ電極コンタクト１５ｎに接続される。
メタライズ配線１２ｐも、樹脂と金属成分とを含む同一導電ペーストを用いて同時に形成されたものである。金属成分は、高融点金属成分１２４と低融点金属成分１２３とを含み、高融点金属成分１２４及び低融点金属成分１２３は互いに拡散接合して、メタライズ層１２１ｐを構成している。合成樹脂膜１２２ｐは、メタライズ層１２１ｐの表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っている。参照符号１６は、絶縁層である。
上記構成によれば、導電性、電気化学的安定性、耐酸化性、充填性、緻密性、機械的・物理的強度に優れ、しかも基板に対する接着力・密着力の高い高品質・高信頼度のメタライズ層１２１ｐ、１２１ｎを有する発光ダイオードが得られる。
合成樹脂膜１２２ｎ、１２２ｐは、メタライズ層１２１ｎ、１２１ｐの表面を、５ｎｍ〜１０００ｎｍの範囲の膜厚で覆っているから、メタライズ層１２１ｐ、１２１ｎに対する酸化防止膜としての機能を確保しつつ、実質的に導電性を有する膜として機能させることもできる。５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜１２２ｐ、１２２ｎであれば、メタライズ配線１２ｐ、１２ｎに、第１及び第２貫通電極１７ＮＴ、１７ＰＴを接続する際の熱処理により、合成樹脂膜１２２ｐ、１２２ｎが、軟化もしくは流動化して接続領域の外側に流れ出し、または、融解して焼失する。このため、メタライズ層１２１ｐ、１２１ｎと、第１及び第２貫通電極１７ＮＴ、１７ＰＴとの間には、合成樹脂膜がなくなり、メタライズ層１２１ｐ、１２１ｎに対して、第１及び第２貫通電極１７ＮＴ、１７ＰＴが直接に接続されることになる。仮に、合成樹脂膜１２２ｐ、１２２ｎが、メタラ
イズ層１２１ｐ、１２１ｎと、第１及び第２貫通電極１７ＮＴ、１７ＰＴとの間に残存したとしても、５ｎｍ〜１０００ｎｍの範囲にある膜厚の合成樹脂膜１２２ｐ、１２２ｎであれば、トンネル効果等を期待することもできるから、両者間の電気的導通を確保することができる。接続部分の外側は、合成樹脂膜１２２ｐ、１２２ｎによって覆われるから、合成樹脂膜１２２ｐ、１２２ｎによる酸化防止機能が損なわれることがない。即ち、本発明によれば、メタライズ層１２１ｐ、１２１ｎに対する第１及び第２貫通電極１７ＮＴ、１７ＰＴの電気的接続の信頼性が高く、しかも、メタライズ層１２１ｐ、１２１ｎに対する酸化防止機能を有するメタライズ配線１２ｐ、１２ｎを実現することができる。
また、上記膜厚であれば、合成樹脂膜１２２ｐ、１２２ｎを、化学的、または、機械的に部分的に除去し、メタライズ層１２１ｐ、１２１ｎに対し、第１及び第２貫通電極１７ＮＴ、１７ＰＴを直接に接触させることも容易である。
なお、本発明に係るメタライズ配線１２は、図示の発光ダイオードのみならず、他のタイプの発光ダイオードにも適用することができる。例えば、光出射側にＩＴＯ等の透明電極を有する発光ダイオード池において、透明電極を形成する場合等である。
＜発光装置、照明装置又は信号灯＞
図１１を参照すると、ｍ個の発光ダイオードＬＥＤ１〜ＬＥＤｍを有する発光装置が図示されている。発光ダイオードＬＥＤ１〜ＬＥＤｍは、図１０に示したものであって、発光素子１４０と、ｎメタライズ配線（第１メタライズ配線）１２ｎと、ｐメタライズ配線（第２メタライズ配線）１２ｐとを含んでいる。発光ダイオードＬＥＤ１〜ＬＥＤｍの具体的な構造は、図１０を参照して詳説したとおりである。発光ダイオードＬＥＤ１〜ＬＥＤｍは、単列、又は、複数列配置してもよい。また、基板は、発光ダイオードＬＥＤ１〜ＬＥＤｍにおいて、共通のものであってもよい。更に、Ｒ、Ｇ、Ｂの発光ダイオードの配列であってもよいし、単色光の発光ダイオードを配列したものであってもよい。
図１１に示した発光装置は、照明装置としても用いることができるし、交通信号の信号灯として用いることもできる。これらの発光装置、照明装置又は信号灯が、高品質で、信頼性が高くなることは、これまでの説明から自明である。
＜液晶ディスプレイ＞
図１２は、液晶ディスプレイを示す図で、液晶パネル８とバックライト９とを組み合わせた構造となっている。バックライト９は、図１１に示したｍ個の発光ダイオードＬＥＤ１〜ＬＥＤｍを、行列状に整列したものである。この液晶ディスプレイが、高品質で、信頼度が高いものであることは、これまでの説明から明らかである。
以上、好ましい試料を参照して本発明の内容を具体的に説明したが、本発明の基本的技術思想及び教示に基づいて、当業者であれば、種々の変形態様を採り得ることは自明である。
１１ 基板
１２ メタライズ配線
１２１ メタライズ層
１２２ 合成樹脂膜
１４ 電子部品

Claims (4)

  1. 基板と、電子部品とを含む電子機器であって、
    前記基板は、メタライズ配線を有しており、
    前記メタライズ配線は、メタライズ層と、合成樹脂膜とを含んでおり、
    前記メタライズ層は、高融点金属成分と低融点金属成分とを含み、前記高融点金属成分及び前記低融点金属成分が互いに拡散接合し、前記基板の表面に付着しており、
    前記合成樹脂膜は、前記メタライズ層と同時に形成され、前記メタライズ層の表面を覆い、膜厚が５ｎｍ〜１０００ｎｍの範囲にあり、
    前記電子部品は、前記メタライズ層に電気的に接続されている。
  2. 請求項１に記載された電子機器であって、前記合成樹脂膜は、膜厚が５ｎｍ〜５００ｎｍの範囲にある。
  3. 請求項１又は２に記載された電子機器であって、前記高融点金属成分及び前記低融点金属成分は、ナノコンポジット構造を有する。
  4. 請求項１乃至３の何れかに記載された電子機器であって、コンピュータ、モバイル情報機器、コンピュータ周辺端末装置、ＯＡ機器、通信機器、業務用情報端末・自動認識装置、カーエレクトロニクス機器、産業用機械、エンターテインメント機器、音響機器、映像機器又は家庭用電気機器の群から選択された少なくとも一種である。
JP2012098837A 2012-04-24 2012-04-24 電子機器 Active JP5124693B1 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2012098837A JP5124693B1 (ja) 2012-04-24 2012-04-24 電子機器
US13/859,175 US20130277850A1 (en) 2012-04-24 2013-04-09 Electronic device
SG2013026984A SG194295A1 (en) 2012-04-24 2013-04-10 Electronic device
EP13275090.2A EP2657962A1 (en) 2012-04-24 2013-04-16 Electronic device with a metallisation layer having a high- and a low-melting-point component diffusion-bonded together and a synthetic resin layer covering the metallisation layer
KR1020130043756A KR101355748B1 (ko) 2012-04-24 2013-04-19 전자기기
TW102113877A TWI529853B (zh) 2012-04-24 2013-04-19 電子機器
CN2013101444077A CN103378051A (zh) 2012-04-24 2013-04-24 电子设备

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012098837A JP5124693B1 (ja) 2012-04-24 2012-04-24 電子機器

Publications (2)

Publication Number Publication Date
JP5124693B1 true JP5124693B1 (ja) 2013-01-23
JP2013229376A JP2013229376A (ja) 2013-11-07

Family

ID=47692899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012098837A Active JP5124693B1 (ja) 2012-04-24 2012-04-24 電子機器

Country Status (7)

Country Link
US (1) US20130277850A1 (ja)
EP (1) EP2657962A1 (ja)
JP (1) JP5124693B1 (ja)
KR (1) KR101355748B1 (ja)
CN (1) CN103378051A (ja)
SG (1) SG194295A1 (ja)
TW (1) TWI529853B (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2839904A1 (en) * 2013-08-21 2015-02-25 Napra Co., Ltd. Functional material
US9293416B2 (en) 2012-08-29 2016-03-22 Napra Co., Ltd. Functional material

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081043A (ja) * 2005-09-13 2007-03-29 Sharp Corp 有機薄膜トランジスタおよびその製造方法
JP2009004394A (ja) * 2006-05-24 2009-01-08 Nissan Chem Ind Ltd ゲート絶縁膜用塗布液、ゲート絶縁膜および有機トランジスタ
JP2009218295A (ja) * 2008-03-07 2009-09-24 Ricoh Co Ltd 薄膜トランジスタ、その製造方法、アクティブマトリクス型薄膜トランジスタアレイ及びアクティブマトリクス駆動表示装置
JP2010129995A (ja) * 2009-03-03 2010-06-10 Napura:Kk 微細空間への金属充填方法
JP2011023497A (ja) * 2009-07-15 2011-02-03 Napura:Kk 回路基板及び電子デバイス
JP2011107576A (ja) * 2009-11-20 2011-06-02 Seiko Epson Corp 半導体装置用基板の製造方法、及び半導体装置用基板
JP4778120B1 (ja) * 2011-03-08 2011-09-21 有限会社ナプラ 電子機器

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2514516B2 (ja) 1992-02-05 1996-07-10 タツタ電線株式会社 半田付け可能な導電性ペ―スト
JPH07138549A (ja) 1993-11-15 1995-05-30 Tatsuta Electric Wire & Cable Co Ltd 導電性接着剤
JPH10134636A (ja) 1996-10-30 1998-05-22 Hitachi Chem Co Ltd 導電性粉体、導電性ペースト及び導電性ペーストを用いた電気回路
JP2001189107A (ja) 1999-10-22 2001-07-10 Matsushita Electric Ind Co Ltd 導電性組成物、導電性接着剤および実装構造体
JP4191678B2 (ja) * 2002-05-31 2008-12-03 タツタ電線株式会社 導電性ペースト、これを用いた多層基板及びその製造方法
JP2005259848A (ja) * 2004-03-10 2005-09-22 Toshiba Corp 半導体装置及びその製造方法
JP4678654B2 (ja) * 2007-09-03 2011-04-27 有限会社ナプラ 電子デバイス。
KR100924554B1 (ko) * 2007-11-30 2009-11-02 주식회사 하이닉스반도체 플립 칩 패키지 및 이의 제조 방법
JP2010238809A (ja) 2009-03-30 2010-10-21 Tokuyama Corp メタライズド配線基板の製造方法
KR20110014034A (ko) * 2009-08-04 2011-02-10 삼성전기주식회사 유기접착층이 있는 금속 회로 배선 및 그 제조방법
JP5209075B2 (ja) * 2010-05-21 2013-06-12 有限会社 ナプラ 電子デバイス及びその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007081043A (ja) * 2005-09-13 2007-03-29 Sharp Corp 有機薄膜トランジスタおよびその製造方法
JP2009004394A (ja) * 2006-05-24 2009-01-08 Nissan Chem Ind Ltd ゲート絶縁膜用塗布液、ゲート絶縁膜および有機トランジスタ
JP2009218295A (ja) * 2008-03-07 2009-09-24 Ricoh Co Ltd 薄膜トランジスタ、その製造方法、アクティブマトリクス型薄膜トランジスタアレイ及びアクティブマトリクス駆動表示装置
JP2010129995A (ja) * 2009-03-03 2010-06-10 Napura:Kk 微細空間への金属充填方法
JP2011023497A (ja) * 2009-07-15 2011-02-03 Napura:Kk 回路基板及び電子デバイス
JP2011107576A (ja) * 2009-11-20 2011-06-02 Seiko Epson Corp 半導体装置用基板の製造方法、及び半導体装置用基板
JP4778120B1 (ja) * 2011-03-08 2011-09-21 有限会社ナプラ 電子機器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9293416B2 (en) 2012-08-29 2016-03-22 Napra Co., Ltd. Functional material
EP2839904A1 (en) * 2013-08-21 2015-02-25 Napra Co., Ltd. Functional material

Also Published As

Publication number Publication date
TWI529853B (zh) 2016-04-11
EP2657962A1 (en) 2013-10-30
US20130277850A1 (en) 2013-10-24
SG194295A1 (en) 2013-11-29
KR20130119872A (ko) 2013-11-01
TW201401437A (zh) 2014-01-01
KR101355748B1 (ko) 2014-01-27
JP2013229376A (ja) 2013-11-07
CN103378051A (zh) 2013-10-30

Similar Documents

Publication Publication Date Title
JP4778120B1 (ja) 電子機器
US10847691B2 (en) LED flip chip structures with extended contact pads formed by sintering silver
KR20160101571A (ko) 반도체 발광 소자를 이용한 디스플레이 장치
CN103378047B (zh) 封装载板
JP5124693B1 (ja) 電子機器
WO2012057075A1 (ja) 配線基板付き裏面電極型太陽電池セルおよび配線基板付き裏面電極型太陽電池セルの製造方法
US9905327B2 (en) Metal conducting structure and wiring structure
JP5352647B2 (ja) 基板
JP5352629B2 (ja) 基板
WO2013187329A1 (ja) 太陽電池モジュールの製造方法、太陽電池用導電性接着剤、太陽電池モジュール
EP2839904B1 (en) Functional material
CN102403436B (zh) 半导体发光元件的散热座的制作方法
US20240244747A1 (en) Wiring board, functional backplane and method for manufacturing the same
EP4152419A1 (en) Semiconductor light-emitting element and display device including same
CN103928433A (zh) 半导体装置及其制法
CN2829091Y (zh) 倒装芯片封装体结构
JP2015207636A (ja) 電子デバイス、その製造方法、金属粒子及び導電性ペースト
CN113809111A (zh) 显示面板、显示装置及显示面板的制备方法
CN111435697A (zh) 一种显示装置用的导电板
CN117480435A (zh) 阵列基板及电子装置
CN101533821A (zh) 增进散热效益的芯片承载器及其芯片封装结构
CN105390175A (zh) 金属化电气部件

Legal Events

Date Code Title Description
TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151102

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 5124693

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250