JP6970219B2 - アンダーバンプメタル構造体用のカラー並びにそれに関連するシステム及び方法 - Google Patents

アンダーバンプメタル構造体用のカラー並びにそれに関連するシステム及び方法 Download PDF

Info

Publication number
JP6970219B2
JP6970219B2 JP2020005714A JP2020005714A JP6970219B2 JP 6970219 B2 JP6970219 B2 JP 6970219B2 JP 2020005714 A JP2020005714 A JP 2020005714A JP 2020005714 A JP2020005714 A JP 2020005714A JP 6970219 B2 JP6970219 B2 JP 6970219B2
Authority
JP
Japan
Prior art keywords
ubm structure
ubm
collar
semiconductor
semiconductor die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020005714A
Other languages
English (en)
Other versions
JP2020074436A (ja
Inventor
マリオッティーニ,ジョルジオ
エス. ヴァダフカー,サミア
エイチ. ファン,ウェイン
チャンドル,アニルクマール
ボスラー,マーク
Original Assignee
マイクロン テクノロジー,インク.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by マイクロン テクノロジー,インク. filed Critical マイクロン テクノロジー,インク.
Publication of JP2020074436A publication Critical patent/JP2020074436A/ja
Application granted granted Critical
Publication of JP6970219B2 publication Critical patent/JP6970219B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481Insulating layers on insulating parts, with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60045Pre-treatment step of the bump connectors prior to bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60067Aligning the bump connectors with the mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60225Arrangement of bump connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02135Flow barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/0219Material of the auxiliary member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/03011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bonding area, e.g. solder flow barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • H01L2224/03472Profile of the lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • H01L2224/0348Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/036Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361Physical or chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03901Methods of manufacturing bonding areas involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/03902Multiple masking steps
    • H01L2224/03906Multiple masking steps with modification of the same mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05007Structure comprising a core and a coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181Tantalum [Ta] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05547Structure comprising a core and a coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05553Shape in top view being rectangular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05555Shape in top view being circular or elliptic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05563Only on parts of the surface of the internal layer
    • H01L2224/05565Only outside the bonding interface of the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05563Only on parts of the surface of the internal layer
    • H01L2224/05566Both on and outside the bonding interface of the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/05686Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/05686Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2224/05687Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/0569Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • H01L2224/11472Profile of the lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902Multiple masking steps
    • H01L2224/11906Multiple masking steps with modification of the same mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13026Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/07Polyamine or polyimide
    • H01L2924/07025Polyimide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/36Material effects
    • H01L2924/365Metallurgical effects
    • H01L2924/3651Formation of intermetallics

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

本技術は、概して半導体デバイスを対象とし、より具体的には、幾つかの実施形態においてはダイ間及び/又はパッケージ間の相互接続用のアンダーバンプメタル(UBM)構造体を対象とする。
例えば、メモリデバイス、マイクロプロセッサ、及び発光ダイオード等のマイクロ電子デバイスは、典型的には、基板に実装されプラスチックの保護カバーに入れられた1つ以上の半導体ダイを含む。半導体ダイは、例えば、メモリセル、プロセッサ回路、及び相互接続回路等の機能的フィーチャを含む。半導体ダイは、典型的には、機能的フィーチャに電気的に結合されたボンドパッドをも含む。ボンドパッドは、半導体ダイをバス、回路、若しくはその他のアセンブリに接続するために保護カバーの外側に延伸するピン又はその他の端子類に電気的に接続される。
半導体ダイの製造は、ダイが占有する体積を削減し、それにもかかわらず、その結果もたらされる封入されたアセンブリの容量及び/又は速度を増加させるという圧力の増加の下にある。これらの要求を満たすために、半導体ダイの製造者は、ダイが実装される回路基板又はその他の素子上の限定された体積内でデバイスの容量又は性能を増大させるために、多数のダイをしばしば相互に積み重ねる。多くの利用において、ダイは、封入される前に相互に積み重ねられて3次元パッケージを形成する。
積み重ねられた半導体ダイは、典型的には、アンダーバンプメタル(UBM)構造体に付着されるはんだバンプ又はその他の電気コネクタによって電気的に接続される。UBM構造体は、典型的には、銅シード構造体をウエハ上に堆積し、ダイ上のボンドパッドと整列された開口部を有するマスクを銅シード構造体上に形成し、シード構造体上に銅をめっきし、UBM構造体を形成するために銅の上に1つ以上のその他の材料をその後めっきすることによって形成される。UBM構造体の最上層の材料は、典型的には、その後に最上層の材料に相互接続を形成するための湿潤(wetting)を促進するために選択される。U
BM構造体を形成した後、相互接続としての機能を果たすように、UBM構造体の最上層の材料の上にはんだ材料のマイクロバンプが形成される。UBM構造体及びマイクロバンプを形成した後、マスクが除去され、分離されたUBM構造体及びマイクロバンプを形成するために適切なウェットエッチングを用いてシード構造体の露出部分が除去される。本技術は、改良されたUBM構造体及びUBM構造体の製造方法を対象とする。
本発明の半導体ダイの一態様は、固体状態の構成要素を有する半導体材料と、前記半導体材料を少なくとも部分的に通って延伸する相互接続部と、前記相互接続部に電気的に結合されたアンダーバンプメタル(UBM)構造体であって、前記UBM構造体は、上面、底面、及び前記上面と前記底面との間に延伸する側壁を有し、前記UBM構造体は、第1の導電性材料と、前記第1の導電性材料上に配置された第2の導電性材料とを含む、UBM構造体と、前記第1の導電性材料の全部ではない一部と前記第2の導電性材料の少なくとも一部とを取り囲むように、前記UBM構造体の前記側壁の少なくとも一部を取り囲むカラーであって、前記カラーは前記UBM構造体の前記上面よりも上方へ延伸しておらず、かつ、前記半導体材料に接触していない、カラーと、前記UBM構造体の前記上面
上に配置されたはんだ材料と、を含み、前記カラーは、酸化物、窒化物、又はポリイミドのうちの少なくとも1つを含む抗湿潤材料を含み、前記はんだ材料は液相において前記抗湿潤材料を容易には濡らさない、ことを特徴とする。
本技術の多くの態様は以下の図面を参照してより理解できる。図面中の構成要素は、必ずしも縮尺通りではく、むしろ本技術の原理を明確に図示することに重点が置かれている。
本技術の実施形態に従った複数の半導体ダイを概略的に示す基板アセンブリの断面図である。 本技術の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の別の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の別の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の別の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の別の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の別の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の別の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の別の実施形態に従った方法のある段階における半導体ダイの一部を概略的に示す断面図である。 本技術の実施形態に従った方法のフローチャートである。 本発明の実施形態に従った方法のフローチャートである。 本発明の実施形態に従った半導体デバイスを組み込むシステムを示すブロック図である。
半導体デバイスを作るための方法の幾つかの実施形態の具体的詳細が関連するデバイス及びシステムと共に本明細書に記載される。用語「半導体デバイス」とは、概して、1つ以上の半導体材料を含む固体状態のデバイスを指す。半導体デバイスの一例としては、とりわけ、論理デバイス、メモリデバイス、マイクロプロセッサ、及びダイオードが挙げられる。また、用語「半導体デバイス」は、完成されたデバイスを指し得、又は完成されたデバイスになる以前の様々な処理段階におけるアセンブリ若しくはその他の構造体を指し
得る。それが用いられる内容に応じて、用語「基板」は、ウエハレベルの基板を指し得、又はシンギュレートされたダイレベルの基板を指し得る。本明細書に記載される方法の適切なステップがウエハレベル又はダイレベルで実行できることは当業者であれば分かるであろう。また、特に断りがない限り、本明細書で開示される構造体は、従来の半導体製造技術を用いて形成され得る。材料は、例えば、化学蒸着、物理蒸着、原子層堆積、スピンコーティング、及び/又はその他の適切な技術を用いて堆積され得る。同様に、材料は、例えば、プラズマエッチング、ウェットエッチング、化学機械平坦化、又はその他の適切な技術を用いて除去され得る。
本技術の多くの実施形態は、例えば、完成した場合に基板及び又はパッケージ材料を完全に通過して延伸する導電性のプラグ又はコネクタを有する貫通シリコンビア等の、TSVに電気的に結合されるUBM構造体に関連して以下に記述される。本技術は、基板アセンブリの第1の側面又は第2の側面の何れかの上にUBM構造体を形成するための実施形態を含むこと、並びにUBM構造体は、半導体アセンブリと関連付けられたその他の電気コネクタに関連して用いられてもよいことも当業者であれば理解するであろう。本技術は、その結果、図1〜図6を参照しながら本明細に記述される実施形態の幾つかの詳細なしに実施されてもよい。参照を容易にするため、同じ参照番号は、この開示を通じて同様の若しくは類似の構成要素又はフィーチャを識別するために用いられるが、同じ参照符号の使用は、フィーチャが同じであると解釈されるべきことを意味しない。実際、本明細書に記述される多くの実施形態において、全く同じ番号が付されたフィーチャは、構造体及び/又は機能が互いに異なる複数の実施形態を有する。また、構成的に同様であり得る断面中の材料を示すために同じ陰影が用いられ得るが、本明細書に特段に言及がない限り、同じ陰影の使用は、材料が同じであると解釈されるべきことを意味しない。
UBM構造体及びマイクロバンプは、リフロー処理を用いて隣接するダイに付着される。UBM構造体の上部に配置されたマイクロバンプのリフローの間、マイクロバンプの幾つかの材料(例えば、スズ)はUBM構造体の材料(例えば、銅)と反応し得、それは、UBM構造体と隣接するダイとの相互接続に有害に作用し得る。例えば、マイクロバンクからの幾つかの材料は、UBM構造体に沿って濡れる側壁に起因して流出し得る。これは、マイクロバンプの側壁上の金属間化合物の形成を導き得る。加えて、マイクロバンプ材料の幾つか(例えば、スズ)は、UBM構造体の材料(例えば、銅)に達して反応している間拡散し得、マイクロバンプ中の利用可能なスズに対してモル体積の縮小をもたらす(ハンダ欠乏とも称される)。これら2つの影響は、マイクロバンプの中心で利用可能な無反応なはんだ材料の減少をもたらし、はんだ接合中の隙間を引き起こし、電子移動の信頼性を減らす。
本技術の幾つかの実施形態は、マイクロバンプのリフローの間、マイクロバンプのはんだ材料がUBM構造体の材料と反応する可能性を削減する。例えば、本技術の幾つかの実施形態は、マイクロバンプからのはんだと反応することからUBMの側壁を保護する、UBM構造体の第1の材料及び/又は第2の材料の少なくとも一部の周囲にカラーを形成する。本技術の幾つかの実施形態は、それ故、より詳細に以下で説明されるように、マイクロバンプのリフローの間、マイクロバンプとUBMの側壁との反応を削減する。
図1は、第1の側112及び第2の側114を伴う半導体材料110を有する基板アセンブリ100を概略的に図示する断面図である。基板アセンブリ100は、半導体材料110の第2の側面114上の誘電性材料116を更に含む。複数の半導体ダイ120は、基板アセンブリ100の別々の領域に形成される。図1には2つの半導体ダイ120が図示されているが、実施において基板アセンブリ100は、典型的には、数百又は1000以上の個々の半導体ダイを有する。個々の半導体ダイ120は、集積回路122と、集積回路122に電気的に結合された複数の相互接続部124とを含み得る。図1に示された
実施形態では、相互接続部124は、誘電性ライナー126と誘電性ライナー126内の導電性プラグ128とを含むTSVである。従って、相互接続部124は、基板アセンブリ100を貫通して延伸しうる。
半導体ダイ120は複数のUBM構造体130を更に含み、個々のUBM構造体130は対応する相互接続部124に電気的に結合される。幾つかの実施形態では、個々のUBM構造体130は、相互接続部124の1つに電気的に結合された第1の材料132と、第1の材料132上の第2の材料134とを含む。抗湿潤(anti-wetting)材料136は、第1の材料132及び第2の材料134の少なくとも一部の周囲にカラー138を形成する。半導体ダイ120は、個々のUBM構造体130の第2の材料134上のマイクロバンプ140をも含み得る。
特定の実施形態では、第1の材料132は銅を含み、第2の材料134はニッケルを含み、マイクロバンプ140はスズ−銀はんだ材料を含み、カラー138は、酸化物、例えば、オルトケイ酸テトラエチル(TEOS)又は別の酸化物を含む。この実施形態は、Cu/Ni UBM構造体130上に形成されたマイクロバンプ140を伴うCu/Ni UBM構造体130と、UBM構造体130の上面(例えば、第2の材料134の上面)を被覆することなくNi及びCuの少なくとも一部の露出した側壁を取り囲む酸化物カラーとを形成する。その他の実施形態では、第1の材料132及び第2の材料134は、例えば、金、シリコン、タングステン等の任意の導電性材料を含み得る。UBM構造体の形状及び寸法は多様であり得る。例えば、幾つかの実施形態では、UBM構造体130は、実質的に円柱形であり、ピラー類似の構造体を形成するが、UBM構造体130は、その他の実施形態では、例えば、長方形、正多角形、不規則多角形、楕円形等のその他の断面形状を有し得る。UBM構造体130は、約1〜100ミクロンの厚さを有し得、約1〜100ミクロンの高さを有し得る。
マイクロバンプ140は、例えば、スズ−銀、インジウム、又は、UBM構造体130と隣接するダイとの電気的機械的接続を形成するのに適切な別のはんだ材料等のはんだ材料を含み得る。カラー138を形成する抗湿潤材料136は、幾つかの実施形態では、第1の材料132及び第2の材料134の側壁上のマイクロバンプ140の濡れを阻止する材料を含む(例えば、抗湿潤材料136は、マイクロバンプ140の材料に非湿潤性の表面を提供する)。抗湿潤材料136は、マイクロバンプ140のはんだ材料に対して極めて低度か無視できる程度の拡散性を有し得る。例えば、幾つかの実施形態では、抗湿潤材料136は、酸化物、窒化物、又はポリイミドを含む。抗湿潤材料136は、幾つかの実施形態では約1000〜5000Åの厚さ、又は幾つかの実施形態では約2000〜2500Åの厚さを有する。一部の実施形態では、抗湿潤材料136は、第1の材料132及び/又は第2の材料134の周囲の少なくとも一部を完全に取り囲むが、他の実施形態では、抗湿潤材料136は、全周囲に満たない範囲を被覆する。抗湿潤材料136はまた、UBM構造体130の高さの少なくとも一部に沿って延伸し;例えば、抗湿潤材料136は、UBM構造体130の高さの少なくとも80%を被覆する。抗湿潤材料136を含むカラー138は、UBM構造体130の第1の材料132及び第2の材料134の側壁に沿ってマイクロバンプ140からのはんだの濡れを除去するか削減する。本技術に従ったUBM構造体、カラー、及びマイクロバンプを形成する更なる実施形態及び態様は、図2A〜図3Gを参照しながら以下に記述される。
図2A〜図2Hは、UBM構造体、カラー、及びマイクロバンプを形成するための方法の様々な段階の間の基板アセンブリ100の一部における半導体ダイ120を概略的に図示する断面図である。図2Aを参照すると、該方法のこの段階において、半導体ダイ120は、誘電性材料116上と、基板110の第2の側114に近接する相互接続部124の一部分上とに形成されたシード構造体240と、シード構造体240上のマスク250
とを有する。シード構造体240は、相互接続部124の位置と関連付けられた第1の領域242と、第1の領域242間の第2の領域244とを有し得る。シード構造体240は、UBM構造体のベース又は第1の材料をめっきするのに適切な単一の材料であり得る。一部の実施形態では、シード構造体240は、バリア材料とバリア材料上のシード材料とを含む。バリア材料は、タンタル、窒化タンタル、チタン、チタン−タングステン、又は誘電性材料116及び基板120中へのUBM材料の拡散を阻止する別の材料であり得る。シード材料は、銅、銅合金、ニッケル、又は周知の電気めっき若しくは非電気めっき技術を用いてシード材料に第1の材料132(図1)をめっきするのに適切なその他の材料であり得る。実施する上で、シード構造体240は、相互接続部124の導電性プラグ128と一体化され得る。
マスク250は、シード構造体240の第1の領域242と整列された複数の開口部252を有するレジスト材料又はその他の適切なマスク材料であり得る。より詳細を以下で説明するが、UBM構造体は、マスク250の開口部252中に形成される。マスク材料250の開口部252は、図2Aに示されるように側面から見た場合にT型の断面を有し、上部254は下部256よりも広い開口を有する。マスク250のこのT型開口部252は、フォトリソグラフィ又はその他の適切な技術の間、リーククロムマスクを用いて形成され得る。
図2Bは、シード構造体240の露出した第1の領域242(図2A)上に第1の材料132が形成された後の半導体ダイ120を概略的に図示する断面図である。一実施形態では、シード構造体240は、物理蒸着処理を用いて堆積された銅シード材料を含み、第1の材料132は、周知の電気めっき又は非電気めっき技術を用いて銅シード材料上に堆積された銅を含む。第1の材料132は、それ故、UBM構造体のベース材料を画定し得る。一実施形態では、第1の材料132は、処理のこの段階では第1の直径(例えば、30μm)と高さ(30μm)とを有するが、第1の材料132の直径及び高さは、具体的な半導体ダイ120の特定の構造に従って任意のその他の寸法を有し得る。
図2Cは、第1の材料132上に第2の材料134があるように第2の材料134が開口部252中に配置された後の半導体ダイ120を概略的に図示する断面図である。第2の材料134は、第2の材料134上に相互接続部を形成するのに適した濡れ面を提供するニッケル又はその他の適切な材料を含み得る。第1の材料132及び第2の材料134は、UBM構造体130を画定し得る。処理のこの段階では、半導体ダイ120は、シード構造体240を通じて電気的に相互に結合される複数のUBM構造体130を有する。幾つかの実施形態では、第2の材料は完全に省略され得、UBM構造体は第1の材料のみを含み得る。
図2Dは、本技術の一実施形態に従ってカラー開口部258を画定するためにマスク250の一部を除去した後の半導体ダイ120を概略的に図示する断面図である。マスク250は、異方性ドライエッチング及びドライクリーニングを用いてエッチングされ得る。ドライエッチングは、UBM構造体130に隣接するカラー開口部158中でマスク250が完全に除去されるまで、半導体ダイ120に渡って十分一様にマスク250を除去し得る。カラー開口部158は、カラー138(図1)の厚さを画定し得、例えば、約1000〜5000Åの厚さ又は約2000〜2500Åの厚さを有する。ドライエッチングのパラメータ(例えば、化学的性質、電力、温度等)は、後続する堆積ステップ用のマスク250を準備するためのエッチングの間、マスク250を硬化するために調整され得る。
図2Eは、本技術の一実施形態に従って抗湿潤材料136が形成された後の半導体ダイ120を概略的に図示する断面図である。抗湿潤材料136は、マイクロバンプ140(
図1)のはんだ材料が液相において容易には濡れず、且つ/又はマイクロバンプ140(図1)のはんだ材料に対して低度の若しくは無視できる程度の拡散性を有する材料であり得る。抗湿潤材料136は、酸化物、窒化物、ポリイミド、又はその他の適切な材料であり得る。一実施形態では、抗湿潤材料136は、低温(例えば、150℃未満)プラズマ増強化学蒸着又はその他の適切な処理により形成されたオルトケイ酸テトラエチル(TEOS)である。抗湿潤材料136は、マスク250及び開口部252上にブランケット層として形成され、UBM構造体130を被覆することと、カラー開口部258(図2D)を充填することとを含む。
図2Fは、本技術の一実施形態に従って抗湿潤材料136の一部分が除去された後の半導体ダイ120を概略的に図示する断面図である。抗湿潤材料136の一部分を除去するために、緩衝酸化物エッチング(buffered oxide etch)又はスペーサエッチング、及び
その後に続くウェットクリーニングが用いられ得る。図2Fに示されるように、抗湿潤材料136の多くは、カラー138を形成するためにカラー開口部258(図2D)中に抗湿潤材料136の残余部分のみが存在するまで除去されている。他の実施形態では、カラー138は第2の材料134に関して埋め込まれ得るが、幾つかの実施形態では、カラー138は第2の材料134と実質的に同一平面にあり得る。
図2Gは、本技術の一実施形態に従ってマイクロバンプ140が形成された後の半導体ダイ120を概略的に図示する断面図である。マイクロバンプ140は、UBM130及びカラー138の上部の開口部252をめっきするはんだ材料(例えば、スズ−銀又はインジウムはんだ)から形成され得る。幾つかの実施形態では、マイクロバンプ140は、約3〜50ミクロンの高さを有し得る。
図2Hは、UBM構造体130同士を互いに電気的に分離するためにマスク250とシード構造体240の一部分とが除去された後の半導体ダイ120を概略的に図示する断面図である。マスク250は、ウェットフォトレジスト剥離又はその他の適切な技術を用いて除去され得、その後、シード構造体240の第2の領域244は、シード構造体の材料を除去するのに適したウェットエッチングを用いて除去され得る。現時点において、UBM構造体は相互に電気的に分離される。
図3A〜図3Gは、本技術の別の実施形態に従ってUBM構造体、カラー、及びマイクロバンプを製造する様々な段階の間の基板アセンブリ100の一部における半導体ダイ120を概略的に図示する断面図である。図3Aを参照すると、該方法のこの段階では、半導体ダイ120は、誘電性材料116上と、基板110の第2の側114に近接する相互接続部124の一部分上のシード構造体240を有し、マスク250はシード構造体240上にある。シード構造体240は、相互接続部124の位置に関連付けられた第1の領域242と、第1の領域242間の第2の領域244とを有する。マスク250は、シード構造体240の第1の領域242と整列された複数の開口部252を有する、レジスト材料又はその他の適切なマスク材料であり得る。以下でより詳細を説明するように、UBM構造体は、マスク250の開口部252中に形成される。
図3Bは、本技術の一実施形態に従って抗湿潤材料136が形成された後の半導体ダイ120を概略的に図示する断面図である。抗湿潤材料136は、マイクロバンプ140(図1)のはんだ材料が液相において容易には濡れず(例えば、被覆せず)、且つ/又はマイクロバンプ140(図1)のはんだ材料に対して低度の若しくは無視できる程度の拡散性を有する材料であり得る。抗湿潤材料136は、酸化物(例えば、オルトケイ酸テトラエチル(TEOS)又は別の酸化物)、窒化物、ポリイミド、又はその他の適切な材料であり得る。一実施形態では、抗湿潤材料136は、低温(例えば、150℃未満)プラズマ増強化学蒸着又はその他の適切な処理により形成されたオルトケイ酸テトラエチル(T
EOS)である。抗湿潤材料136は、マスク250及び開口部252上にブランケット層として形成される。
図3Cは、本技術の一実施形態に従って抗湿潤材料136の一部分が除去された後の半導体ダイ120を概略的に図示する断面図である。抗湿潤材料136の一部分を除去するために、スペーサ酸化物エッチング及びその後に続くウェットクリーニングが用いられる。図3Cに示されるように、抗湿潤材料136の被覆部分は、抗湿潤材料136の残余部分のみが開口部152の側壁に沿うまで除去されている。
図3Dは、シード構造体240の露出した第1の領域242(図3C)上に第1の材料132が形成され、第1の材料132上に第2の材料134が形成された後の半導体ダイ120を概略的に図示する断面図である。一実施形態では、シード構造体240は、物理蒸着処理を用いて堆積された銅シード材料を含み、第1の材料132は、周知の電気めっき又は非電気めき処理を用いて銅シード材料に堆積された銅を含む。第1の材料132及び第2の材料134は、抗湿潤材料136により取り囲まれたUBM構造体130を画定し得る。処理のこの段階では、半導体ダイ120は、シード構造体240を通じて電気的に相互に結合される複数のUBM構造体130を有する。幾つかの実施形態では、第2の材料は完全に省略され得、UBM構造体は第1の材料のみを含み得る。
図3Eは、カラー138を形成するために抗湿潤材料136の更なる一部分が除去された後の半導体ダイ120を概略的に図示する断面図である。図3Bに関して上述した処理と同様に、抗湿潤材料136の追加の一部分は、スペーサ酸化物エッチング及びその後に続くウェットクリーニングを用いて除去され得る。図3Eに示されるように、開口部152の側壁に沿う抗湿潤材料136の残余部分のみが第2の材料134と実質的に同一平面にあり、それによってカラー138を形成するまで、抗湿潤材料136は除去されている。
図3Fは、マイクロバンプ140が形成された後の半導体ダイ120を概略的に図示する断面図である。マイクロバンプ140は、UBM構造体130及びカラー138の上部の開口部252中にめっきされるはんだ材料(例えば、スズ−銀又はインジウムはんだ)から形成される。幾つかの実施形態では、マイクロバンプ140は、約3〜50ミクロンの高さを有し得る。
図3Gは、UBM構造体130同士を互いに電気的に分離するためにマスク250及びシード構造体240が除去された後の半導体ダイ120を概略的に図示する断面図である。マスク250は、ウェットフォトレジスト剥離又はその他の適切な技術を用いて除去され得、その後、UBM構造体130を相互に電気的に分離するために適切なウェットエッチングを用いてシード構造体240の第2の領域244が除去され得る。
図4は、本技術の実施形態に従って半導体ダイ上のUBM構造体を形成するための一実施形態の方法400のフローチャートである。この実施形態では、方法400は、シード構造体上にマスクを形成すること(ブロック402)と、シード構造体の露出領域に第1の材料をめっきすること(ブロック404)とを含む。マスクは、例えば、半導体基板を少なくとも部分的に通じて延伸する相互接続部に電気的に結合されるシード構造体の領域を露出する開口部を含む。一部の実施形態は、マスクの開口部は、TSV上に重ねられる。方法400は、第1の材料上の開口部中に第2の材料を堆積し、それによってUBM構造体を形成すること(ブロック406)と、UBM構造体の周囲のカラー領域をエッチングすること(ブロック408)とを更に含む。該方法は、UBM構造体上であってカラー領域の中に抗湿潤材料を形成すること(ブロック410)と、続いて、カラー領域中の第2の材料と実質的に同一平面になるまで抗湿潤材料をエッチングすること(ブロック41
2)とにより継続する。このステップは、UBM構造体を取り囲むカラーを形成する。方法400は、UBM構造体上にマイクロバンプを形成すること(ブロック414)により継続する。マスクはその後除去され、続いて、ウェットエッチングによりUBM構造体間のシード材料の露出部分が除去される。
図5は、本技術の実施形態に従って半導体ダイ上にUBM構造体を形成するための一実施形態の方法500のフローチャートである。この実施形態では、方法500は、シード構造体上にマスクを形成すること(ブロック502)と、マスク及びシード材料の露出部分上に抗湿潤材料を形成すること(ブロック504)とを含む。マスクは、例えば、半導体基板を少なくとも部分的に通じて延伸する相互接続部に電気的に結合されるシード構造体の領域を露出する開口部を含む。一部の実施形態では、マスクの開口部は、TSV上に重ねられる。方法500は、シード構造体が露出され、残余の抗湿潤材料が開口部中のカラーを画定するまで抗湿潤材料をエッチングすること(ブロック506)を更に含む。例えば、抗湿潤材料は、緩衝酸化物エッチング又はスペーサエッチングと、その後に続くウェットクリーニングとを用いてエッチングされ得る。方法500は、開口部中のシード材料上の第1の材料をめっきすること(ブロック508)と、開口中の第1の導電性材料上に第2の導電性材料を形成し、それによりUBM構造体を形成すること(510)とにより継続する。方法500は、開口部中の第2の導電性材料と実質的に同一平面にカラーがなるまで抗湿潤材料をその後除去する(ブロック512)。方法500は、UBM構造体上にマイクロバンプを形成すること(ブロック514)により継続する。マスクは、その後除去され、続いて、ウェットエッチングによりUBM構造体間のシード材料の露出部分が除去される。
図1〜図5を参照しながら上述したフィーチャを有する半導体デバイスの任意の1つは、図6に概略的に示されたシステム600を代表的な一例とする、より大きな及び/又はより複雑な無数のシステムの何れかに組み込まれ得る。システム600は、プロセッサ602、メモリ604(例えば、SRAM、DRAM、フラッシュメモリ、及び/若しくはその他のメモリデバイス)、入出力デバイス606、並びに/又はその他のサブシステム若しくは構成要素608を含み得る。図1〜図5を参照しながら上述した半導体デバイス100は、図6に示される要素の何れかに含まれ得る。もたらされるシステム600は、適切な計算、処理、記憶、検出、画像化、及び/又はその他の機能の多種多様な何れかを実行するように構成され得る。したがって、システム600の代表例は、例えば、デスクトップコンピュータ、ラップトップコンピュータ、インターネット家電、ハンドヘルドデバイス(例えば、パームトップコンピュータ、ウェアラブルコンピュータ、セルラー若しくは携帯電話、携帯情報端末、音楽プレーヤ等)、タブレット、マルチプロセッサシステム、プロセッサベース若しくはプログラマブルな家庭用電化製品、ネットワークコンピュータ、並びにマイクロコンピュータ等のコンピュータ及び/又はその他のデータプロセッサを含むが、これらに限定されない。システム600の追加の代表例は、照明、カメラ、車両等を含む。これら及びその他の例に関して、システム600は、単一のユニットに包含され得、又は例えば、通信ネットワークを通じて、多数の接続ユニットを介して分配され得る。システム600の構成要素は、それ故、ローカル及び/又は遠隔の記憶保存デバイス、並びに多種多様な任意の適切なコンピュータ読み取り可能媒体を含み得る。
前述の内容から、本発明の特定の実施形態が説明の目的で本明細書に記載されているが、本発明の範囲から逸脱することなく様々な変更が行われてもよいことが理解されるであろう。したがって、発明は、添付の請求項の範囲による場合を除いて限定されない。

Claims (10)

  1. 固体状態の構成要素を有する半導体材料と、
    前記半導体材料を少なくとも部分的に通って延伸する相互接続部と、
    前記相互接続部に電気的に結合されたアンダーバンプメタル(UBM)構造体であって、前記UBM構造体は、上面、底面、及び前記上面と前記底面との間に延伸する側壁を有し、前記UBM構造体は、前記半導体材料の上面上に誘電体材料を介して配置され且つ前記相互接続部に直接接触する第1の導電性材料と、前記第1の導電性材料上に配置された第2の導電性材料とを含む、UBM構造体と、
    前記第1の導電性材料の全部ではない一部と、前記第2の導電性材料の少なくとも一部とを取り囲むように、前記UBM構造体の前記側壁の少なくとも一部を取り囲むカラーであって、前記カラーは、前記UBM構造体の前記上面よりも上方へ延伸しておらず、かつ、前記半導体材料に接触していない、カラーと、
    前記UBM構造体の前記上面上に配置されたはんだ材料と、
    を含み、
    前記カラーは、酸化物、窒化物、又はポリイミドのうちの少なくとも1つを含む抗湿潤材料を含み、前記はんだ材料は液相において前記抗湿潤材料を容易には濡らさない、半導体ダイ。
  2. 前記UBM構造体はピラーであり、前記カラーは前記ピラーの前記側壁のみを被覆する、請求項1に記載の半導体ダイ。
  3. 前記カラーは、前記UBM構造体の前記側壁の高さの一部に沿って延伸し、かつ、前記UBM構造体の前記上面を被覆しない、請求項1に記載の半導体ダイ。
  4. 前記カラーは、前記UBM構造体の前記側壁の高さの少なくとも80%に沿って延伸する、請求項3に記載の半導体ダイ。
  5. 前記カラーの上面は、前記UBM構造体の前記上面と実質的に同一平面にある、請求項1に記載の半導体ダイ。
  6. 前記UBM構造体は約1〜100ミクロンの高さを有する、請求項1に記載の半導体ダイ。
  7. 固体状態の構成要素を有する半導体材料と、
    前記半導体材料を少なくとも部分的に通って延伸する相互接続部と、
    前記相互接続部に電気的に結合されたアンダーバンプメタル(UBM)構造体であって、前記UBM構造体は、上面、底面、及び前記上面と前記底面との間に延伸する側壁を有し、前記UBM構造体は、前記半導体材料の上面上に誘電体材料を介して配置され且つ前記相互接続部に直接接触する第1の導電性材料と、前記第1の導電性材料上に配置された第2の導電性材料とを含む、UBM構造体と、
    前記第1の導電性材料の全部ではない一部と、前記第2の導電性材料の少なくとも一部とを取り囲むように、前記UBM構造体の前記側壁の少なくとも一部を取り囲むカラーであって、前記カラーは、前記UBM構造体の前記側壁の高さの一部に沿って延伸し、かつ、前記UBM構造体の前記上面を被覆しておらず、かつ、前記半導体材料に接触していない、カラーと、
    前記UBM構造体の前記上面上に配置されたはんだ材料と、
    を含み、
    前記カラーは、酸化物、窒化物、又はポリイミドのうちの少なくとも1つを含む抗湿潤材料を含み、前記はんだ材料は液相において前記抗湿潤材料を容易には濡らさない、半導体ダイ。
  8. 前記カラーは、前記UBM構造体の前記側壁の前記高さの少なくとも80%に沿って延伸する、請求項7に記載の半導体ダイ。
  9. 前記カラーの上面は、前記UBM構造体の前記上面と実質的に同一平面にある、請求項7に記載の半導体ダイ。
  10. アンダーバンプメタル(UBM)構造体の周辺領域に、酸化物、窒化物、又はポリイミドのうちの少なくとも1つを含む抗湿潤材料をメッキし、該抗湿潤材料を前記UBM構造体の上面と同一平面までエチングすることにより、前記抗湿潤材料からカラーを形成することであって、前記カラーは、前記UBM構造体の前記上面を被覆することなく前記UBM構造体の側壁の少なくとも一部を取り囲み、前記UBM構造体は、半導体材料の上面上に誘電体材料を介して配置され且つ相互接続部に直接接触する第1の導電性材料と、前記第1の導電性材料上に配置された第2の導電性材料とを含み、前記カラーは、前記第1の導電性材料の全部ではない一部と、前記第2の導電性材料の少なくとも一部とを取り囲み、かつ、前記半導体材料に接触しない、ことと、
    前記UBM構造体の前記上面上にはんだ材料を配置することであって、前記はんだ材料が液相である場合に前記はんだ材料は前記抗湿潤材料を容易には濡らさない、ことと、
    を含む、方法。
JP2020005714A 2015-09-14 2020-01-17 アンダーバンプメタル構造体用のカラー並びにそれに関連するシステム及び方法 Active JP6970219B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/853,807 2015-09-14
US14/853,807 US9780052B2 (en) 2015-09-14 2015-09-14 Collars for under-bump metal structures and associated systems and methods
JP2018512974A JP6672452B2 (ja) 2015-09-14 2016-08-03 アンダーバンプメタル構造体用のカラー並びに関連するシステム及び方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2018512974A Division JP6672452B2 (ja) 2015-09-14 2016-08-03 アンダーバンプメタル構造体用のカラー並びに関連するシステム及び方法

Publications (2)

Publication Number Publication Date
JP2020074436A JP2020074436A (ja) 2020-05-14
JP6970219B2 true JP6970219B2 (ja) 2021-11-24

Family

ID=58237121

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2018512974A Active JP6672452B2 (ja) 2015-09-14 2016-08-03 アンダーバンプメタル構造体用のカラー並びに関連するシステム及び方法
JP2020005714A Active JP6970219B2 (ja) 2015-09-14 2020-01-17 アンダーバンプメタル構造体用のカラー並びにそれに関連するシステム及び方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2018512974A Active JP6672452B2 (ja) 2015-09-14 2016-08-03 アンダーバンプメタル構造体用のカラー並びに関連するシステム及び方法

Country Status (7)

Country Link
US (3) US9780052B2 (ja)
EP (1) EP3350829A4 (ja)
JP (2) JP6672452B2 (ja)
KR (1) KR102124136B1 (ja)
CN (2) CN113643994A (ja)
TW (1) TWI623064B (ja)
WO (1) WO2017048388A1 (ja)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9780052B2 (en) 2015-09-14 2017-10-03 Micron Technology, Inc. Collars for under-bump metal structures and associated systems and methods
US9786619B2 (en) 2015-12-31 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US9754905B1 (en) * 2016-10-13 2017-09-05 International Business Machines Corporation Final passivation for wafer level warpage and ULK stress reduction
US10636759B2 (en) * 2017-01-31 2020-04-28 Globalfoundries Inc. Methods of forming integrated circuit structure for joining wafers and resulting structure
DE102017110073A1 (de) * 2017-05-10 2018-11-15 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines strahlungsemittierenden Halbleiterbauelements und strahlungsemittierendes Halbleiterbauelement
US10276528B2 (en) * 2017-07-18 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor device and manufacturing method thereof
US11640968B2 (en) * 2018-11-06 2023-05-02 Texas Instruments Incorporated Inductor on microelectronic die
US10957664B2 (en) * 2019-05-29 2021-03-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
KR20210086198A (ko) 2019-12-31 2021-07-08 삼성전자주식회사 반도체 패키지

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5736456A (en) * 1996-03-07 1998-04-07 Micron Technology, Inc. Method of forming conductive bumps on die for flip chip applications
CN1199536C (zh) * 1999-10-26 2005-04-27 伊比登株式会社 多层印刷配线板及多层印刷配线板的制造方法
US6569753B1 (en) * 2000-06-08 2003-05-27 Micron Technology, Inc. Collar positionable about a periphery of a contact pad and around a conductive structure secured to the contact pads, semiconductor device components including same, and methods for fabricating same
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
US6413851B1 (en) 2001-06-12 2002-07-02 Advanced Interconnect Technology, Ltd. Method of fabrication of barrier cap for under bump metal
US7008867B2 (en) * 2003-02-21 2006-03-07 Aptos Corporation Method for forming copper bump antioxidation surface
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7488680B2 (en) * 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers
US20090197114A1 (en) * 2007-01-30 2009-08-06 Da-Yuan Shih Modification of pb-free solder alloy compositions to improve interlayer dielectric delamination in silicon devices and electromigration resistance in solder joints
US7485564B2 (en) * 2007-02-12 2009-02-03 International Business Machines Corporation Undercut-free BLM process for Pb-free and Pb-reduced C4
KR20090059504A (ko) * 2007-12-06 2009-06-11 삼성전자주식회사 반도체 장치 및 그 제조방법들
US8039964B2 (en) * 2008-02-27 2011-10-18 International Business Machines Corporation Fluorine depleted adhesion layer for metal interconnect structure
JP2009231682A (ja) 2008-03-25 2009-10-08 Citizen Watch Co Ltd 半導体装置およびその製造方法
US8138036B2 (en) * 2008-08-08 2012-03-20 International Business Machines Corporation Through silicon via and method of fabricating same
US7956442B2 (en) * 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
TW201019440A (en) * 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
US7915741B2 (en) * 2009-02-24 2011-03-29 Unisem Advanced Technologies Sdn. Bhd. Solder bump UBM structure
US8841766B2 (en) 2009-07-30 2014-09-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8324738B2 (en) 2009-09-01 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned protection layer for copper post structure
TWI406380B (zh) * 2009-09-23 2013-08-21 Advanced Semiconductor Eng 具有穿導孔之半導體元件及其製造方法及具有穿導孔之半導體元件之封裝結構
US8637392B2 (en) * 2010-02-05 2014-01-28 International Business Machines Corporation Solder interconnect with non-wettable sidewall pillars and methods of manufacture
US20110227216A1 (en) * 2010-03-16 2011-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Under-Bump Metallization Structure for Semiconductor Devices
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US8232193B2 (en) * 2010-07-08 2012-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming Cu pillar capped by barrier layer
US8241963B2 (en) * 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
US8039385B1 (en) * 2010-09-13 2011-10-18 Texas Instruments Incorporated IC devices having TSVS including protruding tips having IMC blocking tip ends
CN102593068B (zh) * 2011-01-11 2015-08-19 颀邦科技股份有限公司 斜锥状凸块结构
CN102800599B (zh) * 2011-05-25 2015-03-25 颀邦科技股份有限公司 凸块工艺及其结构
CN102867758B (zh) * 2011-07-08 2015-12-02 颀邦科技股份有限公司 凸块制造工艺及其结构
US8847388B2 (en) 2011-10-06 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Bump with protection structure
CN103165482B (zh) * 2011-12-13 2015-06-17 颀邦科技股份有限公司 凸块工艺
US9190375B2 (en) * 2014-04-09 2015-11-17 GlobalFoundries, Inc. Solder bump reflow by induction heating
US9780052B2 (en) 2015-09-14 2017-10-03 Micron Technology, Inc. Collars for under-bump metal structures and associated systems and methods

Also Published As

Publication number Publication date
TW201721811A (zh) 2017-06-16
US20210151400A1 (en) 2021-05-20
US9780052B2 (en) 2017-10-03
US20170077052A1 (en) 2017-03-16
CN113643994A (zh) 2021-11-12
EP3350829A1 (en) 2018-07-25
CN108028229A (zh) 2018-05-11
KR102124136B1 (ko) 2020-06-18
KR20180043382A (ko) 2018-04-27
WO2017048388A1 (en) 2017-03-23
US20170352633A1 (en) 2017-12-07
JP6672452B2 (ja) 2020-03-25
CN108028229B (zh) 2021-08-31
EP3350829A4 (en) 2019-04-03
TWI623064B (zh) 2018-05-01
JP2020074436A (ja) 2020-05-14
US10886244B2 (en) 2021-01-05
JP2018526833A (ja) 2018-09-13

Similar Documents

Publication Publication Date Title
JP6970219B2 (ja) アンダーバンプメタル構造体用のカラー並びにそれに関連するシステム及び方法
US9530759B2 (en) 3D package with through substrate vias
US9633929B2 (en) TSV formation
CN108122875B (zh) 半导体装置及半导体封装
US10950565B2 (en) Interconnect structures for preventing solder bridging, and associated systems and methods
US9966347B2 (en) Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
US9929081B2 (en) Interposer fabricating process
TWI569316B (zh) 半導體晶圓之接合結構的形成方法
US20220068819A1 (en) Front end of line interconnect structures and associated systems and methods
US20220068820A1 (en) Front end of line interconnect structures and associated systems and methods
TWI556385B (zh) 半導體元件、製作方法及其堆疊結構
TW202414736A (zh) 半導體裝置及其形成方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200212

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200212

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20210210

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210330

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210621

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210720

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20210720

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20211005

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20211028

R150 Certificate of patent or registration of utility model

Ref document number: 6970219

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150