CN107408552A - 薄型低翘曲扇出封装件中的双面安装存储器集成 - Google Patents

薄型低翘曲扇出封装件中的双面安装存储器集成 Download PDF

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Publication number
CN107408552A
CN107408552A CN201680019199.XA CN201680019199A CN107408552A CN 107408552 A CN107408552 A CN 107408552A CN 201680019199 A CN201680019199 A CN 201680019199A CN 107408552 A CN107408552 A CN 107408552A
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CN
China
Prior art keywords
nude film
mold compound
rdl
packaging part
nude
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CN201680019199.XA
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English (en)
Inventor
翟军
胡坤忠
钟重华
庞蒙志
S·Y·杨
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Apple Inc
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Apple Computer Inc
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Publication of CN107408552A publication Critical patent/CN107408552A/zh
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Abstract

本发明描述了封装件以及形成方法。在实施方案中，封装件包括直接在顶部裸片(110)上形成的再分配层(RDL)(130)，以及安装在RDL的背表面上的底部裸片(150)。

Description

薄型低翘曲扇出封装件中的双面安装存储器集成
技术领域
本文所述的实施方案涉及半导体封装。更具体地，实施方案涉及扇出封装件及制造方法。
背景技术
对便携式和移动电子设备诸如移动电话、个人数字助理(PDA)、数字相机、便携式播放器、游戏设备、和其他移动设备的当前市场需求要求将更多性能和特征集成到越来越小的空间中。因此，各种多裸片封装解决方案诸如系统级封装(SiP)和堆叠封装(PoP)变得更加普及，以满足对较高裸片/部件密度设备的需求。在一个具体实施中，存储器裸片或封装件(例如，动态随机存取存储器(DRAM))堆叠在逻辑裸片或封装件(例如，专用集成电路(ASIC))或片上系统(SoC)的顶部上。随着便携式和移动电子设备的市场的发展，存储器裸片或封装件需要更大的存储能力。在一个具体实施中，多个存储器裸片竖直堆叠以增加顶部存储器裸片封装件中的存储器。堆叠的裸片可使用引线接合或通过硅通孔互连。
发明内容
描述了双面封装件结构及其制造方法。在实施方案中，封装件包括粘结到再分配层(RDL)的正面的一个或多个第一裸片，以及安装在RDL的背面上的一个或多个第二裸片。例如，第二裸片可使用合适的表面安装技术来安装，诸如倒装芯片和导电凸块，诸如焊料凸块。RDL的第一再分配线直接形成在第一裸片的第一接触垫上，并且第一模制化合物将一个或多个第一裸片包封在RDL的正面上。多个导电柱从RDL的背面延伸，并且第二模制化合物将一个或多个第二裸片以及多个导电柱包封在RDL的背面上。多个导电凸块可位于多个导电柱上。
根据实施方案，可使用各种配置来减小封装件高度。例如，第一模制化合物可以不完全覆盖一个或多个第一裸片的顶表面，并且/或者第二模制化合物可以不完全覆盖一个或多个第二裸片的底表面。一个或多个第一裸片的顶表面和模制化合物的顶表面可为共面的。同样，一个或多个第二裸片的底表面、多个导电柱的底表面和/或第二模制化合物的底表面可为共面的。例如，共面表面可通过蚀刻或后磨操作来实现。在特定实施方案中，一个或多个顶部裸片和底部裸片是存储器裸片。
在实施方案中，通过将一个或多个第一裸片放置在承载衬底上，并且利用第一模制化合物将一个或多个第一裸片包封在承载衬底上来形成扇出封装件。然后移除承载衬底并且再分配层(RDL)在第一模制化合物和第一裸片上形成，其中RDL的再分配线沿着第一裸片的底表面直接形成在接触垫上。多个柱在RDL的背面上形成，并且一个或多个第二裸片安装在RDL的背面上在多个导电柱的周边内部。例如，第二裸片可使用合适的表面安装技术来安装，诸如倒装芯片和导电凸块，诸如焊料凸块。一个或多个第二裸片用第二模制化合物包封，并且一个或多个导电凸块可在多个导电柱上形成。
根据实施方案，可使用各种配置来减小封装件高度。例如可减小第一模制化合物的厚度以暴露一个或多个第一裸片。此外，第一裸片的厚度也可减小，从而产生根据实施方案的平面顶部封装件表面。同样，可减小第二模制化合物的厚度以暴露一个或多个第二裸片。此外，第二裸片的厚度也可减小，从而产生平面底部封装件表面。
附图说明
图1是根据实施方案的放置在承载衬底上的多个裸片的横截面侧视图图示。
图2是根据实施方案的包封在第一模制化合物中的多个裸片的横截面侧视图图示。
图3是根据实施方案的在移除承载衬底之后的重构结构的横截面侧视图图示。
图4是根据实施方案的在重构结构上形成的RDL的横截面侧视图图示。
图5A是根据实施方案的在重构结构上形成的RDL的横截面侧视图图示。
图5B是根据实施方案的在重构结构上形成的RDL的特写横截面侧视图图示。
图6是根据实施方案的在RDL上形成导电柱的横截面侧视图图示。
图7A-图7B是根据实施方案的在RDL上安装多个裸片的横截面侧视图图示。
图8是根据实施方案的施加底部填充材料的特写横截面侧视图图示。
图9是根据实施方案的包封的底部裸片和多个导电柱的横截面侧视图图示。
图10是根据实施方案的具有暴露的底表面的包封的多个导电柱的横截面侧视图图示。
图11是根据实施方案的具有暴露的底表面的包封的底部裸片以及具有暴露的底表面的多个导电柱的横截面侧视图图示。
图12是根据实施方案的选择性地图案化的模制化合物的横截面侧视图图示。
图13是根据实施方案的在多个导电柱的底表面上包括导电凸块的切割封装件的横截面侧视图图示。
图14是根据实施方案的包括变薄的顶部裸片和底部裸片以及模制化合物的切割封装件的横截面侧视图图示。
图15是示出根据实施方案的形成扇出封装件的过程的流程图。
具体实施方式
实施方案描述了扇出封装件及制造方法，尤其是利用扇出晶圆级封装件(FOWLP)技术的方法。裸片向下扇出技术是多功能扇出晶圆级封装件(FOWLP)技术，其可用于满足更高裸片/部件密度设备的需求。FOWLP可致使将裸片包封在承载衬底上的模制化合物中，移除承载衬底，然后在裸片和模制化合物上建立再分布层(RDL)。模制化合物为电扇出提供附加区域，以及可选地，更高的I/O计数。
实施方案描述了其中在RDL的两侧上安装裸片的双面安装扇出封装件。在各个方面中，根据所描述的实施方案的封装配置可允许总封装件z高度减小、增加的设备密度(或存储器容量)和/或封装件翘曲控制，这可另外允许在受控的翘曲公差内形成较宽的封装件。
在实施方案中，封装件包括粘结到RDL的正面的一个或多个第一(顶部)裸片，其中RDL的第一再分配线直接在顶部裸片中的一个顶部裸片的第一接触垫上形成。第一模制化合物将一个或多个顶部裸片包封在RDL的正面上。一个或多个第二(底部)裸片可粘结到RDL的背面，并且多个导电柱从RDL的背面延伸。例如，一个或多个底部裸片可在多个导电柱的周边内。第二模制化合物将一个或多个底部裸片包封在RDL的背面上。
在一个方面中，实施方案描述了双面安装的扇出封装件结构，其可允许总封装件z高度减小。例如，直接在顶部裸片上形成RDL可通过以下方式允许总封装件z高度的减小：消除与表面安装过程相关联的对立高度，诸如与常规倒装芯片附接工艺相关联的焊料凸块高度。总封装件z高度的减小可另外归因于对于扇出使用RDL，其可比常规聚合物或层压衬底显著更薄，并且允许消除通常用于PoP和SiP集成中的附加硅或有机插入物。此外，总封装件z高度减小可归因于断开了在PoP解决方案中常见的底部裸片与竖直导体的厚度关联，其中此类厚度关联描述了底部裸片与底部裸片上方的布线层之间的对立高度。根据实施方案，此类对立高度通过将底部裸片安装到RDL的背面来消除。总封装件z高度减小可另外归因于面向RDL的一个或多个顶部裸片和底部裸片。在此类配置中，可以后磨顶部裸片和底部裸片中的任一者或两者以及模制化合物的厚度，从而进一步有助于总封装件z高度减小。
在又一个方面中，控制顶部裸片和底部裸片以及模制化合物的厚度的能力可允许对封装件翘曲的一定程度的控制。因此，根据实施方案，对封装件z高度的控制另外允许对封装件翘曲的控制。控制封装件翘曲的能力可另外允许形成较宽的封装件，以及RDL的正面和背面上的多个裸片的并排位置。
实施方案可应用于诸如但不限于低功率和/或高I/O宽度存储器架构的应用中。实施方案可通过使用RDL和直接芯片附接来实现到相邻功能单元(例如，SOC、芯片组等)的短双数据速率(DDR)信道。实施方案可特别适用于在包括高速度和宽I/O宽度的目标性能方面需要低功率DDR的移动应用。采用高端应用也可通过用于宽I/O互连的细的RDL再分配线宽度和间距，以及按比例加大适当的存储器密度而成为可能。可扩展性可由在RDL的正面和背面上的双重安装存储器裸片来继承。在应用中，封装件可集成到PoP结构中，例如作为PoP堆栈中的顶部存储器封装件，以及用于直接安装到系统板上。通过将封装件单元堆叠在彼此的顶部上，可额外促进向高密度(双级)的进一步按比例加大，所述封装件单元可为相同的。
在各种实施方案中，参照附图来进行描述。然而，某些实施方案可在不存在这些具体细节中的一个或多个具体细节或者不与其他已知的方法和构型相结合的情况下被实施。在以下的描述中，示出许多具体细节诸如特定构型、尺寸工艺等，以提供对实施方案的透彻理解。在其他情况下，未对熟知的半导体工艺和制造技术进行特别详细地描述，以免不必要地模糊实施方案。整个说明书中所提到的“一个实施方案”是指结合实施方案所描述的特定特征、结构、构型或特性被包括在至少一个实施方案中。因此，整个说明书中多处出现短语“在一个实施方案中”不一定是指相同的实施方案。此外，特定特征、结构、构型或特性可以任何适当的方式组合在一个或多个实施方案中。
本文所使用的术语“在...之上”、“在...上方”、“至”、“在...之间”和“在...上”可指一层相对于其他层的相对位置。一层在另一层“之上”、“上方”或“上”或者键合“至”另一层或者与另一层“接触”可为直接与其他层接触或可具有一个或多个居间层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
现在参考图1，横截面侧视图图示提供了安装在承载衬底102上的多个第一(顶部)裸片110，诸如硅晶片、玻璃面板、金属面板等。承载衬底102可另外包括用于安装多个裸片的粘合剂层。在实施方案中，每个裸片110包括具有一个或多个暴露接触垫112的底表面113和可选的钝化层114。在特定实施方案中，裸片110是存储器裸片，诸如但不限于动态随机存取存储器(DRAM)。裸片110可为具有相同尺寸、形状和存储器容量的相同裸片。另选地，裸片110可为不同类型的裸片，或者例如具有不同尺寸、形状和/或容量的存储器裸片。
虽然实施方案描述了扇出封装件，并且具体地讲，扇出存储器封装件，但实施方案不一定限于存储器裸片，并且所描述的特定封装配置和序列可用于其它封装件，并且包括不同类型的裸片(例如，逻辑)或部件，诸如无源设备，包括电容器或电感器，微机电系统(MEMS)设备，传感器等。
如图2所示，多个裸片110随后被包封在承载衬底102上的第一模制化合物120中。例如，第一模制化合物120可包括热固性交联树脂(例如，环氧树脂)，但是其它材料可如已知那样用于电子封装中。包封可使用合适的技术诸如但不限于传递模制、压缩模制和层压来完成。如本文所使用的，“包封的”不要求所有表面被包封在模制化合物内。在图2所示的实施方案中，裸片110的横向侧被封入模制化合物120中，并且模制化合物120的顶表面121也在最高裸片110的顶表面111上方形成，但是不需要模制化合物覆盖最高裸片110的顶表面111。在实施方案中，模制化合物120跨承载衬底102为连续的，从而覆盖多组裸片110，该裸片随后将例如沿着虚线被切割以形成独立封装件。
根据实施方案，一个或多个裸片110包括在每个封装件中。在实施方案中，多个裸片110包括在每个封装件中。如下文进一步详细所述，控制在RDL的相对侧上的裸片和模制化合物的厚度，以及因此控制封装件翘曲的能力可另外允许形成较宽的封装件，以及RDL的正面和背面上的多个裸片的并排位置。
包括任何可选的粘合剂层的承载衬底102随后可被移除，以暴露如图3所示的裸片110的底表面113，从而导致重构晶片或面板125的形成。给定制造方法，在实施方案中，第一模制化合物120的底表面122可与裸片110的底表面113共面，并且因此与接触垫112以及任选地与裸片110的底表面113对应的钝化层114的暴露表面共面。
现在参考图4，再分配层(RDL)130形成在图3的重构晶片/面板125上，其中RDL 130的正表面131在第一模制化合物120和一个或多个裸片110上形成。RDL 130可包括单个再分配线132或多个再分配线132以及电介质层138。RDL 130可通过逐层工艺形成，并且可使用薄膜技术形成。在实施方案中，RDL 130包括嵌入式再分配线132(嵌入式迹线)。例如，再分配线132可通过首先形成种子层随后形成金属(例如，铜)图案来创建。另选地，再分配线可通过沉积(例如，溅射)和蚀刻来形成。再分配线132的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。再分配线132的金属图案随后被嵌入任选地图案化的电介质层138中。电介质层138可为任何合适的材料，诸如氧化物或聚合物(例如，聚酰亚胺)。
根据实施方案，RDL 130可具有小于常规有机衬底或层压衬底的厚度。例如，常规六层有机衬底或层压衬底可具有300μm–500μm的厚度。RDL 130的厚度可由导电再分配线132和电介质层138的数量以及形成方式确定。根据实施方案，导电再分配线可具有大约3-10μm的厚度，并且电介质层具有2-5μm的厚度。根据实施方案的RDL可另外允许与常规有机衬底或层压衬底相比更窄的线距宽度(细的间距)和更细的线。在实施方案中，RDL 130具有小于50μm，或更具体地讲大约30μm或更小，诸如大约20μm的总厚度。在例示的实施方案中，再分配线132沿着裸片110的底表面113直接在接触垫112上形成(例如，没有凸块)。更具体地，再分配线132的接触垫134直接形成在接触垫112上。
现在参考图5A，在实施方案中，RDL 130的背面133包括着陆垫，诸如凸块下冶金(UBM)垫136A、136B。RDL 130的特写图示示于图5B中，包括UBM垫136A、136B，以及直接在裸片110的接触垫112上形成的再分配线132的接触垫134。例如，对于随后的导电柱凸块，UBM垫136A可具有较大的宽度，诸如大约200μm，而对于随后的裸片附接，UBM垫136B可具有相对较小的宽度，诸如大约50μm。
参考图6，导电柱140在UBM垫136A的顶部上形成。导电柱140的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。导电柱140可使用合适的处理技术来形成，并且可由各种合适的材料(例如，铜)和层形成。在实施方案中，导电柱140通过镀覆技术来形成，诸如使用图案化光刻胶层电镀来限定柱结构尺寸，随后移除该图案化光刻胶层。
现在参考图7A-图7B，一个或多个第二(底部)裸片150可使用重构晶片/面板125作为承载而附接到RDL 130的背面133。在具体实施方案中，裸片150是存储器裸片。例如，裸片150可以是与裸片110相同或不同的存储器裸片，并且可各自具有相同或不同的尺寸、形状和/或存储器容量。在例示的实施方案中，一个或多个裸片150被安装在第一RDL 130上在多个导电柱140的周边内。例如，裸片150可使用表面安装技术诸如倒装芯片来安装。图7A-图7B示出导电柱140高于裸片150厚度。然而，裸片150可具有与导电柱140高度大致相同的厚度，或者裸片150可厚于导电柱140高度。
在例示的实施方案中，裸片150的顶表面151利用导电凸块162，诸如焊料凸块或柱形凸块附接到(例如，表面安装在)RDL 130的背面133。裸片150的顶表面151包括导电触点152和钝化层154，并且裸片150直接电耦接到RDL 130，例如电耦接到着陆垫诸如UBM垫136B。在该配置中，每个裸片150面向重构晶片/面板125。非导电糊剂(NCP)或非导电膜(NCF)可任选地横向围绕导电凸块162。在这样的实施方案中，接合可使用热压缩实现。导电凸块162可由材料诸如金或焊料材料形成，其可与着陆垫诸如UBM垫136B形成接合接头(例如金属间化合物或合金)。在实施方案中，裸片150利用直接在裸片150的导电凸块162和着陆垫诸如RDL 130的UBM垫136之间的各向异性导电膜(ACF)表面安装在RDL 130的背面133上。在实施方案中，裸片150的底表面153不包括任何导电触点152。
现在参考图8，电绝缘材料192可任选地施加在裸片150和RDL 130之间。例如，材料192可为用于倒装芯片接合的毛细管底部填充(CUF)材料，诸如快速固化底部填充物。示例性底部填充材料包括但不限于聚合物或环氧树脂。材料192还可为非导电糊剂。在其它实施方案中，不使用CUF工艺。
现在参考图9，根据实施方案，一个或多个第二(底部)裸片150和导电柱140被包封在第二模制化合物170中。第二模制化合物170可具有与第一模制化合物120相同的材料。在例示的实施方案中，模制化合物170的底表面171覆盖裸片150的底表面153以及导电柱140的底表面141。然而，此类配置并非是必需的。实际上，裸片150的底表面和/或导电柱140的底表面可在包封工艺期间或在包封之后暴露。在实施方案中，使用模制底部填充(MUF)工艺，其中第二模制化合物170用于填充裸片150和RDL 130之间的空间，而不是用CUF材料来填充。
参考图10，示出了其中导电柱140的底表面141暴露，并且未被第二模制化合物170覆盖的实施方案。这可能是包封工艺的结果。这另选地可能是蚀刻或后磨的结果，例如通过化学机械抛光(CMP)。导电柱140的厚度可任选地在蚀刻或后磨期间减小。在实施方案中，第二模制化合物170的底表面171与导电柱140的底表面141共面。
虽然裸片150的底表面153在图10中被示为由第二模制化合物170覆盖，但这不是必需的。例如，在图11所示的实施方案中，裸片150的底表面153暴露，并且未被第二模制化合物覆盖。这可能是包封工艺的结果。这另选地可能是蚀刻或后磨的结果，例如通过CMP的结果。导电柱140、第二模制化合物170和/或裸片150的厚度可任选地在蚀刻或后磨期间减小。在实施方案中，第二模制化合物170的底表面171与导电柱140的底表面141以及裸片150的底表面153共面。根据实施方案，控制在RDL的相对侧上的裸片和模制化合物的厚度的能力允许形成较薄的封装件。控制厚度可另外允许对封装件翘曲的额外控制。
实施方案不限于其中导电柱140由于包封工艺或后磨而暴露的结构。图12为模制和图案化过程的横截面侧视图图示。在例示的实施方案中，初始包封操作可导致模制化合物170在导电柱140上方，以及任选地在裸片150的底表面153上方展开。在包封之后，模制化合物170被图案化以形成开口172，以暴露导电柱140的底表面141。因此，不同于全局研磨或回蚀，可使用选择性的图案化技术诸如激光钻孔或化学蚀刻来暴露导电柱140。
尽管分别描述了图10-图12，但是过程不必彼此排他并且在一些实施方案中可被组合，或者可具有变型。
在第二模制化合物170的形成和处理之后，导电凸块190可附接到导电柱140的暴露底表面141或者在其上生长，并且如图13所示切割各个封装件100。各种结构可用于导电凸块190。例如，导电凸块190可为附接的焊料凸块，如图所示，或镀覆的柱。
向上直到该点，裸片110的顶表面111已被示出为由第一模制化合物120的顶表面121覆盖。在图14所示的实施方案中，至少一个裸片110的顶表面111暴露，并且未被第一模制化合物120覆盖。例如，这可归因于初始包封工艺，或者另选地通过蚀刻或后磨操作来完成，这可在利用第一模制化合物120的初始包封工艺之后或者在利用第二模制化合物170的包封之后执行。在实施方案中，第一模制化合物120的顶表面121与裸片110的顶表面111共面。根据实施方案，控制在RDL的相对侧上的裸片和模制化合物的厚度的能力允许形成较薄的封装件。由于该封装件具有封装材料，并且控制厚度的RDL 130的两侧上的硅含量可另外允许对封装件翘曲的额外控制。除了控制厚度之外，封装材料也可用于通过使用在RDL 130的两侧上具有不同性质和/或厚度的材料来控制封装件翘曲。因此，可以实现非常低的高温翘曲(约20μm或更小)封装件。在实施方案中，封装件100具有大约300μm或更小的总厚度(或z高度)，不包括导电凸块190的高度。例如，在图14中顶表面111、121和底表面141、153、171之间的距离可为大约300μm或更小。
图15为示出根据实施方案形成扇出封装件100，诸如双面安装扇出存储器封装件的方法的流程图。在操作1010处，利用第一模制化合物120将第一裸片110包封在承载衬底102上。然后在操作1020处移除承载衬底120，并且在操作1030处，在第一模制化合物120和第一裸片110上形成RDL 130。例如，RDL 130可形成为使得RDL的再分配线132沿着第一裸片110的底表面113直接在接触垫112上形成。在操作1040处，在RDL的背面133上形成多个导电柱140，并且在操作1050处，在多个导电柱140的周边内部的RDL 130的背面133上安装第二裸片150。然后第二裸片150和多个导电柱140在操作1060处用第二模制化合物170包封。在利用实施方案的各个方面中，对本领域技术人员显而易见的是，上述实施方案的组合或变型可以用于形成扇出封装件，包括但不限于以上所示和所述的变型中的任一种。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述，但应当理解，所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。

Claims (20)

1.一种封装件，包括：
再分配层(RDL)；
第一裸片，所述第一裸片粘结到所述RDL的正面，其中所述RDL的第一再分配线在所述第一裸片的第一接触垫上形成；
第一模制化合物，所述第一模制化合物将所述第一裸片包封在所述RDL的所述正面上；
第二裸片，所述第二裸片安装在所述RDL的背面上；
多个导电柱，所述多个导电柱从所述RDL的所述背面延伸；和
第二模制化合物，所述第二模制化合物将所述第二裸片和所述多个导电柱包封在所述RDL的所述背面上。
2.根据权利要求1所述的封装件，还包括在所述多个导电柱上的多个导电凸块。
3.根据权利要求1所述的封装件，其中所述第一模制化合物未完全覆盖所述第一裸片的顶表面。
4.根据权利要求1所述的封装件，其中所述第二模制化合物未完全覆盖所述第二裸片的底表面。
5.根据权利要求4所述的封装件，其中所述第一模制化合物未完全覆盖所述第一裸片的顶表面，并且所述第二模制化合物未完全覆盖所述第二裸片的底表面。
6.根据权利要求1所述的封装件，其中所述第一裸片的顶表面和所述第一模制化合物的顶表面是共面的。
7.根据权利要求1所述的封装件，其中所述第二裸片的底表面、所述多个导电柱的底表面，以及所述第二模制化合物的底表面是共面的。
8.根据权利要求1所述的封装件，其中：
所述第一裸片的顶表面和所述第一模制化合物的顶表面是共面的；并且
所述第二裸片的底表面、所述多个导电柱的底表面，以及所述第二模制化合物的底表面是共面的。
9.根据权利要求8所述的封装件，其中所述第一裸片和所述第二裸片是存储器裸片。
10.根据权利要求1所述的封装件，其中所述第二裸片利用导电凸块粘结到所述RDL。
11.根据权利要求1所述的封装件，还包括粘结到所述RDL的所述正面的多个第一裸片，以及安装在所述RDL的所述背面上的多个第二裸片。
12.根据权利要求11所述的封装件，其中：
所述多个第一裸片的顶表面和所述第一模制化合物的顶表面是共面的；并且
所述多个第二裸片的底表面、所述多个导电柱的底表面，以及所述第二模制化合物的底表面是共面的。
13.根据权利要求12所述的封装件，其中所述多个第一裸片和所述多个第二裸片是存储器裸片。
14.一种形成扇出封装件的方法：
利用第一模制化合物将第一裸片包封在承载衬底上；
移除所述承载衬底；
在所述第一模制化合物和所述第一裸片上形成再分配层(RDL)，其中所述RDL的再分配线沿着所述第一裸片的底表面直接形成在接触垫上；
在所述RDL的背面上形成多个导电柱；
将第二裸片安装在所述RDL的所述背面上在所述多个导电柱的周边内部；以及
利用第二模制化合物来包封所述第二裸片和所述多个导电柱。
15.根据权利要求14所述的方法，还包括在所述多个导电柱上形成多个导电凸块。
16.根据权利要求14所述的方法，还包括减小所述第一模制化合物的厚度，以暴露所述第一裸片。
17.根据权利要求14所述的方法，还包括减小所述第一模制化合物和所述第一裸片的厚度，从而产生平面顶部封装件表面。
18.根据权利要求14所述的方法，还包括减小所述第二模制化合物的厚度，以暴露所述第二裸片。
19.根据权利要求14所述的方法，还包括减小所述第二模制、所述第二裸片和所述多个导电柱的厚度，从而产生平面底部封装件表面。
20.根据权利要求14所述的方法，还包括：
减小所述第一模制化合物和所述第一裸片的厚度，从而产生平面顶部封装件表面；以及
减小所述第二模制、所述第二裸片和所述多个导电柱的厚度，
从而产生平面底部封装件表面。
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