CN106876290A - 晶圆级扇出型封装件及其制造方法 - Google Patents

晶圆级扇出型封装件及其制造方法 Download PDF

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CN106876290A
CN106876290A CN201710144202.7A CN201710144202A CN106876290A CN 106876290 A CN106876290 A CN 106876290A CN 201710144202 A CN201710144202 A CN 201710144202A CN 106876290 A CN106876290 A CN 106876290A
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chip
passive device
wafer scale
package part
out package
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张鹏
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Priority to CN201710144202.7A priority Critical patent/CN106876290A/zh
Publication of CN106876290A publication Critical patent/CN106876290A/zh
Priority to US15/677,049 priority patent/US10461044B2/en
Priority to KR1020170106246A priority patent/KR102422242B1/ko
Priority to US16/574,981 priority patent/US10580742B2/en
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Abstract

提供了一种晶圆级扇出型封装件及其制造方法。制造晶圆级扇出型封装件的方法包括：准备具有凸起的基体基底；将芯片设置在基体基底的凸起所处的表面上，并且使芯片与凸起分开布置；在基体基底上形成包封层，以包封芯片和凸起；去除基体基底，以暴露芯片的表面并且在包封层中形成与凸起对应的凹进；以及将被动元件设置在凹进中。在制造晶圆级扇出型封装件的方法中，通过在形成包封层之后形成被动元件，使得能够避免在形成包封层时由于包封层的材料的热膨胀而引起的被动元件的相对位置发生偏移的问题。

Description

晶圆级扇出型封装件及其制造方法
技术领域
本发明的示例性实施例涉及半导体封装领域，具体地讲，涉及一种集成有被动元件的晶圆级扇出型封装件和制造该晶圆级扇出型封装件的方法。
背景技术
目前，在集成有被动元件的晶圆级扇出型封装件中，由于晶圆级扇出型封装件内的各元件的热膨胀系数(Coefficient of Thermal Expansion，CTE)不同，因此会导致被动元件在晶圆级扇出型封装件中很容易发生位置偏移，继而影响后续形成在被动元件上的电路层与被动元件之间发生电连接不良的缺陷。例如，当利用诸如环氧树脂的包封材料对半导体芯片和被动元件进行包封时，会因包封材料的热膨胀和收缩而导致被动元件发生位置偏移。
图1A至图1D是示出了根据现有技术的制造晶圆级扇出型封装件的方法的剖视图。
参照图1A，在基体基底110上形成芯片120和与芯片120分开设置的被动元件130，并且在基体基底110上形成包封层140以包封芯片120和被动元件130。
然后，参照图1B，从芯片120和被动元件130去除基体基底110，以暴芯片120和被动元件130的表面。
接下来，参照图1C，在芯片120和被动元件130的暴露的表面上形成电路层150。
最后，参照图1D，在电路层150上形成焊球160。
在形成包封层140以包封芯片120和被动元件130时，由于包封层140的材料的热膨胀和收缩而导致被动元件130发生位置偏移，从而导致形成在被动元件上的电路层150与被动元件130之间发生电连接不良的缺陷。
因此，需要一种新的集成有被动元件的晶圆级扇出型封装件。
发明内容
为了解决现有技术中存在的上述问题，本发明的示例性实施例的目的在于提供一种晶圆级扇出型封装件及其制造方法。
根据本发明的实施例，提供了一种制造晶圆级扇出型封装件的方法，所述方法包括：准备具有凸起的基体基底；将芯片设置在基体基底的凸起所处的表面上，并且使芯片与凸起分开布置；在基体基底上形成包封层，以包封芯片和凸起；去除基体基底，以暴露芯片的表面并且在包封层中形成与凸起对应的凹进；以及将被动元件设置在凹进中。
所述方法还可以包括：在将被动元件设置在凹进中之前，在芯片的暴露的表面以及凹进上形成电路层。
所述方法还可以包括：在将被动元件设置在凹进中之后，在电路层上设置焊球。
被动元件可以通过回流焊设置在凹进中。
凸起的上表面与基体基底的所述表面之间的距离可以为50μm-100μm。
包封层可以包括环氧树脂。
根据本发明的另一实施例，提供了一种晶圆级扇出型封装件，所述晶圆级扇出型封装件包括：芯片，具有上表面、与上表面相对的下表面以及端部；包封层，覆盖芯片的上表面和端部并暴露芯片的下表面，其中包封层在包封层的与芯片的下表面位于同一侧的表面上具有开口；电路层，形成在芯片的下表面和开口上；以及被动元件，形成在开口中并与电路层接触。
所述晶圆级扇出型封装件还可以包括设置在电路层上的焊球。
被动元件可以通过回流焊与电路层连接。
开口可以在包封层的厚度方向上具有50μm-100μm的厚度。
如上所述，在晶圆级扇出型封装件及其制造方法中，通过在形成包封层之后形成被动元件，使得能够避免在形成包封层时由于包封层的材料的热膨胀而引起的被动元件的相对位置发生偏移的问题，从而能够改善被动元件与电路层之间的电路短路问题。另外，在晶圆级扇出型封装件及其制造方法中，由于在形成电路层之后形成被动元件，从而极大地提高了制造精度；而且在形成被动元件期间可以对被动元件进行重制，从而提高良率。
附图说明
通过以下结合附图对实施例的描述，这些和/或其它方面将变得清楚且更容易理解，在附图中：
图1A至图1D是示出了根据现有技术的制造晶圆级扇出型封装件的方法的剖视图；
图2是示出了根据本发明的示例性实施例的晶圆级扇出型封装件的示意图；以及
图3至图8是示出了根据本发明的示例性实施例的制造晶圆级扇出型封装件的方法的剖视图。
具体实施方式
现在将参照附图更充分地描述本发明的实施例，在附图中示出了本发明的示例性实施例。然而，本发明可以以许多不同的形式实施，而不应被解释为局限于在此阐述的实施例；相反，提供这些实施例使得本公开将是彻底的和完整的，并且这些实施例将向本领域的普通技术人员充分地传达本发明的实施例的构思。在下面详细的描述中，通过示例的方式阐述了多处具体的细节，以提供对相关教导的充分理解。然而，本领域技术人员应该清楚的是，可以实践本教导而无需这样的细节。在其它情况下，以相对高的层次而没有细节地描述了公知的方法、步骤、组件和电路，以避免使本教导的多个方面不必要地变得模糊。附图中的同样的标号表示同样的元件，因此将不重复对它们的描述。在附图中，为了清晰起见，可能会夸大层和区域的尺寸和相对尺寸。
现在将在下文中参照附图更充分地描述本发明。
图2是示出了根据本发明的示例性实施例的晶圆级扇出型封装件的示意图。
参照图2，根据本发明的实施例的晶圆级扇出型封装件200包括：芯片220，具有上表面(未示出)、与上表面相对的下表面(未示出)以及端部(未示出)；包封层240，覆盖芯片220的上表面以及端部并暴露芯片220的下表面，其中包封层240在包封层240的与芯片220的下表面位于同一侧的表面上具有开口(或凹进)241；电路层250，形成在芯片220的下表面和开口241上；以及被动元件230，形成在开口241中并与电路层250接触。
芯片220可以具有上表面、与上表面相对的下表面以及端部。在本发明的示例性实施例中，芯片220可以是本领域中通常所熟知的芯片。
包封层240覆盖芯片220的上表面和端部并暴露芯片220的下表面。在本发明的示例性实施例中，包封层240在包封层240的与芯片220的下表面位于同一侧的表面(例如，包封层240的下表面)上具有开口241。芯片220与开口241分开布置。在本发明的示例性实施例中，包封层240可以包括环氧树脂，然而包封层不限于此。在本发明的示例性实施例中，开口241在包封层240的厚度方向(例如，竖直方向或与芯片的上表面垂直的方向)上可以具有50μm-100μm的厚度，然而，本发明不限于此，开口241可以具有能够容纳被动元件的任何适合的厚度。
电路层250形成在芯片220的下表面和开口241上。在本发明的非限制性实施例中，可以使用本领域技术人员所熟知的任何适合的方法来在芯片220的下表面和开口241上形成电路层250。
被动元件230形成在开口241中并与电路层250接触(例如，电接触)。在本发明的示例性实施例中，可以通过回流焊将被动元件230形成在电路层250上，然而本发明不限于此。
在本发明的示例性实施例中，通过在形成包封层之后形成被动元件，使得能够避免在形成包封层时由于包封层的材料的热膨胀而引起的被动元件的相对位置发生偏移的问题，从而能够改善被动元件与电路层之间的电路短路问题。
下面将参照图3至图8详细描述根据本发明的示例性实施例的制造晶圆级扇出型封装件的方法。
图3至图8是示出了根据本发明的示例性实施例的制造晶圆级扇出型封装件的方法的剖视图。
参照图3，首先，准备具有凸起211的基体基底210，然后在基体基底210的其上具有凸起211的表面上设置芯片220，并使芯片220与凸起211分开布置。在本发明的示例性实施例中，凸起的上表面与基体基底的所述表面之间的距离可以为50μm-100μm。在本发明的非限制性实施例中，基体基底210与凸起211可以一体地形成，然而本发明不限于此。
然后，参照图4，在基体基底210上形成包封层240以包封芯片220和凸起211。在本发明的示例性实施例中，包封层240可以包括环氧树脂，然而，本发明的实施例不限于此。在本发明的非限制性实施例中，可以使用任何适合的方法来形成包封层240。
接下来，参照图5，从包封层240去除基体基底210，以暴露芯片220的表面并且在包封层240中形成与凸起211对应的凹进(或开口)241。由于从包封层240去除了具有凸起211的基体基底210，所以在暴露芯片220的表面的同时形成了凹进241。
然后，参照图6，在芯片220的暴露的表面以及凹进241上形成电路层250。在本发明的非限制性实施例中，可以使用任何适合的方法来形成电路层250。
接着，参照图7，将被动元件230设置在凹进241中。在本发明的示例性实施例中，可以将被动元件230设置在凹进241中并使被动元件230与电路层250接触。在本发明的示例性实施例中，被动元件230可以通过回流焊与电路层250接触。
最后，参照图8，在电路层250上设置焊球260。在本发明的非限制性实施例中，可以使用任何适合的方法来形成焊球260。
在参照图3至图8描述的制造根据本发明的制造晶圆级扇出型封装件的方法中，本领域技术人员可以选用常用方法或手段来完成其它步骤。
根据本发明的示例性实施例，在制造晶圆级扇出型封装件的方法中，通过在形成包封层之后形成被动元件，使得能够避免在形成包封层时由于包封层的材料的热膨胀而引起的被动元件的相对位置发生偏移的问题，从而能够改善被动元件与电路层之间的电路短路问题。
另外，在制造晶圆级扇出型封装件的方法中，由于在形成电路层之后形成被动元件，从而极大地提高了制造精度；而且在形成被动元件期间可以对被动元件进行重制，从而提高良率。
虽然已经参照本发明的示例性实施例具体地示出并描述了本发明，但是本领域普通技术人员将理解，在不脱离如所附权利要求和它们的等同物所限定的本发明的精神和范围的情况下，可以在此做出形式和细节上的各种改变。应当仅仅在描述性的意义上而不是出于限制的目的来考虑实施例。因此，本发明的范围不是由本发明的具体实施方式来限定，而是由权利要求书来限定，该范围内的所有差异将被解释为包括在本发明中。

Claims (10)

1.一种制造晶圆级扇出型封装件的方法，其特征在于，所述方法包括：
准备具有凸起的基体基底；
将芯片设置在基体基底的凸起所处的表面上，并且使芯片与凸起分开布置；
在基体基底上形成包封层，以包封芯片和凸起；
去除基体基底，以暴露芯片的表面并且在包封层中形成与凸起对应的凹进；以及
将被动元件设置在凹进中。
2.根据权利要求1所述的方法，其特征在于，所述方法还包括：在将被动元件设置在凹进中之前，在芯片的暴露的表面以及凹进上形成电路层。
3.根据权利要求2所述的方法，其特征在于，所述方法还包括：在将被动元件设置在凹进中之后，在电路层上设置焊球。
4.根据权利要求1所述的方法，其特征在于，被动元件通过回流焊设置在凹进中。
5.根据权利要求1所述的方法，其特征在于，凸起的上表面与基体基底的所述表面之间的距离为50μm-100μm。
6.根据权利要求1所述的方法，其特征在于，包封层包括环氧树脂。
7.一种晶圆级扇出型封装件，其特征在于，所述晶圆级扇出型封装件包括：
芯片，具有上表面、与上表面相对的下表面以及端部；
包封层，覆盖芯片的上表面和端部并暴露芯片的下表面，其中包封层在包封层的与芯片的下表面位于同一侧的表面上具有开口；
电路层，形成在芯片的下表面和开口上；以及
被动元件，形成在开口中并与电路层接触。
8.根据权利要求7所述的晶圆级扇出型封装件，其特征在于，所述晶圆级扇出型封装件还包括设置在电路层上的焊球。
9.根据权利要求7所述的晶圆级扇出型封装件，其特征在于，被动元件通过回流焊与电路层连接。
10.根据权利要求7所述的晶圆级扇出型封装件，其特征在于，开口在包封层的厚度方向上具有50μm-100μm的厚度。
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