CN105981159A - 具有设置在封装体内的无源微电子器件的微电子封装件 - Google Patents

具有设置在封装体内的无源微电子器件的微电子封装件 Download PDF

Info

Publication number
CN105981159A
CN105981159A CN201480075442.0A CN201480075442A CN105981159A CN 105981159 A CN105981159 A CN 105981159A CN 201480075442 A CN201480075442 A CN 201480075442A CN 105981159 A CN105981159 A CN 105981159A
Authority
CN
China
Prior art keywords
packaging body
microelectronic
active
microelectronic component
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480075442.0A
Other languages
English (en)
Other versions
CN105981159B (zh
Inventor
T·迈尔
G·奥夫纳
A·沃尔特
G·塞德曼
S·阿尔贝斯
C·盖斯勒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN105981159A publication Critical patent/CN105981159A/zh
Application granted granted Critical
Publication of CN105981159B publication Critical patent/CN105981159B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)

Abstract

一种微电子封装件，包括设置在封装体内的无源微电子器件，其中，封装体是微电子封装件的部分，封装体为微电子封装件提供支撑和/或刚性。在倒装芯片类型的微电子封装件中，封装体可以包括微电子基板，有源微电子器件电附接至微电子基板。在嵌入式器件类型的微电子封装件中，封装体可以包括其中嵌入有源微电子器件的材料。

Description

具有设置在封装体内的无源微电子器件的微电子封装件
技术领域
本说明书的实施例总体上涉及微电子封装件制造的领域，并且具体而言，涉及包括表面安装器件和/或设置在封装体内的集成无源器件的微电子封装件。
背景技术
微电子产业继续努力生产用在各种电子产品(包括但不限于计算机服务器产品和诸如便携式计算机、电子平板设备、蜂窝电话、数字相机等等之类的便携式产品)中的越来越快和越来越小的微电子封装件。随着实现这些目标，微电子封装件的制造变得更加具有挑战性。一个这种挑战性领域与减小微电子封装件的高度/厚度有关。尽管有源微电子器件(诸如微电子管芯)的厚度已经减小，但是用在微电子封装件中的无源微电子器件(诸如集成无源器件和表面安装器件)难以在尺寸上减小。这种困难起因于通常这些无源微电子器件需要特定量(例如，体积)的部件材料以便实现期望的功能(例如，电容值、电感值等)的事实。由此，制造更薄的无源微电子器件将需要减小部件材料的体积(其将阻碍性能)或使用非常规的部件材料(其可以减小将需要的部件材料的体积，但可能过高地增加无源微电子器件的成本)。
附图说明
在说明书的结束部分中特别地指出并且明确地要求保护本公开内容的主题。根据下面的描述和所附权利要求并且结合附图考虑，本公开内容的前述特征和其它特征将变得更加充分地显而易见。应当理解的是，附图仅仅描绘了根据本公开内容的几个实施例，并且因此不被认为限制其范围。本公开内容将通过使用附图被描述为具有附加的特征和细节，以使得本公开内容的优点可以更容易确定，在附图中：
图1A-1F示出了根据本说明书的实施例的制造倒装芯片类型的微电子封装件的工艺的横截面视图。
图2A-2F示出了根据本说明书的另一个实施例的制造嵌入式技术类型的微电子封装件的工艺的横截面视图。
图3A-3F示出了根据本说明书的又一个实施例的制造嵌入式技术类型的微电子封装件的工艺的横截面视图。
图4是根据本说明书的实施例的制造微电子结构的工艺的流程图。
图5示出了根据本说明书的一个实施方式的计算设备。
具体实施方式
在下面的具体实施方式中，对附图进行了参考，附图通过例示的方式示出了其中可以实施所要求保护的主题的具体实施例。足够详细地描述了这些实施例，以使得本领域技术人员能够实施主题。应当理解的是，各个实施例(尽管不同)不必相互排斥。例如，在不脱离所要求保护的主题的精神和范围的情况下，本文结合一个实施例所描述的特定特征、结构或特性可以在其它实施例内实施。此说明书内对“一个实施例”或“实施例”的提及意指结合实施例所描述的特定特征、结构或特性包括在包含在本书明书内的至少一个实施方式中。因此，使用短语“一个实施例”或“在实施例中”不必指代相同实施例。另外，应当理解的是，每一个所公开的实施例内单独元件的位置或布置可以在不脱离所要求保护的主题的精神和范围的情况下得以修改。下面的具体实施方式因此不认为是限制意义，并且主题的范围仅仅由适当解释的所附权利要求连同所附权利要求所赋予的等同形式的全部范围来限定。在附图中，类似的附图标记指代遍及几个视图的相同或类似的元件或功能，并且其中所描绘的这些元件不必彼此按比例缩放，而是单独的元件可以放大或缩小以便在本说明书的背景下更容易地理解元件。
如本文中所使用的术语“在……上方”、“至”、“在……之间”和“在……上”可以指代一层相对于其它层的相对位置。一层“在”另一层“上方”或“在”另一层“上”或键合“至”另一层可以直接与另一层接触或可以具有一个或多个中间层。层“之间”的一层可以直接与这些层接触或可以具有一个或多个中间层。
本说明书的实施例包括具有设置在封装体内的无源微电子器件的微电子封装件，其中，封装体是微电子封装件的一部分，其为微电子封装件提供支撑和/或刚性。在倒装芯片类型的微电子封装件中，封装体可以包括微电子基板，有源微电子器件电附接至该微电子基板。在嵌入式器件类型的微电子封装件中，封装体可以包括其中嵌入了有源微电子器件的材料。
图1A-1F示出了本说明书的实施例，其中无源器件设置在倒装芯片类型的微电子封装件的封装体内。如在图1A中示出的，可以形成封装体110。封装体110可以是具有第一表面112和相对的第二表面114的微电子基板，诸如母板、内插器(interposer)等。封装体110可以具有形成在封装体的第一表面112中或第一表面112上的多个焊盘116、以及形成在封装体的第二表面114中或第二表面112上的多个焊盘118。封装体110可以包括具有由形成在电介质层中的至少一个电介质层上(示出为形成在第二电介质层1222上)的导电迹线124构成的多个导电路径130的多个电介质层(示出为第一电介质层1221和第二电介质层1222)，其中，连接形成在诸如导电迹线124、封装体的第一表面焊盘116、以及封装体的第二表面焊盘118之类的结构之间，其中导电过孔126形成为穿过各个电介质层(示出为第一电介质层1221和第二电介质层1222)。应当理解的是，导电路径130可以包括封装体的第一表面焊盘116和封装体的第二表面焊盘118。
封装体电介质层(示出为第一电介质层1221和第二电介质层1222)可以包括任何适当的电介质材料，包括但不限于液晶聚合物、环氧树脂、双马来酰亚胺三嗪树脂、聚苯并恶唑、聚酰亚胺材料、二氧化硅填充的环氧树脂(诸如可从日本的Ajinomoto Fine-Techno Co.,Inc.,1-2Suzuki-cho,Kawasaki-ku,Kawasaki-shi,210-0801获得的材料，(例如，Ajinomoto ABFGX13和Ajinomoto GX92))等等。导电路径130可以由任何适当的导电材料构成，包括但不限于铜、银、金、镍、钛、钨及其合金。用于形成封装体110的工艺对于本领域技术人员是公知的，并且为了简洁和简明将不在本文中进行描述或示出。应当理解的是，封装体110可以由任何数量的电介质层构成，可以包含刚性芯(未示出)，并可以包含形成在其中的有源和/或无源微电子器件(未示出)。还应当理解的是，导电路径130可以在封装体110内形成任何期望的电路线和/或利用附加的外部部件(未示出)来形成任何期望的电路线。还应当理解的是，如本领域技术人员将理解的，可以在封装体的第一表面122和/或封装体的第二表面124上利用阻焊层(未示出)。
如在图1B中示出的，可以在封装体110中形成腔132。如所示出的，封装体的腔132可以形成为穿过封装体110，从封装体的第一表面112延伸至封装体的第二表面114并且在它们之间形成腔侧壁134。封装体的腔132可以通过本领域中公知的任何技术来形成，包括但不限于冲压、碾磨、钻孔、夹持(pinching)、蚀刻等。
如在图1C中示出的，在通常被称为倒装芯片或可控塌陷芯片连接(“C4”)的配置中，有源微电子器件140可以利用多个互连件150(诸如可回流的焊接凸点或焊球)附接至对应的封装体的第一表面焊盘116。互连件150可以在封装体的第一表面焊盘116与有源微电子器件140的有源表面144上的镜像焊盘142之间延伸以便在它们之间形成电连接。应当理解的是，有源微电子器件的焊盘142可以与有源微电子器件140内的集成电路(未示出)进行电通信。有源微电子器件140可以是任何适当的微电子器件，包括但不限于微处理器、芯片组、图形器件、无线器件、存储器件、专用集成电路器件等等。还应当理解的是，底部填充材料(未示出)可以设置在有源微电子器件与封装体110之间，并且如本领域技术人员将理解的，可以在封装体的第一表面112和/或封装体的第二表面114上利用阻焊层(未示出)。
如在图1D中示出的，封装体110可以被放置在具有至少一个封装体突出部162和至少一个无源微电子器件突出部164的载体160上，其中，无源微电子器件170可以被放置在封装体的腔132中(见图1C)以接触载体的无源微电子器件突出部164。载体的封装体突出部162和载体的无源微电子器件突出部164可以分别具有不同的高度H1和H2以便将无源微电子器件170放置在封装体的腔132内的适当位置中(见图1C)。如图1D中进一步示出的，可以在腔侧壁134与无源微电子器件170之间施加粘合材料166以将无源微电子器件170固定在适当位置。为了该具体实施方式的目的，无源微电子器件170被限定为表面安装器件或集成无源器件，如本领域技术人员将理解的，其包括在功能性无源部件176的相对侧上的至少两个电端子172、174。无源微电子器件170可以包括任何适当的器件，包括但不限于电阻器、电容器、电感器、阻抗匹配电路、谐波滤波器、耦合器、平衡-不平衡转换器(balun)等等。
如在图1E中示出的，可以移除载体160(见图1D)，并且可以在适当的封装体的第二表面焊盘118上形成外部互连件180(示出为可回流焊球)，并且可以在每个无源微电子器件的电端子172、174与其对应的封装体的第二表面焊盘118之间制造导电材料连接件182。诸如通过焊膏印刷技术(其后对焊膏进行回流)可以同时形成外部互连件180和导电材料连接件182。然而，导电材料连接件182可以诸如通过焊膏分配技术、喷墨技术等(其后对焊膏进行回流)来在单独步骤中制造。如在图1E中进一步示出的，可以诸如通过塑模技术在封装体的第一表面112和有源微电子器件140上方形成密封材料188以形成微电子封装件100。
在另一个实施例中，如在图1F中示出的，封装体的腔132可以从封装体的第一表面112部分地延伸至封装体110中，其形成腔底部表面136并暴露多个导电迹线124。无源微电子器件170可以被放置在封装体的腔132中，其中可以在每个无源微电子器件的电端子172、174与其对应的导电迹线124之间制造导电材料连接件182。根据以上关于图1A-1E的描述和公知的技术，在图1F中示出的用于微电子封装件100的处理步骤将是显而易见的。
图2A-2F示出了其中有源微电子器件140和无源微电子器件170被设置在封装体110内的本说明书的实施例。如在图2A中示出的，有源微电子器件140可以嵌入在封装体110中，以使得有源微电子器件的有源表面144与封装体的第二表面114基本上成平面。图2A中示出的结构可以用各种技术来实现，包括但不限于层压和塑模(其可以是公知为嵌入式管芯封装处理和扇出型晶圆级封装处理的部分)。封装体110可以由任何适当的密封材料(包括但不限于聚合物材料)构成。
如在图2B中示出的，可以在有源微电子器件的有源表面144和封装体的第二表面114上形成再分布层200。再分布层200可以包括多个电介质层(示出为第一电介质层202和第二电介质204)和多个导电路径206。第一电介质层202可以形成在有源微电子器件的有源表面144和封装体的第二表面114上。多个导电路径206可以形成在第一电介质层202上，其中，多个导电路径206中的至少一部分延伸穿过第一电介质层202以接触对应的有源微电子器件的焊盘142。第二电介质层204(诸如阻焊层)可以形成在第一电介质层202和多个导电路径206上。外部互连件180(示出为可回流焊球)可以形成在开口内并穿过第二电介质层204以接触对应的导电路径206。应当理解的是，当封装体110足够介电时，第一电介质层202是可选的，其中。
如在图2C中示出的，封装体的腔132可以形成为穿过封装体110，从封装体的第一表面112延伸至封装体的第二表面114，并可以部分地延伸到再分布层200中并暴露适当的导电路径206。封装体的腔132可以由任何本领域中公知的技术来形成，这些技术包括但不限于冲压、碾磨、钻孔、夹持、蚀刻等、或者它们的组合。
如在图2D中示出的，无源微电子器件170可以被放置在封装体的腔132(见图2C)中，其中导电材料连接件182位于每个无源微电子器件的电端子172、174与其对应的导电路径206之间。
在另一个实施例中，如在图2E中示出的，封装体的腔132还可以延伸穿过再分布层200，并且无源微电子器件170可以被放置为延伸穿过封装体的腔132和再分布层200，其中导电材料连接件182位于每个无源微电子器件的电端子172、174与其对应的导电路径206之间。粘合材料166可以被施加在腔侧壁134与无源微电子器件170之间以将无源微电子器件170固定在适当位置。
在又一个实施例中，如在图2F中示出的，封装体的腔132可以被形成为穿过再分布层200并且从封装体的第二表面114部分地延伸到封装体110中。粘合材料166可以施加在腔侧壁134与无源微电子器件170之间以将无源微电子器件170固定在适当位置，并且可以在每个无源微电子器件的电端子172、174与其对应的导电路径206之间形成导电材料连接件182。
图3A-3F示出了其中有源微电子器件140被设置在封装体110(其包括电介质密封剂330和支撑板310)内的本说明书的实施例。如在图3A中示出的，支撑板310可以被形成为具有第一表面312和相对的第二表面314，其中，支撑板310可以可选地包括形成在支撑板的第二表面314上的电介质材料层316。可以利用附接粘合剂322将有源微电子器件140的背面146附接至支撑板310(示出为具有接触支撑板的电介质材料层316的附接粘合剂322)。如在图3A中进一步示出的，电介质密封剂330可以被形成为邻近支撑板310并嵌入包括有源微电子器件的有源表面144的有源微电子器件140，其中，电介质密封剂的第一表面332可以被限定为邻近支撑板310，并且电介质密封剂的第二表面334可以被限定为与密封剂的第一表面332相对。如在图3A中进一步示出的，开口336可以被形成为从电介质密封剂的第二表面334延伸至对应的有源微电子器件的焊盘142。开口336可以通过任何现有技术中公知的技术来形成，这些技术包括但不限于激光钻孔、光刻、和离子轰击。
支撑板310可以包括任何适当的刚性材料，包括但不限于金属、聚合物、陶瓷等等、以及它们的组合和具有不同材料类别的组合。电介质密封剂330可以由任何适当的电介质材料(包括但不限于聚合物材料)制成，并且可以由任何公知的技术(包括但不限于旋涂、层压、印刷、塑模等)来形成。
如在图3B中示出的，再分布层340可以形成在电介质密封剂的第二表面334上。再分布层340可以包括形成在电介质密封剂的第二表面334上的多个导电路径342，其中，多个导电路径342中的至少一部分延伸到电介质密封剂的开口336(见图3A)中。再分布层340还可以包括电介质层344，诸如阻焊层，其可以形成在电介质密封剂的第二表面334和多个导电路径342上。
如在图3C中示出的，封装体的腔132可以被形成为穿过再分布层340、穿过电介质密封剂330，并部分地延伸到支撑板310中。如在图3D中示出的，可以施加粘合材料166以将无源微电子器件170固定在适当位置。外部互连件180(示出为可回流焊球)可以形成在开口内并穿过电介质层344以接触对应的导线路线342，并且可以在每个无源微电子器件的电端子172、174与其对应的导电路径342之间制造导线材料连接件182。诸如通过焊膏印刷技术(其后对焊膏进行回流)可以同时形成外部互连件180和导电材料连接件182。然而，导电材料连接件182可以诸如通过焊膏印刷或分配技术、喷墨技术等(其后对焊膏进行回流)而在单独的步骤中制造。
应当理解的是，如在图3E中示出的，可以在支撑板310中预先形成凹槽346，以使得电介质密封剂330在被沉积时在其中延伸。因此，如在图3F中示出的，在封装体的腔132的形成中仅需要去除一种材料(即，电介质密封剂330)。
还应当理解的是，密封体的腔132可以整个延伸穿过支撑板310和电介质密封剂330，诸如关于本具体实施方式的其它实施例来展示的。
应当理解的是，与将无源微电子器件170完全嵌入封装体110中相比，本说明书的实施例可以具有优点，这是因为无源微电子器件170可以延伸超过封装体的第一表面112和/或封装体的第二表面114，由此允许形成相对于具有完全嵌入的无源微电子器件的封装体的厚度而言较薄的封装体。
图4是根据本说明书的实施例的制造微电子结构的工艺200的流程图。如在框202中阐述的，可以形成有源微电子器件基板。如在框204中阐述的，可以形成封装体。如在框206中阐述的，封装体可以与有源微电子器件相接触。如在框208中阐述的，导电路径可以形成在封装体中或封装体上。如在框210中阐述的，腔可以形成在封装体中。如在框212中阐述的，无源微电子器件可以设置在腔内。如在框214中阐述的，可以利用导电路径电连接有源微电子器件和无源微电子器件。
图5示出了根据本说明书的一种实施方式的计算设备300。计算设备300容纳板302。板302可以包括若干部件，包括但不限于处理器304和至少一个通信芯片306A和306B。处理器304可以物理地和/或电地耦合至板302。在某些实施方式中，至少一个通信芯片306A、306B还物理地和电气地耦合至板302。在另外的实施方式中，通信芯片306A、306B是处理器304的部分。
取决于其应用，计算设备300可以包括其它部件，这些部件可以物理地和电气地耦合至板302，也可以不存在这样的耦合。这些其它部件包括但不限于易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪存、图形处理器、数字信号处理器、密码协处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编码解码器、视频编码解码器、功率放大器、全球定位系统(GPS)设备、指南针、加速度计、陀螺仪、扬声器、相机、和大容量储存设备(诸如，硬盘驱动器、压缩盘(CD)、数字通用盘(DVD)等等)。
通信芯片306A、306B实现了无线通信，以便将数据传送到计算设备300以及从计算设备300传送数据。术语“无线”及其派生词可以用于描述可以通过使用穿过非固态介质的经调制的电磁辐射来传输数据的电路、设备、系统、方法、技术、通信信道等。该术语并非暗示相关联的设备不包含任何导线，尽管在某些实施例中它们可能不含有。通信芯片306可以实施若干无线标准或协议的任一种无线标准或协议，这些标准或协议包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、它们的衍生物、以及被命名为3G、4G、5G及之后的任何其它无线协议。计算设备300可以包括多个通信芯片306A、306B。例如，第一通信芯片306A可以专用于较短距离的无线通信(诸如Wi-Fi和蓝牙)，而第二通信芯片306B可以专用于较长距离的无线通信(诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等)。
计算设备300的处理器304可以包括具有封装在其中的多个微电子器件(有源和无源两者)的微电子封装件。在本说明书的某些实施方式中，处理器304的无源微电子器件可以被设置在封装体内，如以上所描述的。术语“处理器”可以指代对来自寄存器和/或存储器的电子数据进行处理以将该电子数据转换成可以被存储在寄存器和/或存储器中的其它电子数据的任何器件或器件中的一部分。
通信芯片306A、306B可以包括具有封装在其中的多个微电子器件(有源和无源两者)的微电子封装件。根据本说明书的另一个实施方式，通信芯片306A、306B的无源微电子器件可以被设置在封装体内，如以上所描述的。
在各个实施方式中，计算设备300可以是膝上型计算机、上网本、笔记本、超级本、智能电话、平板设备、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器、或数字视频录像机。在其它实施方式中，计算设备300可以是处理数据的任何其它电子设备。
应当理解的是，本说明书的主题不必限于在图1A-图5中示出的具体应用。如本领域技术人员将理解的，主题可以应用于其它微电子器件和组件应用、以及任何适当的电子应用。
下面的示例涉及另外的实施例。示例中的细节可以在一个或多个实施例中的任何地方使用。
在示例1中，一种微电子封装件可以包括：有源微电子器件，所述有源微电子器件与封装体接触；以及无源微电子器件，所述无源微电子器件被设置在形成于所述封装体中的腔内；其中，所述有源微电子器件和所述无源微电子器件通过形成在所述封装体中或所述封装体上的导电路径来电连接。
在示例2中，示例1的主题可以可选地包括：所述腔从所述封装体的第一表面至所述封装体的第二表面延伸穿过所述封装体。
在示例3中，示例1或示例2的主题可以可选地包括：所述有源微电子器件包括倒装芯片微电子器件，并且所述封装体包括微电子基板，其中，所述倒装芯片微电子器件通过在所述倒装芯片微电子器件与所述微电子基板之间延伸的多个互连件与所述微电子基板接触。
在示例4中，示例1或示例2的主题可以可选地包括：所述有源微电子器件嵌入在所述封装体中，并且其中，所述有源微电子器件的有源表面与所述封装体的第二表面实质上成平面。
在示例5中，示例4的主题可以可选地包括：所述导电路径形成在再分布层中，所述再分布层形成在所述有源微电子器件的有源表面和所述封装体的第二表面上。
在示例6中，示例1的主题可以可选地包括：所述封装体包括支撑板和电介质密封剂，其中，所述有源微电子器件的背面粘附至所述支撑板，并且其中，所述有源微电子器件嵌入在所述电介质密封剂中，其中所述电介质密封剂的一部分在所述有源微电子器件的有源表面上方延伸。
在示例7中，示例6的主题可以可选地包括：所述导电路径形成在再分布层中，所述再分布层形成在所述封装体的第二表面上。
在示例8中，示例7的主题可以可选地包括：所述腔延伸穿过所述再分布层、穿过所述电介质密封剂，并且部分地延伸到所述支撑板中。
在示例9中，一种用于制造微电子封装件的方法可以包括：形成有源微电子器件；形成封装体；使所述封装体与所述有源微电子器件接触；在所述封装体中或所述封装体上形成导电路径；在所述封装体中形成腔；在所述腔内设置无源微电子器件；以及利用所述导电路径电连接所述有源微电子器件与所述无源微电子器件。
在示例10中，示例9的主题可以可选地包括：在所述封装体中形成所述腔包括：形成所述腔以便从所述封装体的第一表面至所述封装体的第二表面延伸穿过所述封装体。
在示例11中，示例9或示例10的主题可以可选地包括：形成所述微电子器件包括形成倒装芯片微电子器件，其中，形成所述封装体包括形成微电子基板，并且其中，所述微电子器件通过在所述倒装芯片微电子器件与所述微电子基板之间延伸的多个互连件与所述微电子基板接触。
在示例12中，示例9或示例10的主题可以可选地包括：形成所述封装体以及使所述封装体与所述有源微电子器件接触包括：将所述微电子器件嵌入在所述封装体中，以使得所述微电子器件的有源表面与所述封装体的第二表面实质上成平面。
在示例13中，示例12的主题可以可选地包括：在所述封装体中或所述封装体上形成导电路径包括：在形成于所述微电子器件的有源表面和所述封装体的第二表面上的再分布层中形成所述导电路径。
在示例14中，示例9的主题可以可选地包括：形成所述封装体包括形成支撑板和形成电介质密封剂，其中，所述有源微电子器件的背面粘附至所述支撑板，并且其中，所述有源微电子器件嵌入在所述电介质密封剂中，其中所述电介质密封剂的一部分在所述有源微电子器件的有源表面上方延伸。
在示例15中，示例14的主题可以可选地包括：在所述封装体中或所述封装体上形成导电路径包括：在形成于所述封装体的第二表面上的再分布层中形成导电路径。
在示例16中，示例15的主题可以可选地包括：在所述封装体中形成所述腔包括：形成所述腔以延伸穿过所述再分布层、穿过所述电介质密封剂，并且部分地延伸到所述支撑板中。
在示例17中，一种计算设备可以包括：板；以及微电子封装件，所述微电子封装件附接至所述板，其中，所述微电子封装件包括：有源微电子器件，所述有源微电子器件与封装体接触；以及无源微电子器件，所述无源微电子器件被设置在形成于所述封装体中的腔内；其中，所述有源微电子器件和所述无源微电子器件通过形成在所述封装体中或所述封装体上的导电路径来电连接。
在示例18中，示例17的主题可以可选地包括：所述腔从所述封装体的第一表面至所述封装体的第二表面延伸穿过所述封装体。
在示例19中，示例17或示例18的主题可以可选地包括：所述有源微电子器件包括倒装芯片微电子器件，并且所述封装体包括微电子基板，其中，所述倒装芯片微电子器件通过在所述倒装芯片微电子器件与所述微电子基板之间延伸的多个互连件与所述微电子基板接触。
在示例20中，示例17或示例18的主题可以可选地包括：所述有源微电子器件嵌入在所述封装体中，并且其中，所述有源微电子器件的有源表面与所述封装体的第二表面实质上成平面。
在示例21中，示例20的主题可以可选地包括：所述导电路径形成在再分布层中，所述再分布层形成在所述有源微电子器件的有源表面和所述封装体的第二表面上。
在示例22中，示例17的主题可以可选地包括：所述封装体包括支撑板和电介质密封剂，其中，所述有源微电子器件的背面粘附至所述支撑板，并且其中，所述有源微电子器件嵌入在所述电介质密封剂中，其中所述电介质密封剂的一部分在所述有源微电子器件的有源表面上方延伸。
在示例23中，示例22的主题可以可选地包括：所述导电路径形成在再分布层中，所述再分布层形成在所述封装体的第二表面上。
在示例24中，示例23的主题可以可选地包括：所述腔延伸穿过所述再分布层、穿过所述电介质密封剂，并且部分地延伸到所述支撑板中。
因此已经详细描述了本说明书的实施例，应当理解的是，由所附权利要求限定的本说明书将并不由以上说明书中阐述的特定细节来限制，因为在不脱离其精神或范围的情况下，许多其显而易见的变型也是可能的。

Claims (24)

1.一种微电子封装件，包括：
有源微电子器件，所述有源微电子器件与封装体接触；以及
无源微电子器件，所述无源微电子器件被设置在形成于所述封装体中的腔内；
其中，所述有源微电子器件和所述无源微电子器件通过形成在所述封装体中或所述封装体上的导电路径来电连接。
2.根据权利要求1所述的微电子封装件，其中，所述腔从所述封装体的第一表面至所述封装体的第二表面延伸穿过所述封装体。
3.根据权利要求1或权利要求2所述的微电子封装件，其中，所述有源微电子器件包括倒装芯片微电子器件，并且所述封装体包括微电子基板，其中，所述倒装芯片微电子器件通过在所述倒装芯片微电子器件与所述微电子基板之间延伸的多个互连件与所述微电子基板接触。
4.根据权利要求1或权利要求2所述的微电子封装件，其中，所述有源微电子器件嵌入在所述封装体中，并且其中，所述有源微电子器件的有源表面与所述封装体的第二表面实质上成平面。
5.根据权利要求4所述的微电子封装件，其中，所述导电路径形成在再分布层中，所述再分布层形成在所述有源微电子器件的有源表面和所述封装体的第二表面上。
6.根据权利要求1所述的微电子封装件，其中，所述封装体包括支撑板和电介质密封剂，其中，所述有源微电子器件的背面粘附至所述支撑板，并且其中，所述有源微电子器件嵌入在所述电介质密封剂中，其中所述电介质密封剂的一部分在所述有源微电子器件的有源表面上方延伸。
7.根据权利要求6所述的微电子封装件，其中，所述导电路径形成在再分布层中，所述再分布层形成在所述封装体的第二表面上。
8.根据权利要求7所述的微电子封装件，其中，所述腔延伸穿过所述再分布层、穿过所述电介质密封剂，并且部分地延伸到所述支撑板中。
9.一种用于制造微电子封装件的方法，包括：
形成有源微电子器件；
形成封装体；
使所述封装体与所述有源微电子器件接触；
在所述封装体中或所述封装体上形成导电路径；
在所述封装体中形成腔；
在所述腔内设置无源微电子器件；以及
利用所述导电路径电连接所述有源微电子器件与所述无源微电子器件。
10.根据权利要求9所述的方法，其中，在所述封装体中形成所述腔包括：形成所述腔以便从所述封装体的第一表面至所述封装体的第二表面延伸穿过所述封装体。
11.根据权利要求9或权利要求10所述的方法，其中，形成所述微电子器件包括形成倒装芯片微电子器件，其中，形成所述封装体包括形成微电子基板，并且其中，所述微电子器件通过在所述倒装芯片微电子器件与所述微电子基板之间延伸的多个互连件与所述微电子基板接触。
12.根据权利要求9或权利要求10所述的方法，其中，形成所述封装体以及使所述封装体与所述有源微电子器件接触包括：将所述微电子器件嵌入在所述封装体中，以使得所述微电子器件的有源表面与所述封装体的第二表面实质上成平面。
13.根据权利要求12所述的方法，其中，在所述封装体中或所述封装体上形成导电路径包括：在形成于所述微电子器件的有源表面和所述封装体的第二表面上的再分布层中形成所述导电路径。
14.根据权利要求9所述的方法，其中，形成所述封装体包括形成支撑板和形成电介质密封剂，其中，所述有源微电子器件的背面粘附至所述支撑板，并且其中，所述有源微电子器件嵌入在所述电介质密封剂中，其中所述电介质密封剂的一部分在所述有源微电子器件的有源表面上方延伸。
15.根据权利要求14所述的方法，其中，在所述封装体中或所述封装体上形成导电路径包括：在形成于所述封装体的第二表面上的再分布层中形成导电路径。
16.根据权利要求15所述的方法，其中，在所述封装体中形成所述腔包括：形成所述腔以延伸穿过所述再分布层，穿过所述电介质密封剂，并且部分地延伸到所述支撑板中。
17.一种计算设备，包括：
板；以及
微电子封装件，所述微电子封装件附接至所述板，其中，所述微电子封装件包括：
有源微电子器件，所述有源微电子器件与封装体接触；以及
无源微电子器件，所述无源微电子器件被设置在形成于所述封装体中的腔内；
其中，所述有源微电子器件和所述无源微电子器件通过形成在所述封装体中或所述封装体上的导电路径来电连接。
18.根据权利要求17所述的计算设备，其中，所述腔从所述封装体的第一表面至所述封装体的第二表面延伸穿过所述封装体。
19.根据权利要求17或权利要求18所述的计算设备，其中，所述有源微电子器件包括倒装芯片微电子器件，并且所述封装体包括微电子基板，其中，所述倒装芯片微电子器件通过在所述倒装芯片微电子器件与所述微电子基板之间延伸的多个互连件与所述微电子基板接触。
20.根据权利要求17或权利要求18所述的计算设备，其中，所述有源微电子器件嵌入在所述封装体中，并且其中，所述有源微电子器件的有源表面与所述封装体的第二表面实质上成平面。
21.根据权利要求20所述的计算设备，其中，所述导电路径形成在再分布层中，所述再分布层形成在所述有源微电子器件的有源表面和所述封装体的第二表面上。
22.根据权利要求17所述的计算设备，其中，所述封装体包括支撑板和电介质密封剂，其中，所述有源微电子器件的背面粘附至所述支撑板，并且其中，所述有源微电子器件嵌入在所述电介质密封剂中，其中所述电介质密封剂的一部分在所述有源微电子器件的有源表面上方延伸。
23.根据权利要求22所述的计算设备，其中，所述导电路径形成在再分布层中，所述再分布层形成在所述封装体的第二表面上。
24.根据权利要求23所述的计算设备，其中，所述腔延伸穿过所述再分布层、穿过所述电介质密封剂，并且部分地延伸到所述支撑板中。
CN201480075442.0A 2014-03-12 2014-03-12 具有设置在封装体内的无源微电子器件的微电子封装件 Active CN105981159B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/024112 WO2015137936A1 (en) 2014-03-12 2014-03-12 Microelectronic package having a passive microelectronic device disposed within a package body

Publications (2)

Publication Number Publication Date
CN105981159A true CN105981159A (zh) 2016-09-28
CN105981159B CN105981159B (zh) 2020-10-16

Family

ID=54072204

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480075442.0A Active CN105981159B (zh) 2014-03-12 2014-03-12 具有设置在封装体内的无源微电子器件的微电子封装件

Country Status (8)

Country Link
US (2) US9997444B2 (zh)
EP (1) EP3117456B1 (zh)
JP (1) JP6293918B2 (zh)
KR (1) KR101862496B1 (zh)
CN (1) CN105981159B (zh)
SG (1) SG11201606359QA (zh)
TW (1) TWI625830B (zh)
WO (1) WO2015137936A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876290A (zh) * 2017-03-10 2017-06-20 三星半导体(中国)研究开发有限公司 晶圆级扇出型封装件及其制造方法
CN109962040A (zh) * 2017-12-19 2019-07-02 三星电子株式会社 半导体封装件以及堆叠型无源组件模块

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9953892B2 (en) * 2015-11-04 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Polymer based-semiconductor structure with cavity
DE102016114883B4 (de) 2015-11-04 2023-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Polymer-Basierte Halbleiterstruktur mit Hohlraum
KR101787840B1 (ko) * 2015-11-23 2017-10-19 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
JP6716967B2 (ja) * 2016-03-04 2020-07-01 富士ゼロックス株式会社 半導体パッケージ及び半導体パッケージの製造方法
US11355427B2 (en) * 2016-07-01 2022-06-07 Intel Corporation Device, method and system for providing recessed interconnect structures of a substrate
US10700011B2 (en) 2016-12-07 2020-06-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an integrated SIP module with embedded inductor or package
US10388637B2 (en) * 2016-12-07 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D interposer system-in-package module
US10797039B2 (en) 2016-12-07 2020-10-06 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a 3D interposer system-in-package module
DE102017111824A1 (de) * 2017-05-30 2018-12-06 Infineon Technologies Ag Package mit einer Komponente, die auf der Träger-Ebene verbunden ist
US10163773B1 (en) * 2017-08-11 2018-12-25 General Electric Company Electronics package having a self-aligning interconnect assembly and method of making same
US10804188B2 (en) * 2018-09-07 2020-10-13 Intel Corporation Electronic device including a lateral trace
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
WO2020166550A1 (ja) * 2019-02-14 2020-08-20 株式会社村田製作所 電子部品モジュールの製造方法、及び電子部品モジュール
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging
US11876085B2 (en) 2021-06-25 2024-01-16 Qualcomm Incorporated Package with a substrate comprising an embedded capacitor with side wall coupling

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388207B1 (en) * 2000-12-29 2002-05-14 Intel Corporation Electronic assembly with trench structures and methods of manufacture
US20060154496A1 (en) * 2002-10-08 2006-07-13 Tatsuro Imamura Wiring board incorporating components and process for producing the same
US20070013068A1 (en) * 2005-06-17 2007-01-18 Lsi Logic Corporation Integrated circuit package and method with an electrical component embedded in a substrate via
US20070210423A1 (en) * 2005-05-12 2007-09-13 Phoenix Precision Technology Corporation Embedded chip package structure
CN101843181A (zh) * 2007-11-01 2010-09-22 大日本印刷株式会社 内置元件电路板、内置元件电路板的制造方法
CN103378014A (zh) * 2012-04-13 2013-10-30 旭德科技股份有限公司 封装载板及其制作方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6228682B1 (en) * 1999-12-21 2001-05-08 International Business Machines Corporation Multi-cavity substrate structure for discrete devices
JP2003152303A (ja) 2001-08-27 2003-05-23 Ibiden Co Ltd 配線板
TW546800B (en) * 2002-06-27 2003-08-11 Via Tech Inc Integrated moduled board embedded with IC chip and passive device and its manufacturing method
US7141874B2 (en) * 2003-05-14 2006-11-28 Matsushita Electric Industrial Co., Ltd. Electronic component packaging structure and method for producing the same
TWI221336B (en) * 2003-08-29 2004-09-21 Advanced Semiconductor Eng Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same
US7498646B2 (en) * 2006-07-19 2009-03-03 Advanced Chip Engineering Technology Inc. Structure of image sensor module and a method for manufacturing of wafer level package
KR20080070991A (ko) * 2007-01-29 2008-08-01 삼성전자주식회사 반도체 모듈, 모듈 기판 및 이들의 제조 방법
US9466545B1 (en) * 2007-02-21 2016-10-11 Amkor Technology, Inc. Semiconductor package in package
JP2010219489A (ja) 2009-02-20 2010-09-30 Toshiba Corp 半導体装置およびその製造方法
KR101179386B1 (ko) * 2010-04-08 2012-09-03 성균관대학교산학협력단 패키지 기판의 제조방법
KR101752829B1 (ko) 2010-11-26 2017-06-30 삼성전자주식회사 반도체 장치
US8247269B1 (en) * 2011-06-29 2012-08-21 Fairchild Semiconductor Corporation Wafer level embedded and stacked die power system-in-package packages
US8716859B2 (en) 2012-01-10 2014-05-06 Intel Mobile Communications GmbH Enhanced flip chip package
US20130292852A1 (en) * 2012-05-03 2013-11-07 Infineon Technologies Ag Chip embedded packages and methods for forming a chip embedded package
US20140167273A1 (en) * 2012-12-19 2014-06-19 Qualcomm Incorporated Low parasitic package substrate having embedded passive substrate discrete components and method for making same
JP2014039005A (ja) * 2013-02-13 2014-02-27 Taiyo Yuden Co Ltd 電子部品内蔵基板
WO2016130859A1 (en) * 2015-02-11 2016-08-18 Endura Technologies LLC Switched power stage with integrated passive components

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388207B1 (en) * 2000-12-29 2002-05-14 Intel Corporation Electronic assembly with trench structures and methods of manufacture
US20060154496A1 (en) * 2002-10-08 2006-07-13 Tatsuro Imamura Wiring board incorporating components and process for producing the same
US20070210423A1 (en) * 2005-05-12 2007-09-13 Phoenix Precision Technology Corporation Embedded chip package structure
US20070013068A1 (en) * 2005-06-17 2007-01-18 Lsi Logic Corporation Integrated circuit package and method with an electrical component embedded in a substrate via
CN101843181A (zh) * 2007-11-01 2010-09-22 大日本印刷株式会社 内置元件电路板、内置元件电路板的制造方法
CN103378014A (zh) * 2012-04-13 2013-10-30 旭德科技股份有限公司 封装载板及其制作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876290A (zh) * 2017-03-10 2017-06-20 三星半导体(中国)研究开发有限公司 晶圆级扇出型封装件及其制造方法
US10461044B2 (en) 2017-03-10 2019-10-29 Samsung Electronics Co., Ltd. Wafer level fan-out package and method of manufacturing the same
US10580742B2 (en) 2017-03-10 2020-03-03 Samsung Electronics Co., Ltd. Wafer level fan-out package and method of manufacturing the same
CN109962040A (zh) * 2017-12-19 2019-07-02 三星电子株式会社 半导体封装件以及堆叠型无源组件模块

Also Published As

Publication number Publication date
US20160358848A1 (en) 2016-12-08
KR20160108476A (ko) 2016-09-19
US10522454B2 (en) 2019-12-31
US20180286799A1 (en) 2018-10-04
SG11201606359QA (en) 2016-09-29
EP3117456A4 (en) 2017-11-15
CN105981159B (zh) 2020-10-16
EP3117456B1 (en) 2022-05-11
JP6293918B2 (ja) 2018-03-14
TW201546974A (zh) 2015-12-16
EP3117456A1 (en) 2017-01-18
KR101862496B1 (ko) 2018-05-29
JP2017508296A (ja) 2017-03-23
US9997444B2 (en) 2018-06-12
WO2015137936A1 (en) 2015-09-17
TWI625830B (zh) 2018-06-01

Similar Documents

Publication Publication Date Title
CN105981159A (zh) 具有设置在封装体内的无源微电子器件的微电子封装件
RU2504863C2 (ru) Корпусы с многослойной укладкой кристаллов в устройстве типа корпус на корпусе, способы их сборки и системы, содержащие их
CN104681457B (zh) 多芯片集成的多级重布线层
CN106165092A (zh) 具有穿桥导电过孔信号连接的嵌入式多器件桥
CN105453261A (zh) 封装上封装堆叠微电子结构
CN104253115A (zh) 用于半导体封装中减小的管芯到管芯间隔的底部填充材料流控制
TW201633411A (zh) 模複合物內之三維結構
CN107646140A (zh) 用于形成封装结构中的沟槽的方法及由此形成的结构
CN105858589A (zh) 具有倒棱角的微电子管芯
US11705377B2 (en) Stacked die cavity package
TW201622023A (zh) 用以形成高密度穿模互連的方法
CN106663674A (zh) 具有模制化合物的集成电路组件
WO2016123115A1 (en) Package-on-package (pop) structure
CN106233458B (zh) 包括作为封装层中的通孔的导线的集成器件
CN107548519A (zh) 用于半导体器件的具有高高宽比的穿过电介质的导电路径
US11694987B2 (en) Active package substrate having anisotropic conductive layer
US20220319967A1 (en) Assembly of flexible and integrated module packages with leadframes
US20220352075A1 (en) Multi-die interconnect
US10658198B2 (en) Solder resist layer structures for terminating de-featured components and methods of making the same
US20220093568A1 (en) Film in substrate for releasing z stack-up constraint
TW202245173A (zh) 具有垂直熱路徑的高功率晶粒散熱器

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant