CN107548519A - 用于半导体器件的具有高高宽比的穿过电介质的导电路径 - Google Patents

用于半导体器件的具有高高宽比的穿过电介质的导电路径 Download PDF

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CN107548519A
CN107548519A CN201680022710.1A CN201680022710A CN107548519A CN 107548519 A CN107548519 A CN 107548519A CN 201680022710 A CN201680022710 A CN 201680022710A CN 107548519 A CN107548519 A CN 107548519A
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post
connection pad
subset
pad
hole
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CN107548519B (zh
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T·迈尔
A·沃尔特
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Intel Corp
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Intel IP Corp
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Abstract

描述了用于半导体器件的具有高高宽比的穿过电介质的导电路径。在一个示例中，在半导体基底上形成多个导电连接焊盘，以连接到形成在所述基底上的电路。在连接焊盘的子集中的每个连接焊盘上形成柱，该柱由导电材料形成。在半导体基底之上，包括在连接焊盘和柱之上形成电介质层。通过去除直接位于柱之上的电介质层来形成孔。利用导电材料填充所形成的孔，并在每个填充的孔之上形成连接器。

Description

用于半导体器件的具有高高宽比的穿过电介质的导电路径
技术领域
本说明书涉及在半导体器件上形成穿过电介质的导电路径，并且更具体地涉及使用导电柱形成的这种路径。
背景技术
半导体和微机械管芯或芯片常常被封装，以针对外部环境进行保护。封装向位于封装内部的管芯提供物理保护、稳定性、外部连接，并且在一些情况下，提供冷却。典型地，管芯被附接到基底，并且然后在管芯之上放置附接到基底的盖体。替代地，管芯被附接到盖体，并且然后在管芯上形成封装基底或再分布层。在一些情况下，管芯盖体横向延伸通过管芯区域，并且再分布层被施加到管芯区域和横向扩展区以形成扇出封装。
晶片级球栅阵列(WLB)封装和其它封装常常使用位于芯片表面与再分布层之间的电介质层。电介质层机械地保护管芯表面并且充当应力缓冲物。这有助于确保来自印刷电路板的应力不会损伤封装或通往板的封装连接。电介质层还限定了管芯的功能金属结构与连接到板的再分布层之间的间隙或距离。该间隙通过限制RDL与管芯表面之间的电容性耦合而提高了电气性能。此外，RDL与芯片表面之间的限定的间隙允许在两者之间构建具有明确限定的线阻抗的传输线。其它类型的封装使用芯片表面与封装基底之间的电介质层。
附图说明
在附图的图示中通过示例而非限制的方式示出了实施例，在附图中，类似的附图标记指代相似的元件。
图1是根据实施例的具有带有柱的导电焊盘的管芯的一部分的截面侧视示意图。
图2是根据实施例的施加了电介质层的图1的管芯的部分的截面侧视示意图。
图3是根据实施例的具有形成的过孔的图2的管芯的部分的截面侧视示意图。
图4是根据实施例的施加了图案化焊料停止层的图3的管芯的部分的截面侧视示意图。
图5是根据实施例的施加了焊料球的图4的管芯的部分的截面侧视示意图。
图6是根据实施例的具有带有柱的大焊盘和小焊盘的另一管芯的一部分的截面侧视示意图。
图7是根据实施例的被切块的图6的管芯的部分的截面侧视示意图。
图8是根据实施例的嵌入在附接到暂时载体的重构晶片中的图7的管芯的部分的截面侧视示意图。
图9是根据实施例的施加了电介质层的图8的重构晶片的部分的截面侧视示意图。
图10是根据实施例的具有形成的过孔的图9的重构晶片的部分的截面侧视示意图。
图11是根据实施例的在焊盘之上具有保护层的重构晶片中的管芯的截面侧视示意图。
图12是根据实施例的具有柱的管芯和模具槽的截面侧视示意图。
图13是根据实施例的在模具工具已经在管芯之上封闭之后的图12的管芯的截面侧视示意图。
图14是根据实施例的在移除模具工具和膜之后的图13的管芯的截面侧视示意图。
图15是根据实施例的并入了封装的管芯的计算装置的方框图。
具体实施方式
管芯和RDL或封装基底之间的电介质层的厚度直接与机械强度和RF性能相关。如果将电介质做得较薄，那么可能会由于焊盘或再分布金属化层与管芯之间的电容性耦合而降低封装的RF性能。为了使用厚度减小的电介质实现特定的线阻抗，线宽度也需要被减小。由于制造的限制，这常常是不可能的。同样利用小的电介质厚度和减小的线宽度，更难以控制宽度、厚度和阻抗的相对容限。同时，希望的是用于电源和地接触部的较大金属结构。当前的制造方法需要对应的较厚的电介质层用于这样的电源和地接触部。典型用于WLB的电介质材料中的电镀或填充的开口的直径是由电介质层的厚度确定的。常规上，较高的电介质厚度需要较大的开口。这是因为对于光刻而言，开口直径和过孔深度之间的高宽比受到电介质的感光成像部件的限制，或者对于激光钻孔而言，受到激光能力的限制。另一方面，较大的金属结构具有增大的电容性耦合，增大的电容性耦合降低了封装的RF性能。
对RDL叠置体内的结构之间以及这种结构与管芯之间的电容性耦合的重要贡献来自过孔，并且来自由这些过孔连接的管芯焊盘和RDL焊盘。非常小的过孔产生较小的电容性耦合。更小的过孔直径允许管芯上和RDL内的更小的焊盘直径。较小的焊盘进一步减小了电容性耦合。减小的过孔和焊盘尺度还允许增大布线密度。对于信号连接，可以使用较小的过孔。另一方面，常常将特定的电流承载能力用于电源和地连接。这些过孔可以更大，并且在本文中可以被称为具有标准焊盘尺度和过孔直径。
可以通过向管芯焊盘或其它焊盘表面施加柱来减小过孔的深度而不影响电介质层的厚度。柱允许管芯上的焊盘与RDL上的焊盘之间的过孔非常小，因为过孔仅在柱与RDL焊盘之间延伸。在柱的位置处这是较浅的深度。同时，对于电源和地连接，可以在较大焊盘上制造没有柱或具有非常短的柱的大过孔以实现更高电流容量。厚电介质和窄过孔提高了扇入型和扇出型二者的WLB封装以及其它封装的RF性能。
如本文所述，柱可以仅用于将具有小直径的那些过孔，或者柱可以用于所有焊盘或用于一些不同类型的焊盘。小焊盘上的柱允许过孔通过减小过孔深度来保持适当的高宽比。可以通过省略柱来并行地制造具有相同高宽比的具有较大直径和更大电介质厚度的其它过孔。较大的过孔可以用于电源连接和地连接等。由于柱的原因，过孔所需的深度小得多。柱允许针对小过孔直径和大过孔直径保持恒定的高宽比。这提高了可制造性。还可以使用柱来制造大过孔。然而，要仔细确保柱作用于管芯焊盘上的机械应力不会损伤管芯焊盘。
图1是已在晶片上形成的半导体管芯102的一部分的截面侧视示意图。晶片将包含更多管芯，尽管为简单起见仅示出了单个管芯的一部分。管芯102包含任何所需类型的逻辑、RF、电源或光学电路(未示出)或其一些组合。管芯的正面110具有不同尺寸的连接焊盘104、106。每个连接焊盘的尺寸可以由该连接焊盘必须要承载的电流量来确定，但也可以由其它因素确定，例如管芯的电路内的连接。管芯的背面是晶片的一部分(未示出)。
在每个小焊盘上形成柱108。柱由诸如铜或镍的导电材料形成，但也可以使用任何其它适合的导电材料。在一个示例中，将诸如TiN的保护层施加于芯片焊盘的表面。然后在整个晶片表面之上形成晶种层。然后施加光致抗蚀剂层并使其图案化以暴露小焊盘，并通过电镀形成柱。在去除光致抗蚀剂之后，蚀刻掉晶种层，并且留下图1的结构。可以将柱直径选择为足够小，以使柱完全位于焊盘内。这导致焊盘在蚀刻掉晶种层和光致抗蚀剂时被部分暴露。因此，施加保护层以放置损伤焊盘。在最后的叠置体中，保护层将柱与管芯焊盘分开。因此，将保护层选择为导电的。
图2是在已经在焊盘和柱之上施加电介质层112之后的图1的管芯的部分的截面侧视示意图。电介质层以机械方式保护管芯表面并充当管芯与板之间的应力缓冲物。电介质层还限定了位于管芯的形成在管芯的正面上的电路内的功能金属结构(未示出)与图4所示的再分布层之间的间隙。电介质层还限定了再分布层与管芯基底之间的距离。因此，可以使用电介质的特定最小厚度。
如果减小电介质层的厚度，则会影响封装性能。首先，电介质层会较不能够缓冲机械应力，这会降低板级可靠性。对于WLB和eWLB封装而言，电介质层被用作结构部件，因此较弱的电介质层可以允许灾难性的损伤。第二，再分布层与管芯的金属结构或管芯基底之间的距离会减小，这会导致封装的电气性能降低，尤其是在较高频率下。
图3是在已经形成过孔之后的图2的管芯的部分的截面侧视示意图。可以通过任何期望方式形成过孔。作为示例，电介质材料可以是光可构造的材料。一些光可构造的材料采取光敏聚合物电介质材料的形式，例如环氧树脂、聚酰亚胺、苯并环丁烯或聚苯并噻唑等。该电介质材料表现得像光致抗蚀剂那样，以形成开口，但在形成并电镀过孔开口之后不去除该电介质材料。可以通过光刻来在连接焊盘104、106之上产生过孔开口。通常，取决于过孔的特定高宽比(高度与直径之比)，仅能够实现好的过孔限定。对于任何给定的电介质层深度，该高宽比将需要最小过孔直径。特定最大高宽比取决于使用的材料和用于形成开口并填充或电镀开口的工艺。
如所示，宽的连接焊盘104允许从电介质的顶部延伸到电介质的底部处焊盘的深过孔116。另一方面，用于较小焊盘106的开口不够宽，不能允许过孔120向下到达电介质的底部。由于柱的原因，较窄的过孔仅需要向下到达柱以连接到较小焊盘。结果，大过孔和小过孔的高宽比可以近似相等。假如每个过孔都宽或大到足以到达期望深度，高宽比也可以相差很大。
在已经形成过孔之后，在电介质和过孔之上形成导电布线层122，以在过孔和焊盘之间形成任何期望的连接。可以形成额外的电介质和布线层，以形成多层再分布层和任何其它期望的结构。根据需要，可以由浅过孔通过每个电介质层连接布线层。多层RDL叠置体内的层之间的连接也可以由柱以及所描述的用于连接到芯片的过孔构成。填充孔的导电材料可以与构成RDL的层的材料相同，并可以以与形成柱的方式相同的方式来施加该导电材料。替代地，可以通过各种不同工艺中的任何工艺(可以彼此相同或不同)来产生柱、导电层和过孔。在一些实施例中，在管芯之上沉积晶种层。在晶种层之上沉积光致抗蚀剂层，并且然后通过曝光和蚀刻使该光致抗蚀剂层图案化。对光致抗蚀剂中的开口进行电镀，并且然后蚀刻掉光致抗蚀剂和晶种层。
图4是在形成再分布层之后的图3的管芯的部分的截面侧视示意图。在管芯之上形成焊料停止层124并使其图案化，以生成暴露再分布层中的焊盘的开口126。在图5中，在这些开口中沉积焊料球并将其附接到暴露的RDL焊盘。管芯可以均是从晶片切换或单一化得到的，并且可以应用任何额外的加工或抛光来抛光每个管芯。
图6是晶片上的与图1的管芯类似的管芯的一部分的截面示意图。在该示例中，示出了eWLB(嵌入式晶片级球栅阵列)工艺。在eWLB工艺中，首先对管芯进行单一化，并且然后将其嵌入模具载体中。向管芯和周围的模制化合物区域施加RDL。然后，通过锯切经重构的晶片将管芯构成的封装与周围的模制化合物彼此分开。这在下一组附图中示出。用于eWLB封装的RDL可以通过与上文相对于WLB封装所示的相同的方式受益于导电柱技术。
在图6中，示出了制造在硅基底(未示出)上的管芯202的一部分。管芯具有形成于其正面210上的内部电路，类似于图1所示。该电路装配有外部连接焊盘，其中一些外部连接焊盘204的直径宽或大，并且其中一些外部连接焊盘206的直径窄或小。如每个例示的示例中那样，管芯焊盘被论述为圆形，但取决于电路类型和要使用的RDL设计，管芯焊盘可以采取任何适当形状。在小焊盘之上形成柱208。
柱被示为尺寸仅稍小于焊盘，然而，柱可以比焊盘更小或更大。柱可以具有类似焊盘的圆形横截面或任何其它适合的横截面。如所示的柱具有电介质层的高度的大约一半。然而，柱的高度可以被调整以适合任何特定设计。这受到抗电镀剂(plating resist)中的开口的最大高宽比的限制。在描述的示例中，柱和过孔形成有类似高宽比，然而，这不是必须的。如附图的示例中所示，柱与过孔的高度大致相同。这样允许将柱和过孔的导电路径被形成为具有柱或过孔本身的高宽比的两倍。换言之，在这些示例中，包括柱的最终导电路径是用于过孔的制造工艺本身所允许的宽度的一半或是其两倍高或长。可以修改柱、开口以及结构的其它方面的尺寸以获得不同的高宽比和相对于总体过孔的不同的柱数量。替代地，对于较长路径，可以使用能够实现较高高宽比的抗电镀剂。也可以将柱叠置，即，可以在第一柱之上形成第二柱。这可以在去除第一光致抗蚀剂之前完成。
图7是其中晶片已经被锯切的图6的管芯的部分的截面示意图。通过锯切或以任何其它期望方式将晶片切块以从一个晶片形成很多小的管芯。这由锯口线212指示。
图8是两个单一化的管芯202、203的横截面侧视示意图。这些管芯已经被压入释放条带220，并且正面210与条带接触。释放条带已经被附接到暂时载体222以承载管芯并保持其彼此的相对位置。柱被压入释放条带中，但柱没有长到干扰管芯在条带上的黏着或定位的程度。管芯一旦被置于条带上的位置中，就被覆盖在模制化合物224中。在该示例中，模制化合物覆盖管芯并且也在管芯之间，以将管芯牢固地固定住。
图9是在使模制化合物固化之后的图6的管芯的截面侧视示意图。将释放条带220释放并去除暂时载体222。通过模制化合物将管芯固定住。尽管仅示出了一个管芯202，但可以同时处理更多的管芯。类似于图2的过程，在管芯的暴露的正面210和周围模制化合物表面之上施加电介质层226。
图10是已经如本文所述通过在光可构造的电介质中进行光刻而形成开口之后的图9的管芯的截面侧视示意图。替代地，可以通过任何其它所需的方式形成开口。
在电介质中形成开口之后，可以通过如上所述相同的方式处理电介质。沉积RDL，并且在同一步骤中，填充过孔。取决于特定实施方式，可以形成RDL的更多层。如图4所示的沉积并结构化的焊料停止层并使其图案化，以形成如图5所示的焊料球栅。然后通过锯切或切割穿过RDL和模制化合物来将管芯彼此分开，以获得个体的管芯封装。
上面将本文描述的柱示为施加于图1中的扇入晶片级封装，并且还施加于扇出晶片级封装，例如，图6中的eWLB封装。在eWLB封装的情况下，可以在解理前的硅晶片上或在RDL制造工艺的第一步中的重构的晶片上施加柱。当在硅晶片上施加柱时，与在重构的晶片上相比，更加精确地控制焊盘的相对位置。精确的柱定位对于对准过孔并允许管芯表面上有较小直径的焊盘是重要的。
在图8中，在对管芯进行单一化并将其封装时(也称为重建)，管芯可能发生位置偏移。在该管芯偏移中，管芯从其在初始硅晶片中的标称位置移开到达重构的模制化合物晶片中的不同位置。这可能对在焊盘上精确定位柱造成问题。对于小焊盘并且当焊盘靠近在一起时，精确度特别重要。在硅晶片级上施加柱之后，在为了重构而进行单一化之前，然后可以拾取管芯并将管芯放在模具载体上的粘合剂上。柱被嵌入条带的粘合剂中，并且因此不会受到工艺的不利影响。
图11示出了可以如何采纳另一种用于形成过孔开口的技术。图11是模制化合物224中包封的管芯202的横截面侧视示意图。已经施加了电介质层226。然而，在施加电介质层之前，利用保护材料230电镀每个连接焊盘。在形成开口的同时，保护材料保护焊盘。作为示例，可以使用激光烧蚀形成开口，然而，薄焊盘可能受到损伤。保护材料层将在烧蚀电介质时提供额外的牺牲屏障来抵抗激光。
可以在如图1和6所示的形成柱的同时施加保护材料。材料可以与柱是相同的材料，例如，铜。这允许形成保护材料而不会增加额外的工艺步骤。由于电镀期间较小焊盘处的电流密度较高，较宽焊盘上的柱一般将具有较小高度。尽管较宽焊盘上的较短的柱对于形成过孔而言可能不必要，但它们也不会对工艺有害，并可以在焊盘和过孔之间提供更好的电连接。
如所示，利用基于面板的或其它类似技术，可以使用激光来打开过孔。在该情况下，大的过孔焊盘也可以被覆盖有柱。柱保护芯片焊盘不被激光烧蚀，即，它们充当激光进行的过孔开口工艺的停止部。这些大的柱的高度可以小于小过孔焊盘的柱。
可以通过多种不同方式中的任何方式进行柱的释放，其中使柱的顶侧能够被再分布层或其它电连接触及。在一些实施例中，在管芯或晶片的整个表面之上施加电介质的全场去除，直到暴露出柱。该去除可以通过等离子体蚀刻、研磨、切割(例如，利用金刚石刀片、飞剪)等进行。这些去除工艺可能不如用于打开过孔的激光和光刻工艺那么昂贵。
在其它实施例中，可以使用膜辅助的模制。在该实施例中，模制化合物用作覆盖带柱的管芯的正面的电介质。可以以薄片、液体形式或颗粒形式施加模制化合物。
图12是使用模制化合物向管芯的顶部施加柱以构建过孔的截面侧视示意图。已经在硅基底302上形成了具有集成电路或其它结构的管芯。电路或其它结构具有通过多个导电焊盘304的外部连接。这些焊盘可以具有不同的尺寸并被布置成方便连接。针对至少一些焊盘，柱306已被安装在焊盘之上。此外，模制化合物308已被施加在管芯之上。在该示例中，模制化合物是液体，其将散布在管芯之上，然而，可以替代地使用其它形式。利用面向管芯的软膜310覆盖顶部模具槽312。
图13是在模具槽在模制化合物、柱、以及管芯的顶部之上封闭之后的图12的管芯和模具槽的侧视截面示意图。结果，在向下按压膜时，柱向上通过模制化合物而压入膜310中。
图14是去除了模具工具的管芯的侧视截面示意图。在打开模具槽312并去除膜310之后，柱已经暴露在模制化合物上方。这是部分发生的，因为如图13所示，柱被压入膜中。在去除膜时，柱被暴露。因此，不需要例如如图9所示的独立过孔打开步骤。
然后可以通过产生再分布层和上文针对其它管芯类型所述的其它操作而继续管芯的处理。作为示例，可以通过溅镀晶种层、施加抗电镀剂并使其图案化、电镀导电再分布线、剥离抗蚀剂、以及蚀刻晶种层来制造再分布层。可以将此过程重复多次，以根据需要构建尽量多的布线层。可以由短过孔连接布线层。
尽管本文描述的示例涉及WLB封装，但可以将类似技术用于各种其它类型的管芯和封装技术。不论晶片或管芯类型如何，都可以在晶片级或管芯级上在管芯接触部之上形成柱，并且然后可以在接触部和本文所述的柱之上形成厚电介质，从而可以形成仅为达到柱所必需的深度的过孔。
图15是根据一种实施方式的计算装置100的方框图。计算装置100容纳系统板2。板2可以包括若干部件，包括但不限于处理器4和至少一个通信封装6。通信封装耦合到一个或多个天线16。处理器4物理和电耦合到板2。至少一个天线16与通信封装6集成，并且通过封装物理和电耦合到板2。在一些实施方式中，可以使用如上所述的穿硅过孔在管芯上形成部件、控制器、集线器或接口中的任何一个或多个。
取决于其应用，计算装置100可以包括可以或可以不物理和电耦合到板2的其它部件。这些其它部件包括但不限于易失性存储器(例如，DRAM)8、非易失性存储器(例如，ROM)9、闪速存储器(未示出)、图形处理器12、数字信号处理器(未示出)、密码处理器(未示出)、芯片组14、天线16、诸如触摸屏显示器的显示器18、触摸屏控制器20、电池22、音频编解码器(未示出)、视频编解码器(未示出)、功率放大器24、全球定位系统(GPS)装置26、罗盘28、加速度计(未示出)、陀螺仪(未示出)、扬声器30、相机32和大容量存储装置(例如，硬盘驱动器)10、光盘(CD)(未示出)、数字多用盘(DVD)(未示出)等。这些部件可以连接到系统板2，安装到系统板或与任何其它部件组合。
如本文所述，这些部件中的任何一个或多个可以实施为封装的半导体管芯。可以将这里示出的部件组合成单个集成电路管芯或可以将其组合成单个封装。其它部件可以实施为一个或多个封装中的多个管芯。封装可以直接或通过系统板彼此连接。
通信封装6能够实现用于向和从计算装置100传输数据的无线和/或有线通信。术语“无线”及其派生词可以用于描述可以通过非固体介质使用经调制的电磁辐射来传送数据的电路、装置、系统、方法、技术、通信信道等。该术语不暗示相关联的装置不包含任何线路，尽管在一些实施例中它们可能不包含。通信封装6可以实施若干无线或有线标准或协议中的任何标准或协议，包括但不限于Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、EDCT、蓝牙、以太网、其衍生物，以及被指定为3G、4G、5G和更高代的任何其它无线和有线协议。计算装置100可以包括多个通信封装6。例如，第一通信封装6可以专用于较短距离无线通信，例如Wi-Fi和蓝牙，并且第二通信封装6可以专用于较长距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其它。
计算装置100的处理器4包括封装于处理器4内的集成电路管芯。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可以存储于寄存器和/或存储器中的其它电子数据的任何装置或装置的部分。
在各种实施方式中，计算装置100可以是膝上型计算机、上网本、笔记本、超级本、智能电话、平板计算机、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器或数字视频录像机。在其它实施方式中，计算装置100可以是可穿戴装置，例如手表、眼镜、耳机或健身装置、用于物联网的节点或处理数据的任何其它电子装置。
各实施例可以被实施为一个或多个存储器芯片、控制器、CPU(中央处理单元)、使用母板互连的微芯片或集成电路、专用集成电路(ASIC)和/或现场可编程门阵列(FPGA)的一部分。
对“一个实施例”、“实施例”、“示例性实施例”、“各实施例”等的引用指示这样描述的(多个)实施例可以包括特定特征、结构或特性，但并非每个实施例都必需包括该特定特征、结构或特性。此外，一些实施例可以具有针对其它实施例所描述的特征中的一些、全部或不具有该特征。
在以下描述和权利要求中，可以使用术语“耦合”及其派生词。“耦合”用于指示两个或更多元件彼此合作或相互作用，但它们之间可以或可以不具有居间的物理或电气部件。
如权利要求中所用的，除非另行指定，否则使用序数形容词“第一”、“第二”、“第三”等描述共同的元件，仅指示正在提及相似元件的不同实例，而并非旨在暗示这样描述的元件必须要在时间上、空间上、排序上或以任何其它方式采用给定的序列。
附图和前面的描述给出了实施例的示例。本领域的技术人员将认识到所描述的元件中的一者或多者可以很好地组合成单个功能元件。替代地，某些元件可以被分成多个功能元件。可以将来自一个实施例的元件添加到另一个实施例。例如，本文所述的工艺的次序可以被改变，并且不限于本文所述的方式。此外，任何流程图的动作都不需要以所示次序实施；所有动作也不一定都必需要执行。而且，那些不依赖于其它动作的动作可以与其它动作并行或组合执行。实施例的范围绝不受到这些具体示例的限制。许多变化都是可能的，无论是否在说明书中明确给出，所述变化例如是结构、尺度和材料使用上的差异。实施例的范围至少与以下权利要求给出的范围一样宽。
以下示例涉及其它实施例。不同实施例的各种特征可以通过各种方式进行组合，其中一些特征被包括在内，而其它特征被排除，以适应多种不同应用。一些实施例涉及一种方法，其包括：在半导体基底上形成多个导电连接焊盘以连接到形成在基底上的电路；在连接焊盘的子集中的每个连接焊盘上形成柱，所述柱由导电材料形成；在半导体基底之上，包括在连接焊盘和柱之上形成电介质层；通过去除直接位于柱之上的电介质层来形成孔；利用导电材料填充所形成的孔；以及在每个被填充的孔之上形成连接器。
在其它实施例中，柱从基底延伸到电介质层的大约一半的高度。
在其它实施例中，柱和所形成的孔具有横截面表面积，并且柱具有比孔更大的横截面表面积。
在其它实施例中，柱的导电材料和填充所述孔的导电材料是相同的导电材料。
在其它实施例中，导电材料是铜。
在其它实施例中，形成多个导电连接焊盘包括形成具有第一直径的连接焊盘的第一子集和具有更大的第二直径的连接焊盘的第二子集，并且其中，形成柱包括仅在连接焊盘的第一子集的焊盘上形成柱。
在其它实施例中，形成孔包括使用图案化的光致抗蚀剂形成孔以及蚀刻在导电连接焊盘之上的电介质层。
在其它实施例中，形成孔包括使用光可构造电介质，暴露出电介质的位于导电连接焊盘之上的部分，以及去除未暴露的电介质。
在其它实施例中，填充所形成的孔包括将铜电镀至孔中。
在其它实施例中，形成多个导电连接焊盘包括形成具有第一直径的连接焊盘的第一子集和具有更大的第二直径的连接焊盘的第二子集，并且其中，形成柱包括在连接焊盘的第一子集和第二子集的焊盘上形成柱，并且其中，形成孔包括通过激光烧蚀形成孔。
其它实施例包括在形成柱之后将半导体基底切块以形成多个管芯，以及在模制化合物中嵌入多个管芯中的至少一部分，并且暴露所述柱，并且其中，形成电介质层是在嵌入之后执行的。
在其它实施例中，嵌入还包括在条带上放置管芯中的至少一部分，使得柱嵌入条带中，该条带被附接到暂时载体，在管芯和暂时载体之上施加模制化合物，以及去除条带和暂时载体以暴露柱。
其它实施例包括在填充孔的同时在电介质层之上形成再分布层，并且其中，形成连接器包括形成焊料球阵列。
在其它实施例中，形成孔包括在电介质之上溅镀晶种层，在所述晶种层之上沉积光致抗蚀剂并使其图案化，并且其中，填充所述孔包括在图案化的光致抗蚀剂中的开口之上进行电镀，剥离所述光致抗蚀剂以及蚀刻所述晶种层。
在其它实施例中，形成孔包括减小所述电介质的高度以暴露所述柱之上并且也在整个基底之上的所述柱。
在其它实施例中，减小包括施加从研磨、抛光、切割和蚀刻的集合中选择的工艺。
在其它实施例中，形成柱包括在连接焊盘的子集中的每个连接焊盘之上施加保护层，在半导体基底之上施加晶种层，对半导体基底之上的光致抗蚀剂进行图案化，其中在连接焊盘的子集之上具有开口，利用导电材料电镀开口以形成柱，以及去除图案化的光致抗蚀剂。
一些实施例涉及一种半导体器件封装，其包括：半导体基底上的多个导电连接焊盘以连接到形成在基底上的电路；连接焊盘的子集中的每个连接焊盘上的柱，该柱由导电材料形成；半导体基底之上的电介质层，包括连接焊盘和柱之上的电介质层；不属于该子集的每个连接焊盘之上以及连接焊盘的子集的每个柱之上的填充的过孔；以及每个填充的过孔之上的连接器。
在其它实施例中，柱从基底延伸到电介质层的大约一半的高度。
在其它实施例中，柱和形成的孔具有横截面表面积，并且柱具有比孔更大的横截面表面积。
在其它实施例中，柱和过孔的导电材料是相同的导电材料。
在其它实施例中，连接焊盘的第一子集具有第一直径，并且连接焊盘的第二子集具有更大的第二直径，并且该柱仅在连接焊盘的第一子集的焊盘上。
其它实施例包括在电介质层之上的再分布层，并且其中，连接器包括焊料球阵列。
一些实施例涉及一种系统，其包括系统板、连接到系统板的存储器以及连接到系统板并通过系统板耦合到存储器的处理器，处理器具有半导体管芯，半导体管芯具有：半导体基底上的多个导电连接焊盘以连接到形成在基底上的电路；连接焊盘的子集中的每个连接焊盘上的柱，该柱由导电材料形成；半导体基底之上的电介质层，包括连接焊盘和柱之上的电介质层；不属于该子集的每个连接焊盘之上以及连接焊盘的子集的每个柱之上的填充的过孔；以及每个填充的过孔之上的连接器。
在其它实施例中，柱从基底延伸到电介质层的大约一半的高度。
在其它实施例中，连接焊盘的第一子集具有第一直径，并且连接焊盘的第二子集具有更大的第二直径，并且该柱仅在连接焊盘的第一子集的焊盘上。

Claims (26)

1.一种方法，包括：
在半导体基底上形成多个导电连接焊盘，以连接到形成在所述基底上的电路；
在所述连接焊盘的子集中的每个连接焊盘上形成柱，所述柱由导电材料形成；
在所述半导体基底之上，包括在所述连接焊盘和所述柱之上形成电介质层；
通过去除直接位于所述柱之上的所述电介质层来形成孔；
利用导电材料填充所形成的孔；以及
在每个填充的孔之上形成连接器。
2.根据权利要求1所述的方法，其中，所述柱从所述基底延伸到所述电介质层的大约一半的高度。
3.根据权利要求1或2所述的方法，其中，所述柱和所形成的孔具有横截面表面积，并且所述柱具有比所述孔更大的横截面表面积。
4.根据权利要求1-3中的任一项或多项所述的方法，其中，所述柱的导电材料和填充所述孔的导电材料是相同的导电材料。
5.根据权利要求1-4中的任一项或多项所述的方法，其中，所述导电材料是铜。
6.根据权利要求1-5中的任一项或多项所述的方法，其中，形成多个导电连接焊盘包括形成具有第一直径的所述连接焊盘的第一子集和具有更大的第二直径的所述连接焊盘的第二子集，并且其中，形成柱包括仅在连接焊盘的所述第一子集的焊盘上形成柱。
7.根据权利要求6所述的方法，其中，形成孔包括使用图案化的光致抗蚀剂形成孔以及蚀刻在所述导电连接焊盘之上的所述电介质层。
8.根据权利要求6所述的方法，其中，形成孔包括：使用光可构造的电介质，暴露所述电介质的位于所述导电连接焊盘之上的一部分，以及去除未暴露的电介质。
9.根据权利要求8所述的方法，其中，填充所形成的孔包括将铜电镀至所述孔中。
10.根据权利要求1-9中的任一项或多项所述的方法，其中，形成多个导电连接焊盘包括形成具有第一直径的所述连接焊盘的第一子集和具有更大的第二直径的所述连接焊盘的第二子集，并且其中，形成柱包括在连接焊盘的所述第一子集和所述第二子集的焊盘上形成柱，并且其中，形成孔包括通过激光烧蚀形成孔。
11.根据权利要求1-10中的任一项或多项所述的方法，还包括：
在形成所述柱之后将所述半导体基底切块以形成多个管芯，以及
在模制化合物中嵌入所述多个管芯中的至少一部分，并且暴露所述柱，并且
其中，形成电介质层是在嵌入之后执行的。
12.根据权利要求10所述的方法，其中，嵌入还包括：
在条带上放置所述管芯中的至少一部分，使得所述柱嵌入所述条带中，所述条带被附接到暂时载体；
在所述管芯和所述暂时载体之上施加所述模制化合物；以及
去除所述条带和所述暂时载体以暴露所述柱。
13.根据权利要求1所述的方法，还包括在填充所述孔的同时在所述电介质层之上形成再分布层，并且其中，形成连接器包括形成焊料球阵列。
14.根据权利要求1-13中的任一项或多项所述的方法，其中，形成孔包括：在所述电介质之上溅镀晶种层，在所述晶种层之上沉积光致抗蚀剂并使其图案化，并且其中，填充所述孔包括：在图案化的光致抗蚀剂中的开口之上进行电镀，剥离所述光致抗蚀剂以及蚀刻所述晶种层。
15.根据权利要求1-14中的任一项或多项所述的方法，其中，形成孔包括减小所述电介质的高度以暴露位于所述柱之上并且也位于整个基底之上的所述柱。
16.根据权利要求15所述方法，其中，减小包括施加从研磨、抛光、切割和蚀刻的集合中选择的工艺。
17.根据权利要求1-16中的任一项或多项所述的方法，其中，形成柱包括：
在连接焊盘的所述子集中的每个连接焊盘之上施加保护层；
在所述半导体基底之上施加晶种层；
在所述半导体基底之上对光致抗蚀剂进行图案化，其中在连接焊盘的所述子集之上具有开口；
利用导电材料电镀所述开口以形成所述柱；以及
去除图案化的光致抗蚀剂。
18.一种半导体器件封装，包括：
半导体基底上的多个导电连接焊盘，以连接到形成在所述基底上的电路；
所述连接焊盘的子集中的每个连接焊盘上的柱，所述柱由导电材料形成；
所述半导体基底之上、包括所述连接焊盘和所述柱之上的电介质层；
不属于所述子集的每个连接焊盘之上以及所述连接焊盘的所述子集的每个柱之上的填充的过孔；以及
每个填充的过孔之上的连接器。
19.根据权利要求18所述的封装，其中，所述柱从所述基底延伸到所述电介质层的大约一半的高度。
20.根据权利要求18或19所述的封装，其中，所述柱和形成的孔具有横截面表面积，并且所述柱具有比所述孔更大的横截面表面积。
21.根据权利要求18-20中的任一项或多项所述的封装，其中，所述柱和所述过孔的导电材料是相同的导电材料。
22.根据权利要求18-21中的任一项或多项所述的封装，其中，所述连接焊盘的第一子集具有第一直径，并且所述连接焊盘的第二子集具有更大的第二直径，并且所述柱仅在连接焊盘的所述第一子集的焊盘上。
23.根据权利要求18-22中的任一项或多项所述的封装，还包括所述电介质层之上的再分布层，并且其中，所述连接器包括焊料球阵列。
24.一种系统，包括：
系统板；
连接到所述系统板的存储器；以及
连接到所述系统板并通过所述系统板耦合到所述存储器的处理器，所述处理器具有半导体管芯，所述半导体管芯具有：半导体基底上的多个导电连接焊盘以连接到形成在所述基底上的电路；所述连接焊盘的子集中的每个连接焊盘上的柱，所述柱由导电材料形成；所述半导体基底之上，包括所述连接焊盘和所述柱之上的电介质层；不属于所述子集的每个连接焊盘之上以及所述连接焊盘的所述子集的每个柱之上的填充的过孔；以及每个填充的过孔之上的连接器。
25.根据权利要求24所述的系统，其中，所述柱从所述基底延伸到所述电介质层的大约一半的高度。
26.根据权利要求24或25所述的系统，其中，所述连接焊盘的第一子集具有第一直径，并且所述连接焊盘的第二子集具有更大的第二直径，并且所述柱仅在连接焊盘的所述第一子集的焊盘上。
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CN102044515A (zh) * 2009-10-14 2011-05-04 日月光半导体制造股份有限公司 封装载板、封装结构以及封装载板工艺
US20140093999A1 (en) * 2012-09-29 2014-04-03 Weng Hong Teh Embedded structures for package-on-package architecture

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US20170148698A1 (en) 2017-05-25
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TW201705406A (zh) 2017-02-01
KR102510359B1 (ko) 2023-03-14

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