TWI711140B - 用以形成半導體裝置之方法、半導體裝置封裝體及運算系統 - Google Patents

用以形成半導體裝置之方法、半導體裝置封裝體及運算系統 Download PDF

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TWI711140B
TWI711140B TW105111521A TW105111521A TWI711140B TW I711140 B TWI711140 B TW I711140B TW 105111521 A TW105111521 A TW 105111521A TW 105111521 A TW105111521 A TW 105111521A TW I711140 B TWI711140 B TW I711140B
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forming
pillar
pads
subset
connection pads
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TW105111521A
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TW201705406A (zh
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特羅斯登 梅耶爾
安德烈亞斯 沃特
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美商英特爾Ip公司
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Abstract

用於半導體裝置之貫穿具有高縱橫比的介電質之傳導路徑被敘述。在一範例中，複數個傳導連接襯墊被形成在一半導體基板上用以連接至被形成在該基板上之電路。一支柱被形成在該等連接襯墊的一子集合之各個上，該等支柱由一傳導材料所形成。一介電層被形成在該半導體基板之上，包括在該等連接襯墊及該等支柱之上。孔洞係藉由直接移除在該等支柱上之該介電材料層而被形成。被形成的該等孔洞由一傳導材料所填充且一連接件被形成在各個被填充的孔洞之上。

Description

用以形成半導體裝置之方法、半導體裝置封裝體及運算系統 發明領域
本說明書係有關於在一半導體裝置上形成傳導路徑貫穿一介電質，且特別地關於使用一傳導支柱所形成的此一路徑。
發明背景
半導體及微機械晶粒或晶片係經常性地被封裝用於保護抵禦一外部環境。該封裝體提供物理性保護、穩定性、外部連接，且在一些情況中，冷卻該等封裝體內之該晶粒。典型地該晶粒被附接於一基板上，且隨後附接於該基板之一覆蓋體被放置於該晶粒之上。或者，該晶粒被附接於一覆蓋體，且隨後一封裝基板或重分佈層被形成在該晶粒上。在一些情況中，一晶粒覆蓋體橫向地延伸越過該晶粒區域，並且該重分佈層被施加於該晶粒區域及該橫向延伸用以形成一扇出封裝體(fan-out package)。
晶圓級球狀柵陣列(WLB)封裝體及其他封裝體時常使用在該晶片表面及該等重分佈層之間的一介電層。該介電層機械地保護該晶粒表面且功能作為一應力緩衝。 這會幫助確保來自一印刷電路板之應力不會損害該封裝體或連接至該板之該等封裝。該介電層也界定出在該晶粒之該等功能性的金屬結構以及連接至該板的該等重分佈層之間的一間隙或距離。此間隙藉由限制在該RDL及該晶粒表面之間的電容耦合來改善電氣性能。此外，一在該RDL及該晶片表面之間的經界定之間隙允許傳輸線被建立在該等兩者之間帶有一良適定義的線阻抗。封裝體的其他形式使用一在該晶片表面及封裝基板之間的介電層。
依據本發明之一實施例，係特地提出一種方法，其包含：在一半導體基板上形成複數個傳導連接襯墊用以連接至被形成在該基板上的電路；在該等連接襯墊之至少一者上形成一支柱，該支柱係以一傳導材料所形成；在該半導體基板之上形成一介電層，其包括在該等連接襯墊及該支柱之上；藉由移除直接在該支柱之上的該介電層來形成一孔洞；以一傳導材料填充被形成的該孔洞；以及在被填充的該孔洞上形成一連接件。
2:系統板
4:處理器
6:通訊封裝體
8:揮發性記憶體
9:非揮發性記憶體
10:大容量儲存裝置
12:圖形處理器
14:晶片組
16:天線
18:顯示器
20:觸控螢幕控制器
22:電池
24:功率放大器
26:全球定位系統
28:羅盤
30:揚聲器
32:影像攝錄器
100:計算裝置
102:主機板
102:半導體晶粒
104:連接襯墊
106:連接襯墊
108:支柱
110:晶粒前側
112:介電層
116:深通孔
120:通孔
122:傳導佈線層
126:開口
202:晶粒
203:晶粒
204:連接襯墊
206:連接襯墊
208:支柱
210:晶粒前側
212:鋸口線
220:釋放帶
222:暫時載體
224:模複合物
226:介電層
230:保護材料
302:矽基板
304:傳導襯墊
306:支柱
308:模複合物
310:軟膜
312:頂部模具槽
實施例以範例的方式被例示說明，而並非以限制的方式為之，在隨附之該等圖式中，其中類似的參考標號意指相似的元件。
圖1係依據一實施例之帶有傳導襯墊偕同支柱之一晶粒的一部分之一橫截面側視圖。
圖2係依據一實施例之帶有一介電層施加於圖1 之該晶粒的該部分之一橫截面側視圖。
圖3係依據一實施例之圖2帶有被形成的通孔之該晶粒的該部分之一橫截面側視圖。
圖4係依據一實施例之帶有一被圖案化的焊料終止層施加於圖3之該晶粒的該部分之一橫截面側視圖。
圖5係依據一實施例之帶有焊料球施加於圖4之該晶粒的該部分之一橫截面側視圖。
圖6係依據一實施例之帶有大襯墊及小襯墊偕同支柱之另一晶粒的一部分之一橫截面側視圖。
圖7係依據一實施例之圖6被切割之該晶粒的該部分之一橫截面側視圖。
圖8係依據一實施例之圖7嵌入在被附接至一暫時載體的一重組晶圓之該晶粒的該部分之一橫截面側視圖。
圖9係依據一實施例之帶有一介電層施加於圖8之該重組晶圓的該部分之一橫截面側視圖。
圖10係依據一實施例之圖9帶有一被形成的通孔之該重組晶圓的該部分之一橫截面側視圖。
圖11係依據一實施例之一晶粒在一帶有一保護層在該等襯墊之上的重組晶圓中的一橫截面側視圖。
圖12係依據一實施例之帶有支柱及一模具槽的一晶粒上之一橫截面側視圖。
圖13係依據一實施例之圖12在一模具已被閉合在該晶粒之上之後的該晶粒之一橫截面側視圖。
圖14係依據一實施例之圖13在移除該模具及一膜之後的該晶粒之一橫截面側視圖。
圖15係依據一實施例之一計算裝置併入一封裝晶粒之一方塊圖。
較佳實施例之詳細說明
在一晶粒及該RDL或封裝基板之間的該介電層之該厚度直接地有關於機械強度及RF性能。如果該介電質被製作得較薄，那麼該封裝體之該RF性能可藉由在該襯墊或重分佈金屬化層及該晶粒之間的該電容耦合而減少。為達成使用帶有一被減少厚度之一介電質的一特定線阻抗，該線寬也會需要被減少。因為製程限制，這經常是不可能的。而且，隨著小介電質厚度與被減少的線寬，寬度、厚度與阻抗之相對容許度係更加難以控制。與此同時，用於電源和接地接點之較大的金屬結構為所欲的。當前的製程方法需要對應的用於此等電源和接地接點之較厚的介電層。典型地被使用於WLB之在該等介電材料中被電鍍或被填滿的開口之直徑係藉由該介電層之厚度所決定。照慣例，一較高的介電質厚度需要一較大的開口。這是因為在該開口之直徑與該通孔之深度之間的縱橫比係藉由用於微影製程之該介電質的光影像組件或藉由用於雷射鑽孔之雷射的能力所限制。另一方面，該等較大的金屬結構具有增大的電容耦合其減少封裝體之RF性能。
在該RDL堆疊內的結構之間以及在此等結構及 該晶粒之間對於該電容耦合的一重要貢獻，其來自該等通孔及來自該等晶粒襯墊以及藉由這些通孔所連接之該等RDL襯墊。非常小的通孔產生較小的電容耦合。再者，較小的通孔直徑允許在該晶粒上及該RDL內有較小的襯墊直徑。較小的襯墊進一步減小電容耦合。減小的通孔及襯墊尺寸也允許一增加的佈線密度。對於訊號連接，一較小的通孔可被使用。另一方面，一特定電流攜帶能力時常被使用於電源和接地連接。這些通孔可為較大的且於此可被參照作為具有標準襯墊尺寸及通孔直徑。
該等通孔之深度可藉由應用一支柱至一晶粒襯墊或其他襯墊表面在不影響該介電層之厚度下被減少。該支柱允許在該RDL上之一襯墊至該晶粒上的一襯墊之間的一通孔為非常小的，因為該通孔僅延伸在該支柱及該RDL襯墊之間。這是在該等支柱之位置的一較淺的深度。與此同時，用於電力及接地連接之大的通孔，沒有支柱或帶有非常短的支柱可被製作在較大襯墊上用於較高的電流容量。厚的介電質及窄的通孔改善用於扇入及扇出形式兩者的WLB封裝體以及用於其他封裝體之RF性能。
如本文所描述的，支柱僅可被使用於將具有小直徑的那些通孔或者支柱可被使用於所有襯墊或用於不同形式的一些襯墊。在小襯墊上的該等支柱允許通孔藉由減少通孔之深度來維持一合適的縱橫比。其他帶有較大的直徑與較大的介電質厚度之通孔可藉由省略支柱而以相同縱橫比的方式被平行製造。較大的通孔可被使用於電力及用 於接地連接等等。由於該支柱，該通孔所需之深度是更少的。該支柱允許對於小的和大的通孔直徑之一固定的縱橫比可被維持。這改善製造可行性。該等大的通孔也可使用支柱來製造。然而，要謹慎以對以確保該等支柱的機械應力作用在該等晶粒襯墊上不會損害該等晶粒襯墊。
圖1係已被形成在一晶圓上的一半導體晶粒102之一部分的一橫截面側視圖。雖然為了簡化，僅一單一晶粒的一部分被顯示，但該晶圓將含有更多晶粒。該晶粒102含有任何所欲形式的邏輯、RF、電力或光學電路(未顯示)或其等之一些組合。該晶粒之該前側110具有不同尺寸的連接襯墊104、106。各個連接襯墊之尺寸可藉由該連接襯墊所必須攜帶的電流總額來決定，但也可藉由其他因素所決定，諸如該晶粒之該電路內的連接。該晶粒之該後側係該晶圓之一部分(未顯示)。
一支柱108被形成在該等小襯墊之每一個上。該等支柱由諸如銅或鎳之一傳導材料所形成，但任何其他合適的電氣傳導材料可被使用。在一範例中，如氮化鈦之一保護層被施加於該等晶片襯墊之表面。一晶種層隨後被形成在整個晶圓表面之上。一光阻層隨後被施加並圖案化用以曝露出藉由電鍍所形成之該等小襯墊及該等支柱。在該光阻被移除之後，該晶種層被蝕刻掉而圖1之結構餘留。該支柱直徑可被選擇足夠小使得該支柱可被完全地放置於該襯墊內。這導致當該晶種層及光阻被蝕刻掉時該襯墊被部分地曝露出。因此一保護層被施加用以防止對於該襯墊 的損傷。在最後的堆疊中，該保護層將該支柱自該晶粒襯墊分離。因此該保護層被選擇為具有傳導性的。
圖2係圖1之該晶粒的該部分在一介電層112已被施加在該等襯墊及該等支柱之上之後的一橫截面側視圖。該介電層機械地保護該晶粒表面且功能作為在該晶粒及該板之間的應力緩衝。該介電層也定義在該晶粒之該等功能性的金屬結構之間的一間隙(未顯示)，其在電路內被形成在該晶粒的該前側及在圖4中所顯示的該等重分佈層之上。該介電層也定義在重分佈層及該晶粒基板之間的距離。因此該介電質之一特定最小的厚度可被使用。
如果該介電層之厚度被減少，則封裝體性能會被影響。第一，該介電層會較不能夠緩衝機械的應力，其會減少板層級可靠度。對於WLB及eWLB封裝體，該介電層被使用作為一結構性的組件因而較弱的介電層可允許致命性故障。第二，在該重分佈層及該晶粒或該晶粒結構之該等金屬結構之間的距離會被減少，其會導致對於該封裝體之降低的電子性能，特別在高頻率的情況下。
圖3係圖2之該晶粒的該部分在通孔已被形成後的一橫截面側視圖。該等通孔可以任何所欲的方式被形成。作為一範例，該介電材料可為一可光結構化的材料。一些可光結構化的材料採用光感高分子介電材料之形態，諸如環氧樹脂、聚醯亞胺、苯環丁烯或聚苯並噁唑等等。此介電材料作為像是一光阻用以形成開口，但在該等通孔開口被形成及電鍍後不會被移除。在該等連接襯墊104、106 之上的通孔開口可藉由微影製程而被產生。通常一好的通孔定義僅可被實現取決於該等通孔之一特定縱橫比(高度對直徑的比例)。對於任何給定的介電層深度，該縱橫比將需要一最小的通孔直徑。特殊的最大縱橫比隨使用的材料及該等程序而定。
如所顯示的，該等寬連接襯墊104允許一深通孔116自該介電質之頂部延伸至在該介電質之底部的該襯墊。另一方面，用於該等較小襯墊106之該等開口係不足夠寬的以允許該通孔120向下到達該介電質之該底面。由於該等支柱，較窄的通孔僅需要向下到達該支柱以連接至該等較小的襯墊。結果，大的及小的通孔之該等縱橫比可大約相等。假若各個通孔係為足夠寬的或大的以達到所欲深度，則該等縱橫比也可十分不同。
在該等通孔已被形成之後，傳導佈線層122被形成在該介電質及該等通孔之上以製造在通孔及襯墊之間任何所欲的連接。額外的介電質及佈線層可被形成用以形成一多層重分佈層以及任何其他所欲的結構。該等佈線層可藉由淺通孔通過如所欲的各個介電層而被連接。一多層RDL堆疊內之層間的連接也可由帶有如所述的用於連接至該晶片的一通孔之一支柱所構成。填充該等孔洞之傳導材料可為組成該RDL之該等層的相同材料且其可以與該等支柱所形成之相同方式被施加。或者，該等支柱、該等傳導層及該等通孔可藉由各種不同的程序之任一者所產生，該等程序可為相同或彼此不同。在一些實施例中，一晶種層 被沉積在該晶粒之上。一光阻層被沉積在該晶種層之上，且隨後藉由曝光及蝕刻而被圖形化。在該光阻中之該等開口被電鍍，且隨後該光阻及晶種層被蝕刻掉。
圖4係圖3之該晶粒的該部分在該重分佈層被形成後的一橫截面側視圖。一焊料終止層124被形成在該晶粒之上及被圖形化以創造開口126曝露出在該重分佈層中之襯墊。在圖5中，焊料球被沉積在這些開口中且被附接至該等被曝露出的RDL襯墊。該等晶粒各者可自該晶圓被切割或單離(singulated)，且任何額外的處理或加工可被施加用以完成各晶粒。
圖6係在一晶圓上之一晶粒的一部分其類似於圖1之該晶粒的一橫截面圖。在此範例中，一eWLB(嵌入式晶圓級球狀柵陣列)處理程序被顯示。在一eWLB處理程序中，該等晶粒係首先被單離且隨後被嵌入一模具運載架中。該RDL被施加至該等晶粒及周圍的模複合物區域。隨後由晶粒所組成之該等封裝體及周圍的模複合物藉由鋸開重組的晶圓被彼此分離。這被顯示在下面一組圖中。對於一eWLB封裝體的該RDL可用如上所示關於該WLB封裝體之傳導支柱技術的相同方式得到益處。
在圖6中，一晶粒202之一部分被顯示製造在一矽基板(未顯示)上。該晶粒具有內部電路被形成在其類似於圖1之前側210上。該電路裝設有外部連接襯墊，其中一些204在直徑上係寬或大的而其中一些206在直徑上係窄或小的。如在每個所例示的範例中，該等晶粒襯墊被討論視為 圓形的，但可採用任何合適的形狀隨電路的形式及要被使用的RDL設計而定。一支柱208被形成在該等小襯墊之上。
該支柱被顯示具有僅略微小於該襯墊的一尺寸，然而，該支柱可較小或較大於該襯墊。該支柱可具有像是該襯墊之一圓的橫截面或任何其他合適的橫截面。該支柱如所顯示的具有大約該介電層之一半高度。然而該支柱之高度可被採取適合於任何特殊設計。其係藉由在該電鍍光阻中之開口的最大縱橫比所限制。在該等被敘述的範例中，該等支柱及該等通孔被以一類似的縱橫比所形成，然而，這並非必須的。如該等圖式之範例中所顯示的，該支柱係大約與該通孔相同高度。這允許該支柱及該通孔之傳導路徑以該支柱或該通孔任何一者單獨的該縱橫比之兩倍而被形成。換句話說，在這些範例中，最後包括該支柱的傳導路徑為一半的寬度或對於該通孔單獨的製造程序所允許之兩倍的高或長。該等支柱的尺寸、該等開口及該結構之其他形態可被修改以獲得不同的縱橫比及相對於全體通孔不同的支柱數量。或者，對於一較長的路徑，能夠有一較高縱橫比之一電鍍光阻可被使用。支柱也可被堆疊，亦即一第二支柱可被形成在該第一支柱之上。這是可在該第一光阻被移除之前被完成的。
圖7係圖6之該晶粒的該部分在其中該晶圓已被鋸開之一橫截面圖。該晶圓係藉由鋸開或任何其他所欲的方式被切開以自該一晶圓來形成許多小晶粒。這係藉由鋸口線212所表示。
圖8係兩個單離的晶粒202、203之一橫截面側視圖。這些已被以該前側210接觸該帶之方式壓入一釋放帶220中。該釋放帶已被附接至一暫時載體222以攜帶該等晶粒及維持它們對於彼此之相對位置。該等支柱被壓入該釋放帶中，但該等支柱並不夠長以致於會干擾在該帶上的該等晶粒之附著或位置。一旦該等晶粒被保持進入該帶上的位置則被覆蓋於一模複合物224中。在此範例中，該模複合物覆蓋該等晶粒且也在該等晶粒之間以牢固地保持該等晶粒在適當位置。
圖9係圖6之該晶粒在該模複合物已被硬化後的一橫截面側視。該釋放帶220被釋放且該暫時載體222被移除。該等晶粒藉由該模複合物保持在適當位置。儘管只有一個晶粒202被顯示，有更多晶粒可以被同時處理。類似於圖2之處理程序，一介電層226被施加在該等晶粒之被曝露出的前側210，以及周圍的該模複合物表面之上。
如本文所描述的，圖10係圖9之該晶粒在開口已藉由微影技術於可光結構化的介電質中被形成後的一橫截面側視。或者，該等開口可以任何其他所欲的方式被形成。
在該等開口被形成在該介電質中之後，該介電質可用如前面所描述的相同方式被處理。該RDL被沉積且該等通孔於同一步驟被填充。視特定的實施方式而定，更多層的RDL可被形成。一結構化的焊料終止層如同圖4被沉積且被圖案化以形成如同圖5的一焊料球狀柵。該等晶粒隨後藉由鋸開或切開穿過該RDL及模複合物來分離彼此用以獲 得獨立的晶粒封裝體。
於此所描述的該等支柱已如上所示被施加於在圖1中的一扇入晶圓級封裝體並且也被施加於一扇出晶圓級封裝體，例如在圖6中的一eWLB封裝體。在一eWLB封裝體的情況中，支柱可在切割之前被施加在該矽晶圓上或在該RDL製造程序之一第一步驟中被施加在該重組的晶圓上。當該等支柱被施加於該矽晶圓上，該等襯墊之相對位置相較於在該重組晶圓上被更精準地控制。精準的支柱定位是重要的用以對準該等通孔且允許在該晶粒表面上較小的直徑襯墊。
在圖8中，當該等晶粒被單離且封裝，也被稱為重組，該等晶粒可在位置上移動。於此晶粒移動中，該晶粒從其在該原始矽晶圓中的標稱位置移開至在該重組的模複合晶圓中的一不同位置。這可導致關於準確地定位一支柱在一襯墊上的問題。準確度對小襯墊以及當該等襯墊係靠近在一起時係特別重要的。在該等支柱被施加在一矽晶圓等級上之後，在用於該重組之單離之前，該等晶粒可隨後被揀出且被放置於該模具運載架上的附著劑上。該等支柱被嵌入在該帶的附著劑中且因此不會被該處理程序不良地影響。
圖11顯示用於形成該等通孔開口之另一技術如何可被採納。圖11係該晶粒202被封裝在該模複合物224中之一橫截面側視圖。該介電層226已被施加。然而，在該介電層被施加前，各個連接襯墊以一保護材料230被電鍍。當 該等開口被形成的時候，該保護材料保護該等襯墊。作為一範例雷射剝蝕可被使用以形成該等通孔，然而，該等薄襯墊可能被損傷。當該介電質被剝蝕的時候，一保護材料層將提供一額外的犧牲屏蔽以對抗該雷射。
該保護材料可在形成如在圖1及圖6中之該等支柱時被同時施加。該材料可為與該等支柱相同之材料，諸如銅。這允許該保護材料以沒有增加一額外的程序步驟而被形成。由於在電鍍期間打入較高的電流密度在該等較小的襯墊，在該等較寬的襯墊上之該等支柱通常具有較小高度。儘管該等較短的支柱於該等較寬的襯墊上可能不需要用於形成該等通孔，它們也不會危害該處理程序且可在該等襯墊及該等通孔之間提供一較佳的電氣連接。
如所顯示的，以一面板為基礎的(panel-based)或其他類似的技術之一雷射可被用來打開該等通孔。在這情況中，該等大的通孔襯墊也可以一支柱來覆蓋。該等支柱保護該等晶片襯墊防止雷射剝蝕，亦即其作為用於藉由雷射之該通孔開口程序的一終止。這些大支柱的高度可小於用於小通孔襯墊之該等支柱。
該等支柱的釋放可以任何各種不同方式完成，其中該等支柱的頂側被製作為可接達至一重分佈層或其他電氣連接。在一些實施例中，該介電質的一全部領域之移除被施加於該晶粒或晶圓的整體表面之上直到該等支柱被曝露出。這移除可藉由電漿蝕刻、研磨、切割(例如以鑽石刀、高速切削)等等。這些移除程序相較於雷射及光微影程序用 於打開該等通孔可為較不昂貴的。
在其他實施例中，薄膜輔助的造模可被使用。在這實施例中一模複合物被使用作為一介電質覆蓋於帶有該等支柱的該晶粒之前側。它可被施加作為以液體形式或以粒狀形式的一薄片。
圖12係施加支柱至一晶粒之該頂部以使用一模複合物來建立通孔的一橫截面側視圖。一帶有積體電路或其他結構的晶粒已被形成在一矽基板302上。該等電路或其他結構具有外部連接經由多重傳導襯墊304。這些襯墊可具有不同尺寸且為了促進該等連接而被安排。對於至少一些該等襯墊，支柱306已被安置在該等襯墊之上。此外，一模複合物308已被施加在該晶粒之上。在這範例中，該模複合物係一液體其將被散布在該晶粒之上，然而，其他形式可被替代使用。一頂部模具槽312以一面向該晶粒的軟膜310所覆蓋。
圖13係圖12之該晶粒及模具槽在該模具槽已被閉合在該模複合物、該等支柱及該晶粒的該頂部之上之後的一橫截面側視。結果，當該膜被向下壓時該等支柱被向上壓穿過該模複合物進入該膜310。
圖14係隨著該模具槽被移除之該晶粒的一橫截面側視。在打開該模具槽312並移除該膜310後，該等支柱已被曝露在該模複合物上面。這在某種程度上發生是因為該等支柱如圖13中所顯示被壓入該膜。當該膜被移除時，該等支柱被曝露出。因此，不需要如圖9中的範例所示之一 獨立的通孔開口步驟。
該晶粒的處理可隨後持續以一重分佈層的產生及如前述用於其他晶粒形式的其他操作。該重分佈層可作為一範例藉由濺鍍一晶種層、施加並圖形化一電鍍光阻、電鍍傳導重分佈線、剝除該光阻以及蝕刻該晶種層而被製造。這可被重覆多次以建立如所欲一樣多的佈線層。該等佈線層可藉由短通孔而被連接。
儘管於本文所描述的該等範例係有關於WLB封裝體，類似的技術可被使用於各種其他形式的晶粒及封裝技術。支柱可被形成於一晶圓級或一晶粒級上的晶粒接點之上而不管晶圓或晶粒形式，且隨後一厚的介電質可被形成在如同本文所描述的該等接點及該等支柱之上使得通孔可被形成，其僅需要夠深以達到該等支柱即可。
圖15係依據一實施方式之一計算裝置100之一方塊圖。該計算裝置100收容一系統板2。該板2可包括許多組件，包括但不限於一處理器4及至少一通訊封裝體6。該通訊封裝體被耦接至一或多個天線16。該處理器4係物理地及電氣地耦接至該板2。至少一天線16係與一通訊封裝體6整合在一起且係物理地及電氣地經由該封裝體耦接至該板2。在一些實施方式中，任何一或多個該等組件、控制器、集線器或界面使用如上所述的穿矽通孔而被形成在晶粒上。
隨其應用而定，計算裝置100可包括其他可或不可被物理地及電氣地耦接至該板2的組件。這些其他組件包 括但不限於揮發性記憶體(例如，DRAM)8、非揮發性記憶體(例如，ROM)9、快閃記憶體(未顯示)、一圖形處理器12、一數位訊號處理器(未顯示)、一加密處理器(未顯示)、一晶片組14、一天線16、諸如一觸控螢幕顯示器之一顯示器18、一觸控螢幕控制器20、一電池22、一音訊編解碼器(未顯示)、一視訊編解碼器(未顯示)、一功率放大器24、一全球定位系統(GPS)裝置26、一羅盤28、一加速度計(未顯示)、一陀螺儀(未顯示)、一揚聲器30、一影像攝錄器32、以及一大容量儲存裝置(諸如硬碟機)10、光碟(CD)(未顯示)、數位多功能光碟(DVD)(未顯示)等等)。這些組件可被連接至該系統板2、安裝至該系統板或與該等其他組件的任一者合併。
任何這些組件的一或多者可被實行作為如同本文所描述的封裝半導體晶粒。此處所顯示的組件可被合併入一單一的積體電路晶粒或可被合併入一單一的封裝體。其他組件可被實行作為在一或多個封裝體中的多重晶粒。該等封裝體可直接地連接彼此或經由該系統板。
該通訊封裝體6致能用於資料的轉移出入該計算裝置100之無線及/或有線通訊。詞彙“無線”及其衍生詞可被使用來描述電路、裝置、系統、方法、技術、通訊通道等等，其可透過調變電磁輻射的使用經由一非固態介質傳遞資料。該詞並非暗示相關裝置不包含任何導線，雖然在一些實施例中它們是可能的。該通訊封裝體6可實行若干無線或有線標準或協定中之任一者，包括但不限於 Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其之乙太網路衍生物、以及任何其他被定名為3G、4G、5G、與更超越之無線及有線協定。該計算裝置100可包括複數個通訊封裝體6。舉例來說，一第一通訊封裝體6可被專用於較短範圍的無線通訊，諸如Wi-Fi與藍芽，以及一第二通訊封裝體6可被專用於較長範圍的無線通訊諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、以及其他。
該計算裝置100之處理器4包括一積體電路晶粒被封裝在該處理器4之內。詞彙“處理器”可意指任何裝置或一裝置的部分其處理來自暫存器及/或記憶體之電子資料用以轉換那個電子資料成為可被儲存在暫存器及/或記憶體中之其他電子資料。
在各種實施方式中，該計算裝置100可以是一膝上型電腦、小筆電、筆記型電腦、超輕薄筆電、智慧型電話、平板電腦、個人數位助理(PDA)、超級移動電腦、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位影像攝錄器、可攜帶型音樂播放器、或者數位錄影機。在進一步的實施方式中，該計算裝置100可以是一種穿戴式裝置，諸如一手表、眼鏡、耳機或健身裝置、用於物聯網之一節點或任何其他處理資料的電子裝置。
實施例可被實行作為一或多個記憶體晶片、控制器、CPU(中央處理單元)、使用一主機板互連的微晶片或積體電路、一特殊應用積體電路(ASIC)及/或一現場可程式閘陣列(FPGA)的一部份。
參照“一個實施例”、“一實施例”、“範例實施例”、“各種實施例”等等，表示如此描述的該(等)實施例可包括特別的特徵、結構或特性，但不是每個實施例都需要包括該等特別的特徵、結構或特性。進一步地，一些實施例可具有一些、所有或沒有所敘述用於其他實施例的該等特徵。
於以下敘述及請求項中，詞彙“耦接”與其衍生詞可被使用。“耦接”被使用以表示二或更多元件合作或彼此相互作用，但在他們之間可或不可具有介於其中的物理或電氣的組件。
如於請求項中所使用的，除非用別的方法具體指定，順序形容詞的使用“第一”、“第二”、“第三”等等用以描述一通用元件，僅表示相似元件的不同例子被參照，且不意圖暗示如此描述之該等元件必須為在時間上或空間上以一給定的序列、以順序或以任何其他方式。
該等圖式及先前敘述給了實施例的範例。熟習此技者將可領會到一或多個所敘述的元件很可能被合併入一單一的功能元件。或者，某些元件可被分開成為多功能元件。來自一實施例的元件可被附加於另一實施例。舉例來說，於本文所描述的處理順序可被改變且不限於本文所描 述的方式。此外，任何流程圖的動作不需要以所顯示的順序被實行；亦不需要做所有必須被執行的動作。而且，那些不隨其他動作而定的動作可被同時或與其他動作合併執行。實施例的範圍決不藉由這些特定的範例所限制。許多變異，無論是否明確地給定在說明書中，諸如在結構、尺寸以及材料使用上的不同都是有可能的。實施例的範圍係至少寬廣的像是藉由以下請求項所給定者。
以下的範例屬於進一步的實施例。不同實施例之各種特徵可用一些特徵被包括及其他被排除而被多樣地合併以適合各種不同的應用。一些實施例屬於包括在一半導體基板上形成複數個傳導連接襯墊之一方法以連接至被形成在該基板上的電路，在該等連接襯墊的一子集合之各個上形成一支柱，該等支柱係以一傳導材料所形成，在該半導體基板之上形成一介電層，其包括在該等連接襯墊及該等支柱之上，形成藉由移除直接在該等支柱之上的該介電層來形成孔洞，以一傳導材料填充被形成的該等孔洞，以及在各個被填充的孔洞之上形成一連接件。
在進一步的實施例中，該等支柱自該基板延伸至大約該介電層的一半之一高度。
在進一步的實施例中，該等支柱及被形成的該等孔洞具有一橫截面的表面區域以及該等支柱相較於該等孔洞具有一較大的橫截面的表面區域。
在進一步的實施例中，該等支柱的該傳導材料及填充該等孔洞的該傳導材料係相同的傳導材料。
在進一步的實施例中，該傳導材料為銅。
在進一步的實施例中，形成複數個傳導連接襯墊其包含形成具有一第一直徑之該等連接襯墊的該第一子集合以及具有一第二較大的直徑之該等連接襯墊的一第二子集合，且其中形成一支柱包含僅在連接襯墊之該第一子集合的該等襯墊上形成一支柱。
在進一步的實施例中，形成孔洞其包含使用一被圖形化的光阻及蝕刻在該等傳導連接襯墊之上的該介電層來形成孔洞。
在進一步的實施例中，形成孔洞其包含使用一可光結構化的介電質，曝露出在該等傳導連接襯墊之上的該介電質之一部分且移除該未被曝露出的介電質。
在進一步的實施例中，填充該等被形成的孔洞其包含電鍍銅進入該等孔洞。
在進一步的實施例中，形成複數個傳導連接襯墊其包含形成具有一第一直徑之該等連接襯墊的該第一子集合以及具有一第二較大的直徑之該等連接襯墊的一第二子集合，且其中形成一支柱包含在連接襯墊之該第一子集合和該第二子集合的該等襯墊上形成一支柱，且其中形成孔洞包含藉由雷射剝蝕形成孔洞。
進一步的實施例包括在形成該等支柱後切割該半導體基板以形成複數個晶粒，以及以該等支柱被曝露出的方式來嵌入複數個晶粒的至少一部分在一模複合物之中，且其中形成一介電層在嵌入後被執行。
在進一步的實施例中，嵌入進一步包含放置該等晶粒之該至少一部分在一帶上使得該等支柱被嵌入該帶，該帶被附接至一暫時載體，施加該模複合物在該等晶粒及該暫時載體之上且移除該帶及該暫時載體以曝露出該等支柱。
進一步的實施例包括當填充該等孔洞時在該介電層之上形成一重分佈層且其中形成一連接件包含形成一焊料球陣列。
在進一步的實施例中，形成孔洞包含濺鍍一晶種層在該介電質之上，沉積及圖案化一光阻在該晶種層之上，且其中填充該等孔洞包含電鍍在該被圖案化的光阻中的開口之上，剝除該光阻並蝕刻該晶種層。
在進一步的實施例中，形成孔洞包含減少在該等支柱之上且也在該整體基板之上的該介電質之高度以曝露出該等支柱。
在進一步的實施例中，減少包含施加一程序由研磨、拋光、切割及蝕刻之該集合所選擇。
在進一步的實施例中，形成一支柱其包含施加一保護層在連接襯墊之該子集合的各者之上，施加一晶種層在該半導體基板之上，以開口在連接襯墊之該子集合之上的方式來圖案化在該半導體基板之上的一光阻，用一傳導材料來電鍍該等開口用以形成該等支柱，以及移除被圖案化的該光阻。
一些實施例屬於一半導體裝置封裝體其包括在 一半導體基板上之複數個傳導連接襯墊用以連接至被形成在該基板上的電路，在該等連接襯墊之一子集合的各者上之一支柱，該等支柱係以一傳導材料所形成，在該半導體基板之上包括在該等連接襯墊及該等支柱之上的一介電層，在其不屬於該子集合中的各個連接襯墊之上及在該等連接襯墊之該子集合的各個支柱之上被填充的通孔，以及在各個被填充的通孔之上的一連接件。
在進一步的實施例中，該等支柱延伸由該基板至該介電層之大約一半的一高度。
在進一步的實施例中，該等支柱及該被形成的孔洞具有一橫截面表面區域且該等支柱具有一相較於該等孔洞較大的橫截面表面區域。
在進一步的實施例中，該等支柱的該傳導材料及該等通孔係為相同傳導材料。
在進一步的實施例中，該等連接襯墊之該第一子集合具有一第一直徑並且該等連接襯墊之一第二子集合具有一第二較大的直徑，以及該等支柱僅在連接襯墊之該第一子集合的該等襯墊上。
進一步的實施例包括在該介電層之上的一重分佈層且其中該等連接件包含一焊料球陣列。
一些屬於一系統的實施例其包括一系統板、一記憶體被連接至該系統板，以及一處理器被連接至該系統板且經由該系統板耦接至該記憶體，該處理器具有一半導體晶粒，其具有在一半導體基板上之複數傳導連接襯墊用以 連接至被形成在該基板上的電路、在該等連接襯墊之一子集合的各者上之一支柱，該等支柱係以一傳導材料所形成、在該半導體基板之上包括在該等連接襯墊及該等支柱之上的一介電層、在不屬於該子集合的各個連接襯墊之上且在該等連接襯墊之該子集合的各個支柱之上被填充的通孔，以及在各個被填充的通孔之上的一連接件。
在進一步的實施例中，該等支柱延伸自該基板至該介電層之大約一半的一高度。
在進一步的實施例中，該等連接襯墊之該第一子集合具有一第一直徑並且該等連接襯墊之一第二子集合具有一第二較大的直徑，以及該等支柱僅在連接襯墊之該第一子集合的該等襯墊上。
104:連接襯墊
106:連接襯墊
108:支柱
116:深通孔
120:通孔
122:傳導佈線層

Claims (20)

  1. 一種用以形成半導體裝置之方法，其包含：在一半導體基板上形成複數個傳導連接襯墊，以連接至形成在該基板上的電路；在該等連接襯墊之至少一者上形成一支柱，該支柱係以一傳導材料所形成；在該半導體基板之上包括在該等連接襯墊及該支柱之上形成一介電層；藉由移除直接在該支柱之上的該介電層來形成一孔洞，以曝露出帶有在至少一些該等傳導連接襯墊之間之剩餘的介電質之該支柱；以一傳導材料填充被形成的該孔洞以電氣地接觸該支柱；以及在帶有在至少一些該等傳導連接襯墊之間之剩餘的介電質之被填充的該孔洞之上形成一連接件。
  2. 如請求項1之用以形成半導體裝置之方法，其中該支柱延伸自該基板至該介電層之大約一半的一高度。
  3. 如請求項1之用以形成半導體裝置之方法，其中該支柱及被形成的該孔洞具有一橫截面的表面區域且該支柱具有一較大於該孔洞之橫截面的表面區域。
  4. 如請求項1之用以形成半導體裝置之方法，其中該支柱之該傳導材料及填充該孔洞之該傳導材料係相同的傳導材料。
  5. 如請求項1之用以形成半導體裝置之方法，其中該傳導材料為銅。
  6. 如請求項1之用以形成半導體裝置之方法，其中形成複數個傳導連接襯墊包含形成具有一第一直徑之該等連接襯墊的一第一子集合以及具有一第二較大的直徑之該等連接襯墊的一第二子集合，且其中形成一支柱包含僅在連接襯墊之該第一子集合的該等襯墊上形成一支柱。
  7. 如請求項6之用以形成半導體裝置之方法，其中形成孔洞包含使用一被圖案化的光阻及蝕刻在該等傳導連接襯墊之上的該介電層來形成孔洞。
  8. 如請求項6之用以形成半導體裝置之方法，其中形成孔洞包含使用一可光結構化的介電質，使在該等傳導連接襯墊之上的該介電質之一部分曝光，且移除未被曝光的該介電質。
  9. 如請求項1之用以形成半導體裝置之方法，其中形成複數個傳導連接襯墊包含形成具有一第一直徑之該等連接襯墊的一第一子集合以及具有一第二較大的直徑之該等連接襯墊的一第二子集合，且其中形成一支柱包含在連接襯墊之該第一子集合和該第二子集合的該等襯墊上形成一支柱，且其中形成孔洞包含藉由雷射剝蝕形成孔洞。
  10. 如請求項1之用以形成半導體裝置之方法，其進一步包含： 在形成該支柱後切割該半導體基板以形成複數個晶粒；以及以該支柱被曝露出的方式來嵌入該等複數個晶粒的至少一部分在一模複合物之中，且其中形成一介電層在嵌入後被執行。
  11. 如請求項10之用以形成半導體裝置之方法，其中嵌入進一步包含：放置該等晶粒之該至少一部分在一帶上使得該支柱被嵌入該帶，該帶被附接至一暫時載體；施加該模複合物在該等晶粒及該暫時載體之上；以及移除該帶及該暫時載體以曝露出該支柱。
  12. 如請求項1之用以形成半導體裝置之方法，其進一步包含當填充該孔洞時在該介電層之上形成一重分佈層且其中形成一連接件包含形成一焊料球陣列。
  13. 如請求項1之用以形成半導體裝置之方法，其中形成一孔洞包含減少在該支柱之上且也在該整體基板之上的該介電質之該高度以曝露出該支柱。
  14. 如請求項1之用以形成半導體裝置之方法，其中形成一支柱包含：施加一保護層在該等連接襯墊之一子集合的各者之上；施加一晶種層在該半導體基板之上；以開口在連接襯墊的該子集合之上的方式來圖案 化在該半導體基板之上的一光阻；用一傳導材料來電鍍該等開口以形成該等支柱；以及移除被圖案化的該光阻。
  15. 一種半導體裝置封裝體，其包含：一半導體基板，其具有形成在該半導體基板上之電路；在該半導體基板上之複數個傳導連接襯墊，以連接至該電路；在該等連接襯墊之一子集合的各者上之一支柱，該等支柱係以一傳導材料所形成；在該半導體基板之上包括在該等連接襯墊及該等支柱之上的一介電層；在不屬於該子集合的各個連接襯墊之上及在該等連接襯墊之該子集合的各個支柱之上被填充的通孔，其中在不屬於該子集合的各個連接襯墊不具有一相對應的支柱；以及在各個被填充的通孔之上的一連接件。
  16. 如請求項15之半導體裝置封裝體，其中該等連接襯墊之一第一子集合具有一第一直徑並且該等連接襯墊之一第二子集合具有一第二較大的直徑，以及該等支柱僅在連接襯墊之該第一子集合的該等襯墊上。
  17. 如請求項15之半導體裝置封裝體，進一步包含在該介電層之上，電氣地耦接至該等被填充的通孔的一重分佈 層，且其中該等連接件包含一焊料球陣列。
  18. 一種運算系統，其包含：一系統板；一記憶體，其被連接至該系統板；以及一處理器，其被連接至該系統板且經由該系統板耦接至該記憶體，該處理器具有一半導體晶粒，其具有：在一半導體基板上之複數個傳導連接襯墊，以連接至被形成在該基板上的電路；在該等連接襯墊之一子集合的各者上之一支柱，該等支柱係以一傳導材料所形成；在該半導體基板之上包括在該等連接襯墊及該等支柱之上的一介電層；在不屬於該子集合的各個連接襯墊之上且在該等連接襯墊之該子集合的各個支柱之上被填充的通孔；以及在各個被填充的通孔之上的一連接件。
  19. 如請求項18之運算系統，其中該等支柱延伸自該基板至該介電層之大約一半的一高度。
  20. 如請求項18之運算系統，其中該等連接襯墊之該第一子集合具有一第一直徑並且該等連接襯墊之一第二子集合具有一第二較大的直徑，以及該等支柱僅在連接襯墊之該第一子集合的該等襯墊上。
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