JP2018517281A - 半導体デバイスのための高アスペクト比を有する誘電体を通る導電性パス - Google Patents
半導体デバイスのための高アスペクト比を有する誘電体を通る導電性パス Download PDFInfo
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- JP2018517281A JP2018517281A JP2017552118A JP2017552118A JP2018517281A JP 2018517281 A JP2018517281 A JP 2018517281A JP 2017552118 A JP2017552118 A JP 2017552118A JP 2017552118 A JP2017552118 A JP 2017552118A JP 2018517281 A JP2018517281 A JP 2018517281A
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Abstract
Description
導電性接続パッドのサブセットの各々の上に、導電性材料から構成されるポストを形成する工程と、
接続パッドおよびポストの上を含む半導体基板の上に誘電体層を形成する工程と、
ポストの直上の誘電体層を除去することにより穴を形成する工程と、
形成された穴を導電性材料で充填する工程と、
各々の充填された穴の上にコネクタを形成する工程とを含む方法に関連する。
Claims (26)
- 半導体基板上に形成された回路に接続する複数の導電性接続パッドを前記半導体基板上に形成する段階と、
導電性材料から構成されるポストを、前記複数の導電性接続パッドのサブセットの各々の上に形成する段階と、
前記複数の導電性接続パッドおよび前記ポストの上を含む前記半導体基板の上に誘電体層を形成する段階と、
前記ポストの直上の前記誘電体層を除去することにより穴を形成する段階と、
形成された前記穴を導電性材料で充填する段階と、
各々の充填された穴上にコネクタを形成する段階と
を備える方法。 - 前記ポストは、前記半導体基板から前記誘電体層のおよそ半分の高さまで延伸する、
請求項1に記載の方法。 - 前記ポストおよび前記形成された穴は、断面積を有し、前記ポストは、前記穴より大きい断面積を有する、
請求項1または2に記載の方法。 - 前記ポストの前記導電性材料および前記穴を充填する前記導電性材料は、同じ導電性材料である、
請求項1から3のいずれか一項に記載の方法。 - 前記導電性材料は、銅である、
請求項1から4のいずれか一項に記載の方法。 - 複数の導電性接続パッドを形成する段階は、第1直径を有する前記複数の導電性接続パッドの第1の前記サブセットと、より大きい第2の直径を有する前記複数の導電性接続パッドの第2のサブセットとを形成する段階を有し、ポストを形成する段階は、前記複数の導電性接続パッドの第1の前記サブセットの前記複数の導電性接続パッド上にのみポストを形成する段階を有する、
請求項1から5のいずれか一項に記載の方法。 - 穴を形成する段階は、パターン化されたフォトレジストを用いて穴を形成する段階と、前記複数の導電性接続パッドの上の誘電体層をエッチングする段階とを有する、
請求項6に記載の方法。 - 穴を形成する段階は、光構造化可能な誘電体を用いて前記複数の導電性接続パッドの上の誘電体層の一部を露出する段階と、露出されない誘電体層を除去する段階とを有する、
請求項6に記載の方法。 - 前記形成された穴を充填する段階は、前記穴へ銅を電気めっきする段階を有する、
請求項8に記載の方法。 - 複数の導電性接続パッドを形成する段階は、第1直径を有する前記複数の導電性接続パッドの第1の前記サブセットと、より大きい第2の直径を有する前記複数の導電性接続パッドの第2のサブセットとを形成する段階を有し、
ポストを形成する段階は、前記複数の導電性接続パッドの第1の前記サブセットおよび前記第2のサブセットの前記複数の導電性接続パッド上にポストを形成する段階を有し、
穴を形成する段階は、レーザーアブレーションにより穴を形成する段階を有する、
請求項1から9のいずれか一項に記載の方法。 - 複数のダイを形成すべく、前記ポストを形成する段階後に半導体基板をダイシングする段階と、
前記複数のダイの少なくとも一部を前記ポストが露出された状態でモールド化合物に埋め込む段階と
をさらに備え、
誘電体層を形成する段階は、埋め込む段階後に実行される、
請求項1から10のいずれか一項に記載の方法。 - 埋め込む段階はさらに、
前記ポストが一時的なキャリアに取り付けられたテープに埋め込まれるように、前記テープ上に前記複数のダイの少なくとも一部を配置する段階と、
前記複数のダイおよび前記一時的なキャリアの上に前記モールド化合物を適用する段階と、
前記ポストを露出すべく、前記テープおよび前記一時的なキャリアを除去する段階と
を含む
請求項11に記載の方法。 - 前記穴を充填している間に前記誘電体層の上に再分配層を形成する段階をさらに備え、
コネクタを形成する段階は、半田ボールアレイを形成する段階を有する、
請求項1に記載の方法。 - 穴を形成する段階は、前記誘電体層の上にシード層をスパッタリングする段階と、前記シード層の上にフォトレジストを堆積しパターン化する段階とを有し、
前記穴を充填する段階は、パターン化された前記フォトレジストにおける開口部の上に電気めっきする段階と、前記フォトレジストを剥離する段階と、前記シード層をエッチングする段階と
を有する、
請求項1から13のいずれか一項に記載の方法。 - 穴を形成する段階は、前記ポストの上の前記ポスト、および前記半導体基板全体の上の前記ポストをも露出すべく、前記誘電体層の高さを低減する段階を有する、
請求項1から14のいずれか一項に記載の方法。 - 低減する段階は、グラインディング、ポリッシング、切断およびエッチングのセットから選択される処理を適用する段階を含む
請求項15に記載の方法。 - ポストを形成する段階は、
前記複数の導電性接続パッドのサブセットの各々の上に保護層を適用する段階と、
前記半導体基板の上にシード層を適用する段階と、
前記半導体基板の上のフォトレジストを前記複数の導電性接続パッドの前記サブセットの上の開口部でパターン化する段階と、
前記ポストを形成すべく、導電性材料で前記開口部を電気めっきする段階と、
前記パターン化されたフォトレジストを除去する段階と
を有する請求項1から16のいずれか一項に記載の方法。 - 半導体基板上に形成された回路に接続する前記半導体基板上の複数の導電性接続パッドと、
前記複数の導電性接続パッドのサブセットの各々の上の、導電性材料から構成されるポストと、
前記複数の導電性接続パッドおよび前記ポストの上を含む前記半導体基板の上の誘電体層と、
前記サブセットではない各々の接続パッドの上、および前記複数の導電性接続パッドの前記サブセットの各ポストの上の充填されたビアと、
各々の充填されたビアの上のコネクタと
を備える半導体デバイスパッケージ。 - 前記ポストは、前記半導体基板から前記誘電体層のおよそ半分の高さまで延伸する、
請求項18に記載の半導体デバイスパッケージ。 - 前記ポストおよび前記形成された穴は、断面積を有し、前記ポストは、前記穴より大きい断面積を有する、
請求項18または19に記載の半導体デバイスパッケージ。 - 前記ポストおよび前記ビアの前記導電性材料は、同じ導電性材料である、
請求項18から20のいずれか一項に記載の半導体デバイスパッケージ。 - 前記複数の導電性接続パッドの第1の前記サブセットは、第1直径を有し、前記複数の導電性接続パッドの第2のサブセットは、より大きい第2直径を有し、前記ポストは、前記複数の導電性接続パッドの前記第1のサブセットの前記複数の導電性接続パッド上にのみ存在する、
請求項18から21のいずれか一項に記載の半導体デバイスパッケージ。 - 前記誘電体層の上に再分配層をさらに備え、前記コネクタは、半田ボールアレイを有する、
請求項18から22のいずれか一項に記載の半導体デバイスパッケージ。 - システムボードと、
前記システムボードに接続されるメモリと、
前記システムボードに接続され、前記システムボードを介して前記メモリに連結されるプロセッサであって、
前記プロセッサは、
半導体基板上に形成された回路に接続する、前記半導体基板上の複数の導電性接続パッドを有する半導体ダイと、
前記複数の導電性接続パッドのサブセットの各々の上の、導電性材料から構成されるポストと、
前記複数の導電性接続パッドおよび前記ポストの上を含む前記半導体基板の上の誘電体層と、
前記サブセットではない各々の接続パッドの上、および前記複数の導電性接続パッドの前記サブセットの各ポストの上の充填されたビアと、
各々の充填されたビアの上のコネクタと
を有する、
システム。 - 前記ポストは、前記半導体基板から前記誘電体層のおよそ半分の高さまで延伸する、
請求項24に記載のシステム。 - 前記複数の導電性接続パッドの第1の前記サブセットは、第1直径を有し、前記複数の導電性接続パッドの第2のサブセットは、より大きい第2直径を有し、前記ポストは、複数の導電性接続パッドの第1の前記サブセットの前記複数の導電性接続パッド上にのみ存在する、
請求項24または25に記載のシステム。
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