CN111868925A - 芯片尺度薄3d管芯堆叠封装 - Google Patents

芯片尺度薄3d管芯堆叠封装 Download PDF

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Publication number
CN111868925A
CN111868925A CN201980021812.5A CN201980021812A CN111868925A CN 111868925 A CN111868925 A CN 111868925A CN 201980021812 A CN201980021812 A CN 201980021812A CN 111868925 A CN111868925 A CN 111868925A
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Prior art keywords
die
electronic package
package
zone
perimeter
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Inventor
R·桑克曼
S·贾内桑
B·韦德哈斯
T·瓦纳
L·克泽尔
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Intel Corp
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Intel Corp
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Publication of CN111868925A publication Critical patent/CN111868925A/zh
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Abstract

本文所公开的实施例包含一种包括堆叠管芯的电子封装。在一个实施例中，电子封装包括第一管芯，该第一管芯包括从第一管芯的第一表面延伸出的多个第一导电‎互连。在一个实施例中，第一管芯还包括禁用区带。在一个实施例中，电子封装还可以包括第二管芯。在一个实施例中，第二管芯完全位于第一管芯的禁用区带的‎周界内。在一个实施例中，第二管芯的第一表面‎面向第一管芯的第一表面。

Description

芯片尺度薄3D管芯堆叠封装
技术领域
本公开的实施例涉及电子封装，并且更特别地，涉及包括具有面对面管芯堆叠的3D堆叠的封装配置。
背景技术
为了提供增加的计算能力和/或功能，电子封装通常包括彼此通信耦合的多个管芯。例如，存储器管芯可以通信地耦合到处理器管芯。为了提供改进的形状因子，多个管芯通常被堆叠。
堆叠管芯的一个实例包括倒装芯片安装到封装基板的主管芯和形成于所述主管芯的背侧表面上方的堆叠管芯。堆叠管芯可以引线接合到封装基板。在这样的配置中，所述主管芯及所述堆叠管芯以背对背配置（即，每一管芯的具有有源器件的表面彼此背对）定向。引线接合增加了封装的Z高度，并增加了X-Y形状因子。
堆叠管芯的附加示例包括层叠封装（PoP）配置。在这样的配置中，主管芯可以是安装到第一封装基板的倒装芯片，并且堆叠管芯可以引线接合到第二封装基板。第二封装基板可以通过围绕主管芯的周界形成的导电柱电耦合到第一封装基板。在这样的配置中，所述主管芯及所述堆叠管芯以背对背配置定向。引线接合和额外的封装基板增加了封装的Z高度，并且对围绕第一封装的柱的需要增加了X-Y形状因子。
堆叠管芯的附加示例包括倒装芯片安装到封装基板的主管芯，其中堆叠管芯耦合到所述主管芯的背侧表面。在这样的配置中，主管芯可具有硅通孔（TSV）以提供从主管芯的有源表面到堆叠芯片的有源表面的电连接。在这样的配置中，所述主管芯及所述堆叠管芯以背对前配置（即，所述主管芯的所述背侧表面面向所述堆叠管芯的所述有源表面）定向。与引线接合的堆叠管芯和PoP配置相比，这样的配置提供了改进的Z高度和X-Y形状因子。然而，包含TSV显著增加了主管芯的成本和复杂性。
堆叠管芯的又一配置包括倒装芯片安装到封装基板的第一表面的主管芯，以及倒装芯片安装到封装基板的第二表面的堆叠管芯。与引线接合的堆叠管芯和PoP配置相比，这样的实施例改进了Z高度和X-Y形状因子。然而，将堆叠管芯安装到封装基板的第二表面需要在第二管芯所在的位置减少第二级互连的数量。
附图说明
图1A是根据一个实施例的具有第一管芯及与所述第一管芯呈面对面定向的多个堆叠管芯的电子封装的横截面图示。
图1B是根据一个实施例的图1A中的电子封装沿线B-B'的平面图图示。
图2是根据一个实施例的具有第一管芯及多个堆叠管芯的电子封装的横截面图示，其中封装基板包含腔。
图3是根据一个实施例的具有第一管芯和多个堆叠管芯的电子封装的横截面图示，其中封装基板包含通孔。
图4A是根据一个实施例的具有第一管芯和多个堆叠管芯的电子封装的横截面图示，其中电子封装是晶片级芯片尺度封装（WLCSP）。
图4B是根据一个实施例的在WLCSP中具有第一管芯和多个堆叠管芯的电子封装的横截面图示，其中堆叠管芯中的一个延伸出模制层。
图5A是根据一个实施例的在扇出封装中具有第一管芯和多个堆叠管芯的电子封装的横截面图示。
图5B是根据一个实施例的在扇出封装中具有第一管芯和多个堆叠管芯的电子封装的横截面图示，其中堆叠管芯之一延伸出模制层。
图5C是根据一个实施例的具有第一管芯及多个堆叠管芯的电子封装的横截面图示，其中所述堆叠管芯包括重分布层。
图6A是根据一个实施例的具有第一管芯及多个堆叠管芯的电子封装的横截面图示，其中所述堆叠管芯中的一个包含TSV。
图6B是根据附加实施例的具有第一管芯及多个堆叠管芯的电子封装的横截面图示，其中所述堆叠管芯中的一个包含TSV。
图6C是根据附加实施例的具有第一管芯及多个堆叠管芯的电子封装的横截面图示，其中所述堆叠管芯中的多于一个包含TSV。
图7A是根据一个实施例的晶片的平面图图示和晶片上的第一管芯的放大透视图。
图7B是根据一个实施例的用于将第二管芯安装到第一管芯上的过程的透视图。
图7C是根据一个实施例的用于将第三管芯安装到第一管芯上的过程的透视图。
图7D是根据一个实施例的图7C中的电子封装的横截面视图。
图8是根据一个实施例构建的计算设备的示意图。
具体实施方式
本文描述了具有堆叠管芯的电子封装和形成堆叠管芯封装的方法。在以下描述中，将使用本领域技术人员通常采用的术语来描述说明性实现的各个方面，以向本领域其他技术人员传达其工作的实质。然而，对于本领域技术人员来说，显然本发明可以仅利用所描述的方面中的一些来实施。为了解释的目的，阐述了具体的数字、材料和配置，以便提供对说明性实现的透彻理解。然而，对于本领域技术人员来说，显然可以在没有这些具体细节的情况下实施本发明。在其它实例中，省略或简化了公知的特征，以免混淆说明性实现。
各种操作将以最有助于理解本发明的方式依次描述为多个分立的操作，然而，描述的顺序不应被解释为暗示这些操作必须是顺序相关的。特别地，这些操作不需要以呈现的顺序来执行。
如上所述，朝向增加的功能性的驱动已经需要将多个管芯通信地耦合在一起。然而，这已经导致了这样的电子封装的形状因子的增加。因此，本文描述的实施例包括以面对面配置封装的多个管芯。如本文所使用的，面对面可以指第一管芯的有源表面被定向成使得它面向第二管芯的有源表面。
在一个实施例中，可以通过将管芯焊盘作为凸起放置在第一管芯的边缘上来实现面对面配置。第一管芯的内表面区域可以是禁用（keep out）区带。附加管芯可堆叠于所述禁用区带的周界内。可以用重分布层中的柱或导电特征形成从第一管芯到第二级互连的附接。因此，实施例允许倒装芯片配置、晶片级芯片尺度封装（WLCSP）配置、扇出配置等。
现在参考图1A，根据一个实施例，示出了电子封装100的横截面图示。在一个实施例中，电子封装100可以包括多个堆叠管芯。在一个实施例中，第一管芯110可以倒装芯片安装到封装基板170。第一管芯110的第一表面111可以被定向为使得第一表面111面向封装基板170。在一个实施例中，第一表面111可被称为第一管芯110的有源表面。例如，有源特征（例如，晶体管等）可以形成为接近第一管芯110的第一表面111。
在一个实施例中，封装基板170可以包括电耦合到第一管芯110的第二级互连（SLI） 172。在一个实施例中，第一管芯110可以通过导电柱112和焊料凸起113电耦合到封装基板170。在一个实施例中，导电柱112可从第一管芯110的第一表面111延伸出。在一个实施例中，导电柱112可具有足以允许一个或多个管芯堆叠在第一管芯110的第一表面111与封装基板170之间的高度H。例如，在图1A中，第二管芯120、第三管芯130及第四管芯140堆叠于第一管芯110与封装基板170之间。在一个实施例中，导电柱112可具有20μm或更大、50μm或更大、或100μm或更大的高度H。在一个实施例中，导电柱112可以是高纵横比导电柱。例如，导电柱112可以具有2:1或更大、3:1或更大、或5:1或更大的高度：宽度纵横比。在一个实施例中，导电柱112可以是任何合适的导电材料。例如，导电柱112可以是铜等。
在一个实施例中，堆叠在第一管芯110和封装基板170之间的一个或多个管芯可以与第一管芯110面对面的配置来定向。例如，在图1A所示的实施例中，第二管芯120、第三管芯130和第四管芯140与第一管芯110以面对面的配置定向。特别地，第二管芯120的第一表面121、第三管芯131的第一表面131和第四管芯的第一表面141均被定向为使得它们面向第一管芯的第一表面111。在一个实施例中，第一表面121、131及141可分别为芯片120、130及140的有源表面。
在一个实施例中，堆叠管芯可通过焊料凸起和/或导电柱电耦合到第一管芯110。在一个实施例中，第二管芯120通过焊料凸起123和/或铜柱（未示出）电耦合到第一管芯110。在一个实施例中，第三管芯130通过导电柱132及导电柱132上方的焊料凸起133电耦合到第一管芯110。在一个实施例中，第四管芯140通过导电柱142和导电柱142上方的焊料凸起143电耦合到第一管芯110。虽然导电柱在本文中是指形成管芯之间的互连，但应当理解，也可以使用任何合适的结构来克服管芯之间的距离。例如，导电柱可以用铜芯凸起等代替。
在一个实施例中，电子封装100还可以包括在多个管芯110、120、130、140周围以及在封装基板170之上形成的模制层160。例如，多个管芯110可以完全嵌入在模制层160内。然而，附加实施例可以包括暴露第一管芯110的部分（例如，第一管芯110的背侧表面）的模制层160。在一个实施例中，第一管芯110可以通过封装基板170电耦合到第二级互连（SLI）172。在一个实施例中，SLI 172可以是焊料凸起或任何其它SLI架构。
在一个实施例中，多个管芯可以具有任何功能。在一个特定实施例中，第一管芯110可以是处理器，并且第二管芯120、第三管芯130及第四管芯140中的一个或多个可以是存储器管芯。然而，根据实施例使用的面对面堆叠的管芯可以具有其他功能（例如，RF收发器、功率管理、图形处理等）。
现在参考图1B，根据一个实施例，示出了沿线B-B'的图1A的平面图图示。图1B示出实现多个管芯110、120、130及140的堆叠面对面配置的多个管芯的布局。
在所示的实施例中，第一管芯110的周界被表示为虚线。在一个实施例中，第一管芯110可以包括禁用区带115。在一个实施例中，多个导电柱112形成在禁用区带115的周界之外。例如，第一管芯110可以包括在禁用区带115之外的管芯焊盘，或者可以使用重分布层（RDL）来将管芯焊盘重新布线到禁用区带115之外。
在一个实施例中，所述一个或多个堆叠管芯（即，管芯120、130及140）可定位于第一管芯110的禁用区带115内。如本文所使用的，当管芯被称为定位在另一管芯的禁用区带内时，应当理解，管芯的相对定位是指它们在X-Y平面中的定位。
在一个实施例中，堆叠管芯120、130及140中的一个或多个可具有其自身的禁用区带。在一个或多个堆叠管芯中提供禁用区带允许每个管芯具有到第一管芯110的直接连接。因此，不需要硅通孔（TSV），且可降低成本。然而，如将在下文中更详细描述，实施例并不局限于不具有TSV的配置。
在一个实施例中，最靠近第一管芯110的堆叠管芯（即，第二管芯120）可不具有禁用区带。在一个实施例中，第三管芯130可具有禁用区带135。在一个实施例中，第二管芯120可定位于第三管芯130的禁用区带135的周界内。在所示的实施例中，第二管芯120不完全在第三管芯的禁用区带135内。例如，第二管芯120可不直接堆叠在第三管芯130上方。然而，实施例还可包含直接堆叠于第三管芯130上方的第二管芯120。在这样的实施例中，第二管芯120可完全在第三管芯的禁用区带135内。
在一个实施例中，第四管芯140可具有禁用区带145。在一个实施例中，第二管芯120和第三管芯130可定位于禁用区带145的周界内。在所示的实施例中，第二管芯120及第三管芯130完全在第四管芯140的禁用区带145内。然而，应当理解，第二管芯120及第三管芯130中的一个或两者可从第四管芯140偏移（即，不完全在第四管芯140上方），且因此可部分在禁用区带145外部。
现在参考图2，示出了根据附加实施例的电子封装200的横截面图示。在一个实施例中，除了封装基板270可以包括腔273之外，电子封装200可以大体上类似于上述电子封装100。在一个实施例中，腔273可以形成在第一管芯210的禁用区带的阴影中。这样，一个或多个堆叠管芯可以延伸到腔273中。例如，第四管芯240部分地设置在腔273中。腔273的形成允许Z高度减小、堆叠较厚管芯的能力和/或堆叠更多管芯的能力。
现在参考图3，根据附加实施例，示出了电子封装300的横截面图示。在一个实施例中，除了腔被完全延伸穿过封装基板370的通孔374代替之外，电子封装300可以大体上类似于上述电子封装200。通孔374的使用允许Z高度减小、堆叠较厚管芯的能力和/或堆叠更多管芯的能力。然而，应当理解，通孔374的使用可导致从封装基板的形成通孔374的区域中减少SLI 372的数目。
在图1A-3中，电子封装每个都包括导电柱以提供封装基板和第一管芯之间的电连接。然而，应当理解，根据本文所述的实施例，也可以使用其他封装架构来形成面对面堆叠的管芯。特别地，应当理解，可以使用任何合适的结构来克服第一管芯和封装基板之间的距离。例如，导电柱可以用铜芯凸起等代替。
现在参考图4A，根据一个实施例，示出了电子封装400的横截面图示。在一个实施例中，电子封装400可具有多个管芯，所述多个管芯以大体上类似于上文相对于图1A所描述的配置的面对面定向配置，除了第一管芯410通过RDL 480电耦合到SLI 472之外。在这样的一个实施例中，可以省略封装基板。例如，形成在RDL 480中的多个导电迹线482和通孔481可提供从第一管芯410到SLI 472的电连接。诸如图4A所示的电子封装400可以称为WLCSP。
现在参考图4B，根据附加实施例，示出了电子封装400的横截面图示。图4B中所示的电子封装400可与图4A中所示的电子封装400大体上相同，除了堆叠管芯中的一个或一个以上延伸超过RDL 480之外。例如，第四管芯440向外延伸超过RDL 480。特别地，第四管芯440的侧壁448和第二表面447可以被暴露。在这样的实施例中，可从RDL的其中暴露第四管芯440的区域中减少SLI 472的数量。在一个实施例中，第四管芯440的第二表面447可以具有足以允许安装到印刷电路板（PCB）（未示出）的相隔距离D。在一个实施例中，相隔距离D可以是SLI 472的节距和球直径的函数。在一个实施例中，相隔距离D可以大约为50μm或更大。
现在参考图5A，根据附加实施例，示出了电子封装500的横截面图示。在一个实施例中，电子封装500可以被称为扇出封装。例如，电子封装500可以包括在第一管芯510的覆盖区（footprint）之外的SLI 572。在一个实施例中，SLI 572可以以大体上类似于上文参照图4A所述的电子封装400的方式用形成在RDL 580中的迹线582和通孔581电耦合到第一管芯510。在一个实施例中，模制层570可形成在第一管芯510上方并与RDL 580接触。
现在参考图5B，根据附加实施例，示出了电子封装500的横截面图示。图5B中所示的电子封装500可与图5A中所示的电子封装500大体上相同，除了堆叠管芯中的一个或多个延伸超过RDL 580之外。例如，第四管芯540向外延伸超过RDL 580。特别地，第四管芯540的侧壁548和第二表面547可以被暴露。在这样的实施例中，可以从RDL的暴露第四管芯540的区域中减少SLI 572的数量。在一个实施例中，第四管芯540的第二表面547可以具有足以允许安装到印刷电路板（PCB）（未示出）的相隔距离D。在一个实施例中，相隔距离D可为SLI572的节距和球直径的函数。在一个实施例中，相隔距离D可以大约为50μm或更大。
虽然上文相对于图1A到5B描述的电子封装不包含具有TSV的管芯，但应理解，实施例并不局限于这样的配置。例如，实施例可包含包括TSV的一个或多个堆叠管芯。参照图6A-6C描述这样的实施例的示例。
现在参考图6A，根据一个实施例，示出了电子封装600的横截面图示。电子封装600可大体上类似于相对于图1A所描述的电子封装，除了堆叠管芯中的一个包括TSV 635之外。例如，第三管芯630可包含多个TSV 635。这样，由于可以通过第三管芯630形成到第一管芯的电连接，所以在第三管芯630下方的第四管芯640不需要具有禁用区带。
现在参考图5C，根据附加实施例，示出了电子器件封装500的横截面图示。图5C中的电子封装500可大体上类似于图5B中的电子封装500，除了第二管芯520、第三管芯530和第四管芯540可包括重分布层524/534/544之外。在一个实施例中，重分布层524/534/544可以包括迹线、通孔和/或焊盘。例如，RDL 524/534/544的使用允许管芯焊盘形成于管芯520/530/540上的任何位置处，而非仅沿着导电互连523/532/542下方的管芯的周界形成。虽然图5C中示出了重分布层524/534/544，但是应当理解，本文描述的任何其他实施例也可以包括在管芯中的一个或多个管芯上方的重分布层，以便提供管芯焊盘放置的改进的灵活性。
现在参考图6B，根据附加实施例，示出了电子封装600的横截面图示。在一个实施例中，电子封装600可以大体上类似于关于图6A描述的电子封装600，除了第四管芯640还可以包括直接到第一管芯610的电连接之外。例如，导电柱642和焊料凸起643可将第四管芯640电耦合到第一管芯610而无需穿过TSV 635。然而，应当理解，可以通过利用穿过第三管芯630的TSV 635来形成到第四管芯640的附加电连接。
现在参考图6C，根据附加实施例，示出了电子封装600的横截面图示。在一个实施例中，电子封装600可大体上类似于相对于图6A所描述的电子封装600，除了多个管芯包含TSV之外。例如，TSV 625可穿过第二管芯620而形成，且TSV 635可穿过第三管芯630而形成。在这样的实施例中，第四管芯640和第一管芯610之间的电连接可以由导电柱642A和焊料凸起643A来形成，而不穿过TSV 625和穿过连接到TSV 625的导电柱642B和焊料凸起643B。到第四管芯640的附加连接可由经由第三管芯630连接到TSV 635的焊料凸起643C来形成。
现在参考图7A-7C，一系列图示描述了根据一个实施例的可以用于形成诸如上述那些的电子封装的工艺。
现在参考图7A，示出了根据一个实施例的具有多个管芯710的晶片790的平面图图示。图7A还示出了根据一个实施例的形成在晶片790上的第一管芯710的放大透视图。
在一个实施例中，晶片790可以是任何合适的半导体晶片（例如，硅晶片、绝缘体上硅（SIO）、III-V半导体材料等）。在一个实施例中，如本领域所公知的，晶片790可以包括多个第一管芯710。例如，晶片790可以包括数百、数千、数万或更多的第一管芯710。
在一个实施例中，第一管芯710可以包括多个导电柱712。导电柱712可具有高度H，其适合于形成诸如以上描述的包括以面对面配置堆叠的多个管芯的电子封装。例如，高度H可为20μm或更大、50μm或更大、或100μm或更大。在一个实施例中，导电柱712可以是高纵横比柱。例如，导电柱的高度：宽度纵横比可以是2:1或更大、3:1或更大、5:1或更大、或10:1或更大。在一个实施例中，其它互连可以替代导电柱712。例如，导电柱可以用铜芯凸起等代替。
在一个实施例中，第一管芯710可以包括禁用区带715。在一个实施例中，导电柱712可以仅形成在禁用区带715的外部。这样，随后放置的管芯可以被定位在第一管芯710的禁用区带中。
现在参考图7B，示出了根据一个实施例的用于将第二管芯720安装到第一管芯710的过程的透视图。在一个实施例中，焊料凸起723可以形成在第二管芯720的第一表面721上。如箭头所示，第二管芯720可以安装到第一管芯710。特别地，第二管芯720的第一表面721可以被定向成使得其面向第一管芯710的第一表面711。在一个实施例中，第二管芯720可以完全安装在第一管芯710的禁用区带715内。
现在参考图7C，示出了根据一个实施例的用于将第三管芯730安装到第一管芯710的过程的透视图。在一个实施例中，第三管芯730可以包括多个导电柱732和禁用区带735。导电柱732可形成在禁用区带735的外部。第三管芯730的禁用区带735可以被确定尺寸，使得其在第三管芯730被安装到第一管芯710时覆盖第二管芯720，如箭头所示。在一个实施例中，第三管芯730的第一表面731可以被安装为使得第一表面731面向第一管芯710的第一表面711。
现在参考图7D，示出了根据一个实施例的在第一管芯710被安装到封装基板770之后的电子封装700的横截面图示。如图所示，第二管芯720靠近第一管芯710。第三管芯730可以通过第二管芯720与第一管芯710间隔开。在一个实施例中，第三管芯730的导电柱形成在第二管芯720的周界之外。然而，诸如以上更详细描述的配置的其它配置可以用类似的工艺来形成。
虽然参考图1A-7D提供了面对面堆叠管芯配置的特定示例，但是应当理解，也可以使用其他配置。例如，可使用较少数目的管芯、较多数目的管芯、在给定Z高度处的多于一个管芯、TSV的不同组合、导电柱的使用和/或RDL的使用来提供给定电子封装的期望功能和/或形状因子。
图8示出了根据本发明的一个实现的计算设备800。计算设备800容纳板802。板802可以包括多个部件，包括但不限于处理器804和至少一个通信芯片806。处理器804物理地和电气地耦合到板802。在一些实现中，至少一个通信芯片806还物理地和电气地耦合到板802。在另外的实现中，通信芯片806是处理器804的一部分。
这些其它部件包括但不限于易失性存储器（例如DRAM）、非易失性存储器（例如ROM）、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统（GPS）设备、罗盘、加速度计、陀螺仪、扬声器、相机和大容量存储设备（诸如硬盘驱动器、光盘（CD）、数字多功能盘（DVD）等）。
通信芯片806实现用于向和从计算设备800传输数据的无线通信。术语"无线"及其派生词可用于描述可通过使用调制电磁辐射经由非固态介质来传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并不意味着相关联的设备不包含任何导线，尽管在一些实施例中它们可能不包含。通信芯片806可以实现多种无线标准或协议中的任何一种，包括但不限于Wi-Fi（IEEE802.11族）、WiMAX（IEEE802.16族）、IEEE802.20、长期演进（LTE）、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生物、以及被指定为3G、4G、5G及以上的任何其它无线协议。计算设备800可以包括多个通信芯片806。例如，第一通信芯片806可以专用于诸如Wi-Fi和蓝牙的较短距离无线通信，并且第二通信芯片806可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等的较长距离无线通信。
计算设备800的处理器804包括封装在处理器804内的集成电路管芯。在本发明的一些实现中，根据本文所述的实施例，处理器的集成电路管芯可以以面对面配置通信地耦合到一个或多个堆叠管芯。术语"处理器"可以指处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可以存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的一部分。
通信芯片806还包括封装在通信芯片806内的集成电路管芯。根据本发明的另一个实现，根据本文所述的实施例，通信芯片的集成电路管芯可以以面对面配置通信地耦合到一个或多个堆叠管芯。
以上对本发明的所示实现的描述，包括摘要中所描述的，不是旨在穷举或将本发明限制为所公开的精确形式。虽然为了说明的目的，在此描述了本发明的具体实现和示例，但是如相关领域的技术人员应当理解的，在本发明的范围内各种等同修改是可能的。
根据以上详细描述，可以对本发明进行这些修改。在所附权利要求中使用的术语不应被解释为将本发明限制于在说明书和权利要求中公开的特定实现。相反，本发明的范围完全由所附权利要求确定，权利要求将根据权利要求解释的既定原则来进行解释。‎
示例1：一种电子封装，包括：第一管芯，其中，所述第一管芯包括从所述第一管芯的第一表面延伸出的多个第一导电‎互连，并且其中，‎所述第一管芯包括禁用区带；以及第二管芯，其中，第二管芯完全位于第一管芯的禁用区带的‎周界内，并且其中，第二管芯的‎第一表面面向第一管芯的第一表面。‎
示例2：根据示例1所述的电子封装，其中，所述导电互连具有大于所述第二管芯的厚度的‎高度。‎
示例3：根据示例1或示例2所述的电子封装，其中，所述导电互连具有3:1或更大的纵横比‎。‎
示例4：根据示例1至3所述的电子封装，其中，所述第二管芯通过焊料凸起电耦合至所述第一管芯‎。‎
示例5：根据示例1-4所述的电子封装，其中，第一管芯‎的第一表面包括有源器件，并且其中，第二管芯的第一表面包括有源器件。‎
示例6：根据示例1至5所述的电子封装，还包括第三管芯，其中，所述第三管芯完全在所述第一管芯的所述禁用区带‎的周界内，并且其中，所述第三管芯包括从所述第三管芯的第一表面延伸出的多个柱‎，其中，从所述第三管芯的第一表面延伸出的所述多个柱‎将所述第三管芯‎电耦合至所述第一管芯。‎
示例7：根据示例1至6所述的电子封装，其中，所述第二管芯位于‎所述第一管芯的所述第一表面与所述第三管芯的所述第一表面之间。‎
示例8：根据示例1至7所述的电子封装，其中，所述第三管芯包括禁用区带‎，并且其中，所述第二管芯位于所述第三‎管芯的所述禁用区带上方。‎
示例9：根据示例1至8所述的电子封装，其中，所述第二管芯完全位于所述第三管芯的所述禁用区带的周界内‎。‎
示例10：根据示例1到9所述的电子封装，其中，所述第二管芯的一部分‎位于所述第三管芯的所述禁用区带上方。‎
示例11：根据示例1至10所述的电子封装，还包括：封装基板，其通过所述多个导电互连电耦合到所述第一管芯‎。
示例12：根据示例1至11所述的电子封装，其中，所述封装基板包括在所述第一管芯的所述禁用区带的周界内的‎凹部。‎
示例13：根据示例1-12的电子封装，其中，所述封装基板包括‎在第一管芯的‎禁用区带的周界内完全穿过封装基板的开口。‎
示例14：根据示例1至13所述的电子封装，还包括第三管芯和第四‎管芯，其中所述第三管芯和所述第四管芯完全在所述第一管芯的‎禁用区带的周界内。‎
示例15：根据示例1至14所述的电子封装，其中，所述第二管芯、所述‎第三管芯和所述第四管芯中的至少一个包括穿基板通孔。‎
示例16：一种电子封装，包括：第一管芯，其中，所述第一管芯包括禁用区带；第二管芯，其中，所述第一管芯的第一表面面对‎所述第二管芯的第一表面，并且其中，所述第二管芯位于所述第一管芯的禁用区带‎的周界内；以及第三管芯，其中，所述第三管芯包括从所述第三管芯的第一表面延伸出的多个导电柱‎，并且其中，所述‎导电柱将所述第三管芯电耦合到所述第一管芯。
示例17：根据示例16所述的电子封装，其中，所述电子封装是晶片‎级芯片尺度（WLCS）封装。
示例18：根据示例16或示例17所述的电子封装，其中，所述电子封装是扇‎出封装。‎
示例19：根据示例16至18所述的电子封装，其中，所述第三管芯包括禁用区带，并且其中，所述第二管芯至少部分地位于所述第三管芯的禁用区带内。‎
示例20：根据示例16至19所述的电子封装，还包括在所述‎第一管芯上方的模制层，其中所述第二管芯和所述第三管芯嵌入在所述模制‎层内。‎
示例21：根据示例16至20所述的电子封装，其中，所述第三管芯完全嵌入‎在所述模制层内。‎
示例22：根据示例16至21所述的电子封装，其中，所述第三管芯至少‎部分地延伸出所述模制层，并且其中，所述第三管芯的底表面具有距下层印刷电路板（PCB）的‎相隔距离，所述相隔距离是‎大约50μm或更大。‎
示例23：一种计算机系统，包括：第一管芯；第二管芯，其通信地耦合到所述第一管芯，其中，所述第一管芯的第一‎表面面向所述第二管芯的第一表面；第三管芯，其中，所述第三管芯的第一表面面向‎所述第一管芯的第一表面，并且其中，所述第三管芯通过‎多个导电柱电耦合到所述第一管芯；以及多个第二级互连，其电耦合至第一管芯的第一‎表面，其中，第二管芯和第三管芯位于第一管芯的第一表面和第二级互连之间‎。‎
示例24：根据示例23所述的计算机系统，其中，所述多个第二级‎互连通过从所述第一管芯的‎第一表面延伸出的铜柱耦合到所述第一管芯。‎
示例25：根据示例23或示例24所述的计算机系统，其中，所述多个第二级‎互连通过重分布层中的通孔和迹线耦合到所述第一管芯。

Claims (25)

1.一种电子封装，包括：
第一管芯，其中，所述第一管芯包括从所述第一管芯的第一表面延伸出的多个第一导电互连，并且其中，所述第一管芯包括禁用区带；以及
第二管芯，其中，所述第二管芯完全位于所述第一管芯的所述禁用区带的周界内，并且其中，所述第二管芯的第一表面面向所述第一管芯的所述第一表面。
2.根据权利要求1所述的电子封装，其中，所述导电互连具有大于所述第二管芯的厚度的高度。
3.根据权利要求1或2所述的电子封装，其中，所述导电互连具有3:1或更大的纵横比。
4.根据权利要求1或2所述的电子封装，其中，所述第二管芯通过焊料凸起电耦合到所述第一管芯。
5.根据权利要求1或2所述的电子封装，其中，所述第一管芯的所述第一表面包括有源器件，并且其中，所述第二管芯的所述第一表面包括有源器件。
6.根据权利要求1或2所述的电子封装，还包括：
第三管芯，其中，所述第三管芯完全在所述第一管芯的所述禁用区带的周界内，并且其中，所述第三管芯包括从所述第三管芯的第一表面延伸出的多个柱，其中，从所述第三管芯的第一表面延伸出的所述多个柱将所述第三管芯电耦合到所述第一管芯。
7.根据权利要求6所述的电子封装，其中，所述第二管芯位于所述第一管芯的所述第一表面与所述第三管芯的所述第一表面之间。
8.根据权利要求7所述的电子封装，其中，所述第三管芯包括禁用区带，并且其中，所述第二管芯位于所述第三管芯的所述禁用区带上方。
9.根据权利要求8所述的电子封装，其中，所述第二管芯完全位于所述第三管芯的所述禁用区带的周界内。
10.根据权利要求8所述的电子封装，其中，所述第二管芯的一部分位于所述第三管芯的所述禁用区带上方。
11.根据权利要求1或2所述的电子封装，还包括：
封装基板，所述封装基板通过所述多个导电互连电耦合到所述第一管芯。
12.根据权利要求11所述的电子封装，其中，所述封装基板包括在所述第一管芯的所述禁用区带的所述周界内的凹部。
13.根据权利要求11所述的电子封装，其中，所述封装基板包括在所述第一管芯的所述禁用区带的所述周界内完全穿过所述封装基板的开口。
14.根据权利要求1或2所述的电子封装，还包括第三管芯及第四管芯，其中，所述第三管芯及所述第四管芯完全在所述第一管芯的所述禁用区带的周界内。
15.根据权利要求14所述的电子封装，其中，所述第二管芯、所述第三管芯及所述第四管芯中的至少一个包括穿基板通孔。
16.一种电子封装，包括：
第一管芯，其中，所述第一管芯包括禁用区带；
第二管芯，其中，所述第一管芯的第一表面面向所述第二管芯的第一表面，并且其中，所述第二管芯位于所述第一管芯的所述禁用区带的周界内；以及
第三管芯，其中，所述第三管芯包括从所述第三管芯的第一表面延伸出的多个导电柱，并且其中，所述导电柱将所述第三管芯电耦合至所述第一管芯。
17.根据权利要求16所述的电子封装，其中，所述电子封装是晶片级芯片尺度（WLCS）封装。
18.根据权利要求16或17所述的电子封装，其中，所述电子封装是扇出封装。
19.根据权利要求16或17所述的电子封装，其中，所述第三管芯包括禁用区带，并且其中，所述第二管芯至少部分地位于所述第三管芯的所述禁用区带内。
20.根据权利要求16或17所述的电子封装，还包括在所述第一管芯上方的模制层，其中，所述第二管芯和所述第三管芯被嵌入在所述模制层内。
21.根据权利要求20所述的电子封装，其中，所述第三管芯完全嵌入在所述模制层内。
22.根据权利要求20所述的电子封装，其中，所述第三管芯至少部分地延伸出所述模制层，并且其中，所述第三管芯的底部表面具有距下层印刷电路板（PCB）约50μm或更大的相隔距离。
23.一种计算机系统，包括：
第一管芯；
第二管芯，其通信地耦合到所述第一管芯，其中，所述第一管芯的第一表面面向所述第二管芯的第一表面；
第三管芯，其中，所述第三管芯的第一表面面向所述第一管芯的第一表面，并且其中，所述第三管芯通过多个导电柱电耦合至所述第一管芯；以及
电耦合至所述第一管芯的所述第一表面的多个第二级互连，其中，所述第二管芯和所述第三管芯位于所述第一管芯的所述第一表面与所述第二级互连之间。
24.根据权利要求23所述的计算机系统，其中，所述多个第二级互连通过从所述第一管芯的所述第一表面延伸出的铜柱来耦合至所述第一管芯。
25.根据权利要求23或24所述的计算机系统，其中，所述多个第二级互连通过重分布层中的通孔和迹线耦合至所述第一管芯。
CN201980021812.5A 2018-06-29 2019-05-07 芯片尺度薄3d管芯堆叠封装 Pending CN111868925A (zh)

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