CN111244060A - 半导体封装 - Google Patents
半导体封装 Download PDFInfo
- Publication number
- CN111244060A CN111244060A CN201911016086.6A CN201911016086A CN111244060A CN 111244060 A CN111244060 A CN 111244060A CN 201911016086 A CN201911016086 A CN 201911016086A CN 111244060 A CN111244060 A CN 111244060A
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- conductive
- redistribution layer
- circuit board
- layer structure
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Abstract
本发明实施例公开半导体封装及形成所述半导体封装的方法。所述半导体封装中的一者包括电路板结构、第一重布线层结构、多个第一结合元件、封装结构及多个第二结合元件。所述第一重布线层结构设置在所述电路板结构之上且电连接到所述电路板结构。所述第一结合元件设置在所述第一重布线层结构与所述电路板结构之间且电连接到所述第一重布线层结构及所述电路板结构。所述封装结构设置在所述第一重布线层结构之上且电连接到所述第一重布线层结构。所述第二结合元件设置在所述第一重布线层结构与所述封装结构之间且电连接到所述第一重布线层结构及所述封装结构。
Description
技术领域
本发明实施例涉及半导体封装。
背景技术
半导体封装用于各种电子应用,例如个人计算机、手机、数字相机及其他电子设备。就用于集成电路组件或半导体管芯的封装而言,一般将一个或多个芯片封装结合到电路载体(例如,系统板、印刷电路板等)以用于与其他外部器件或电子组件进行电连接。
近来,高性能计算(high-performance computing,HPC)已变得越来越流行并被广泛用于高级网络及服务器应用,尤其是用于需要高数据速率、增加带宽及降低延迟的人工智能(artificial intelligence,AI)相关产品。然而,随着包括HPC组件的封装大小越来越大,出现了更具挑战性的问题。
发明内容
本发明实施例的一种半导体封装包括电路板结构、第一重布线层结构、多个第一结合元件、封装结构及多个第二结合元件。所述第一重布线层结构设置在所述电路板结构之上且电连接到所述电路板结构。所述第一结合元件设置在所述第一重布线层结构与所述电路板结构之间且电连接到所述第一重布线层结构及所述电路板结构。所述封装结构设置在所述第一重布线层结构之上且电连接到所述第一重布线层结构。所述第二结合元件设置在所述第一重布线层结构与所述封装结构之间且电连接到所述第一重布线层结构及所述封装结构。
附图说明
结合附图阅读以下详细说明,会最好地理解本公开的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为论述清晰起见,可任意增大或减小各种特征的临界尺寸。
图1A到图1I是根据本公开一些示例性实施例的制作半导体封装的方法中的各个阶段的示意性剖视图。
图2是示出根据本公开一些实施例的半导体封装的示意性剖视图。
图3是示出根据本公开一些实施例的半导体封装的示意性剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然,这些仅为实例而不旨在进行限制。举例而言,以下说明中将第二特征形成在第一特征“之上”或第一特征“上”可包括其中第二特征与第一特征被形成为直接接触的实施例,且也可包括其中第二特征与第一特征之间可形成有附加特征、以使得所述第二特征与所述第一特征可能不直接接触的实施例。另外,本公开可在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简洁及清晰的目的,而并非自身表示所论述的各种实施例和/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“在...之下(beneath)”、“在...下面(below)”、“下部的(lower)”、“在…上(on)”、“在…之上(over)”、“上覆在…之上(overlying)”、“在...上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。装置可具有其他取向(旋转90度或处于其他取向),且本文中所用的空间相对性描述语可同样相应地进行解释。
另外,为易于说明,本文中可能使用例如“第一(first)”、“第二(second)”、“第三(third)”、“第四(fourth)”等用语来阐述图中所示相似的或不同的元件或特征,且可根据所述说明的存在的次序或上下文来互换地使用所述用语。
也可包括其他特征及工艺。举例而言,可包括测试结构以帮助对三维(threedimensional,3D)封装或三维集成电路(three dimensional integrated circuit,3DIC)器件进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试焊盘(test pad),以便能够对三维封装或3DIC进行测试、对探针和/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外,可将本文中所公开的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用,以提高良率并降低成本。
图1A到图1I是根据本公开一些示例性实施例的制作半导体封装的方法中的各个阶段的示意性剖视图。参照图1A,在载体C之上形成重布线层结构RDL1。在一些实施例中,载体C可为玻璃载体或用于承载半导体晶片或用于半导体封装制造方法的重构晶片的任何合适的载体。载体C的形状可为圆形、矩形或其他合适的形状。在一些实施例中,举例而言,重布线层结构RDL1可为扇出型重布线层结构。在一些实施例中,重布线层结构RDL1的形成可包括依序形成多个导电图案102、102a及多个介电层104,其中导电图案102、102a及介电层104交替地堆叠在载体C之上。在一些实施例中,导电图案102、102a可通过沉积以及之后的光刻及蚀刻工艺形成。在一些实施例中,使用最外导电图案102a(也被称为暴露出的导电图案102a或最顶部导电图案102a)作为导电端子,所述导电端子可包括用于球安装的多个导电柱及位于所述多个导电柱下方的多个球下金属(under-ball metallurgy,UBM)图案。在一些实施例中,举例而言,最外导电图案102a可为结合焊盘。在一些实施例中,导电图案102、102a可通过电镀或化学镀形成。在一些实施例中,导电图案102、102a包含金属,例如铝、钛、铜、镍、钨和/或其合金。在一些实施例中,介电层104通过合适的制作技术(例如旋转涂布、化学气相沉积(chemical vapor deposition,CVD)、等离子体增强化学气相沉积(plasma-enhanced chemical vapor deposition,PECVD)等)形成。在一些实施例中,介电层104的厚度介于5μm到50μm的范围内。在一些实施例中,介电层104的材料可为模制化合物、聚合物(例如聚酰亚胺、聚苯并恶唑(polybenzoxazole,PBO)或苯并环丁烯(benzocyclobutene,BCB))、氮化物(例如氮化硅)、氧化物(例如氧化硅)、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼硅酸盐玻璃(borosilicate glass,BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass,BPSG)、其组合等。在一些实施例中,由模制化合物制成的介电层104与由聚合物(并非模制化合物)制成的介电层104可交替地设置。在一些实施例中,举例而言,最底部介电层104由模制化合物制成,且最顶部介电层104由聚合物(其并非模制化合物)制成。在示例性实施例中,由聚酰亚胺制成的介电层104与由模制化合物制成的介电层104可交替地设置,其中最底部介电层104由模制化合物制成,且最顶部介电层104由聚酰亚胺制成。然而,本公开并非仅限于此。
在形成重布线层结构RDL1之后,在最外导电图案102a上形成多个结合元件106。在一些实施例中,结合元件106可为焊料区,例如焊料球或球栅阵列(ball grid array,BGA)连接件、金属柱等。结合元件106通过最外导电图案102a电连接到重布线层结构RDL1。在一些实施例中,结合元件106例如可通过安装工艺及回流工艺形成。在一些实施例中,举例而言,结合元件106的直径介于25μm到800μm的范围内。
参照图1B,通过结合元件106将电路板结构CBS结合到重布线层结构RDL1。在一些实施例中,尽管仅示出一个电路板结构CBS,然而可分别将多个电路板结构CBS结合到重布线层结构RDL1上。详细而言,重布线层结构RDL1可包括多个封装区,且电路板结构CBS分别结合到封装区。在一些实施例中,电路板结构CBS包括芯体层CL以及分别位于芯体层CL的两个表面上的第一构成层(first build-up layer)BL1及第二构成层BL2。在一些实施例中,芯体层CL包括芯体介电层CDL、芯体导电层108A及108B、导电盖110A及110B以及镀覆穿孔TH。在一些实施例中,芯体介电层CDL包含预浸体(其包含环氧树脂、树脂、二氧化硅填料和/或玻璃纤维)、味之素构成膜(Ajinomoto Buildup Film,ABF)、树脂涂布铜箔(resincoated copper foil,RCC)、聚酰亚胺、照片图像介电质(photo image dielectric,PID)、陶瓷芯体、玻璃芯体、模制化合物、其组合等。然而,本公开并非仅限于此,且也可使用其他介电材料。芯体介电层CDL可通过叠层工艺、涂布工艺等形成。芯体导电层108A及108B形成在芯体介电层CDL的相对侧上。在一些实施例中,芯体导电层108A及108B包含铜、金、钨、铝、银、金、其组合等。导电盖110A及110B分别位于芯体导电层108A及108B之上。在一些实施例中,举例而言,导电盖110A及110B包含铜或其他合适的导电材料。
在一些实施例中,镀覆穿孔TH设置在芯体介电层CDL中并穿透过芯体介电层CDL,芯体介电层CDL在芯体导电层108A与芯体导电层108B之间提供电连接。换句话说,镀覆穿孔TH在位于芯体介电层CDL的两个相对侧上的电路之间提供电路径。在一些实施例中,镀覆穿孔TH可衬有导电材料且填充有绝缘材料。在一些实施例中,形成镀覆穿孔TH的方法包括以下操作。首先,通过例如机械或激光钻孔、蚀刻或另一种合适的移除技术,在预定位置处形成穿孔(未示出)。可执行去垢处理(desmear treatment)以移除余留在穿孔中的残留物。随后,可利用一种或多种导电材料将穿孔镀覆至预定厚度,从而提供镀覆穿孔TH。举例而言,可利用电镀或化学镀来向穿孔镀覆铜。
在一些实施例中,芯体导电层108A及108B、导电盖110A及110B以及镀覆穿孔TH可通过以下步骤形成。首先,分别在芯体介电层CDL的两个相对的表面上形成第一导电材料(未示出)。接着,如之前所述,形成镀覆穿孔TH以穿透芯体介电层CDL,并在分别形成在芯体介电层CDL的两个表面上的第一导电材料之间提供电连接。此后,在芯体介电层CDL的相对的表面上的第一导电材料之上分别形成第二导电材料,其中第二导电材料可不同于第一导电材料。在一些实施例中,第一导电材料及第二导电材料可使用任何合适的方法(例如,化学气相沉积(chemical vapor deposition,CVD)溅射、印刷、镀覆等)形成。接着,可将第一导电材料与第二导电材料一起图案化以分别形成芯体导电层108A及108B以及导电盖110A及110B。在一些实施例中,可使用光刻工艺及蚀刻工艺或另一种合适的移除技术来部分地移除第一导电材料及第二导电材料。
在一些实施例中,第一构成层BL1及第二构成层BL2分别设置在芯体层CL的相对侧上。具体而言,第一构成层BL1形成在芯体层CL的芯体导电层108A之上,且第二构成层BL2形成在芯体层CL的芯体导电层108B之上。在一些实施例中,第一构成层BL1的形成可包括依序形成多个第一介电层112A及多个第一导电图案114A、115A,其中第一介电层112A及第一导电图案114A、115A交替地堆叠在芯体层CL的第一表面之上。相似地,第二构成层BL2的形成可包括依序形成多个第二介电层112B及多个第二导电图案114B、115B,其中第二介电层112B及第二导电图案114B、115B交替地堆叠在芯体层CL的第二表面之上。在一些实施例中,介电层112A、112B的材料可为ABF、预浸体、RCC、聚酰亚胺、PID、模制化合物、其组合等。在一些替代实施例中,芯体介电层CDL与第一介电层112A及第二介电层112B可由相同的材料制成。举例而言,芯体介电层CDL以及第一介电层112A及第二介电层112B的材料可为模制化合物,例如环氧模制化合物(epoxy molding compound,EMC)。介电层112A、112B可通过叠层工艺、涂布工艺等形成。尽管相对于第一构成层BL1及第二构成层BL2中的每一者而言仅示出三层导电图案及三层介电层,然而本公开的范围并非仅限于此。在其他实施例中,介电层112A、112B的数目及导电图案114A、114B、115A、115B的数目可根据设计要求进行调整。在一些实施例中,举例而言,芯体层CL的厚度介于30μm到2000μm的范围内。在一些实施例中,举例而言,介电层112A、112B的厚度介于5μm到50μm的范围内,且导电图案114A、114B、115A、115B的厚度介于2μm到50μm的范围内。在一些实施例中,举例而言,最外导电图案115A、115B的厚度可大于内部导电图案114A、114B的厚度。在一些实施例中,第一构成层BL1的层的总数目可总计达导电图案及介电层的总共0到8个层,且第二构成层BL2的层的总数目可总计达导电图案及介电层的总共0到8个层。换句话说,在一些替代实施例中,可省略第一构成层BL1及第二构成层BL2中的至少一者。在一些替代实施例中,可省略第一构成层BL1,且芯体层CL可通过结合元件106结合到重布线层结构RDL1。在一些实施例中,第一构成层BL1中的层的数目等于第二构成层BL2中的层的数目。作为另外一种选择,在一些实施例中,第一构成层BL1及第二构成层BL2的总数目可不同。在一些实施例中,电路板结构CBS中的第一构成层BL1及第二构成层BL2的层的总数目小于传统的电路板结构中的构成层的层的总数目(其可为28层到36层)。因此,在一些实例中,电路板结构CBS也可被称为半成品电路衬底或半成品电路载体。
在一些实施例中,第一构成层BL1的最外导电图案115A结合到结合元件106,以使电路板结构CBS与重布线层结构RDL1结合在一起。在一些实施例中,举例而言,执行回流工艺以将电路板结构CBS附接到重布线层结构RDL1之上的结合元件106上。在结合之后,电路板结构CBS通过结合元件106电连接到重布线层结构RDL1。
参照图1C,在将电路板结构CBS与重布线层结构RDL1结合在一起之后,绝缘材料116形成在载体C之上以包封电路板结构CBS。在一些实施例中,举例而言,绝缘材料116可为模制化合物、模制底部填充胶、聚合物(例如聚酰亚胺、聚苯并恶唑(PBO)或苯并环丁烯(BCB))、味之素构成膜(ABF)或其他合适的包封材料。在一些实施例中,绝缘材料116可通过模制工艺或其他合适的方法形成。在示例性实施例中,绝缘材料116通过包覆模制工艺(over-molding process)形成。在一些实施例中,绝缘材料116覆盖第二构成层BL2的最外导电图案115B及电路板结构CBS的侧壁。另外,绝缘材料116形成在第一构成层BL1的最外导电图案115A之间,且形成在结合元件106及最外导电图案102a的旁边。换句话说,电路板结构CBS嵌入绝缘材料116中。
参照图1D,移除绝缘材料116的一些部分,从而暴露出第二构成层BL2的最外导电图案115B并在最外导电图案115B之间形成绝缘图案118。在一些实施例中,可通过研磨工艺或平坦化工艺(例如化学机械抛光工艺)部分地移除绝缘材料116的顶部部分直到最外导电图案115B被暴露出。在一些实施例中,在研磨之后,余留的绝缘材料116的顶表面实质上与电路板结构CBS的顶表面齐平。也就是说,绝缘图案118的顶表面实质上与最外导电图案115B的顶表面共面。因此,最外导电图案115B的顶表面未被绝缘图案118覆盖。在一些实施例中,举例而言,最外导电图案115B的侧壁可接触绝缘图案118。在一些实施例中,举例而言,绝缘图案118可为绝缘柱。举例而言,绝缘图案118的厚度可介于7μm到80μm的范围内,且绝缘图案118的宽度可介于5μm到5000μm的范围内。
参照图1E,移除最外导电图案115B的一些部分,且最外导电图案115B的顶表面低于绝缘图案118的顶表面。在一些实施例中,可通过蚀刻工艺(例如软蚀刻工艺)部分地移除最外导电图案115B。另外,在蚀刻工艺之后,举例而言,可对最外导电图案115B的顶表面执行表面处理(例如有机可焊性防腐剂(organic solderability preservative,OSP)表面处理)。在一些实施例中,举例而言,在部分地移除之后,最外导电图案115B的厚度可介于5μm到30μm的范围内。在一些实施例中,如图1E所示,在相邻的绝缘图案118及相邻的绝缘图案118之间的最外导电图案115B之间形成开口120,且开口120暴露出最外导电图案115B。在一些实例中,开口120也可被称为导电端子的容纳空间或凹槽。在一些实施例中,举例而言,开口120可具有介于2μm到50μm范围内的深度(即,最外导电图案115B与绝缘图案118之间的高度差)以及介于400μm到700μm范围内的宽度。
参照图1F,将其之上具有电路板结构CBS的重布线层结构RDL1从载体C剥离并上下翻转。也就是说,移除载体C。接着,在重布线层结构RDL1之上形成多个结合元件126。在一些实施例中,在形成结合元件126之前,在重布线层结构RDL1上形成介电层122,且在介电层122中形成多个导电图案124以电连接重布线层结构RDL1。在一些实施例中,在重布线层结构RDL1的最外导电图案102a上形成介电层122,并介电层122暴露出重布线层结构RDL1的最外导电图案102a。在一些实施例中,介电层122的材料可为聚合物(例如聚酰亚胺、聚苯并恶唑(PBO)或苯并环丁烯(BCB))、氮化物(例如氮化硅)、氧化物(例如氧化硅)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺杂硼的磷硅酸盐玻璃(BPSG)、其组合等。在一些实施例中,介电层122可通过合适的制作技术(例如旋转涂布、化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)等)形成。在一些实施例中,举例而言,介电层122的材料可不同于重布线层结构RDL1的最外介电层104的材料。在示例性实施例中,最外介电层104可由模制化合物制成,且介电层122可由聚合物(例如聚酰亚胺)制成。然而,本公开并非仅限于此。在一些实施例中,使用导电图案124作为导电端子,所述导电端子可包括用于球安装的多个导电柱及位于所述多个导电柱下方的多个球下金属(UBM)图案。在一些实施例中,重布线层结构RDL1以及重布线层结构RDL1之上的介电层122及导电图案124可被统称为电路板结构CBS之上的重布线层结构。
在介电层122中形成导电图案124之后,结合元件126形成在导电图案124上并电连接到导电图案124。在一些实施例中,结合元件126可为焊料区(例如微凸块等)。结合元件126通过导电图案124电连接到重布线层结构RDL1。在一些实施例中,结合元件126可通过安装工艺及回流工艺形成。在一些实施例中,结合元件126的直径小于结合元件106的直径。在一些实施例中,举例而言,结合元件126之间的节距可为20μm到80μm,且结合元件126的直径可介于10μm到25μm之间。在导电图案124及结合元件126的形成期间,可保护电路板结构CBS的最外导电图案115B免受损坏。
参照图1G,在一些实施例中,执行划切工艺以沿着切割线将整个结构(至少切穿重布线层结构RDL1及介电层122)切割成用于半导体封装的各别的及单独的集成衬底100,如图1G所示。在一些实施例中,举例而言,切割线实质上是电路板结构CBS的侧壁的延长线。在一些实施例中,划切工艺是晶片划切工艺(包括机械刀片锯切或激光切割)。在一些实施例中,用于封装结构的集成衬底100可包括电路板结构CBS(即,半成品电路衬底)、重布线层结构(即,重布线层结构RDL1、导电图案124及介电层122)及电路板结构CBS的相对表面上的绝缘图案118以及重布线层结构的相对表面上的结合元件106、126。在一些实施例中,举例而言,集成衬底100具有高模量(modulus),例如介于15GPa到50GPa的范围内。
参照图1H,通过结合元件126将封装结构PKS结合到集成衬底100。在一些实施例中,封装结构PKS可包括系统芯片(System-On-Chip,SoC)封装、晶片上芯片(Chip-On-Wafer,CoW)封装、集成扇出型(Integrated-Fan-Out,InFO)封装、衬底上晶片上芯片(Chip-On-Wafer-On-Substrate,CoWoS)封装、其他三维集成电路(3DIC)封装等。在一些实施例中,封装结构PKS包括上面有多个连接件130的多个封装组件128A、128B、128C、用于包封封装组件128A、128B、128C的包封体136以及位于包封体136之上的重布线层结构RDL2。
在一些实施例中,封装组件128A、128B、128C中的每一者可为封装、器件管芯、管芯堆叠等。器件管芯可为高性能集成电路,例如系统芯片(SoC)管芯、中央处理器(CentralProcessing Unit,CPU)管芯、图形处理单元(Graphic Processing Unit,GPU)管芯、现场可编程门阵列(field-programmable gate array,FPGA)管芯、移动应用管芯、存储器管芯或管芯堆叠。在一些实施例中,存储器管芯可呈存储器立方体(例如高带宽存储器(HighBandwidth Memory,HBM)立方体)形式。封装组件128A、128B、128C可在各自的管芯中具有各自的半导体衬底(未示出)。在一些实施例中,半导体衬底的后表面是根据图1H所示取向面朝上的表面。封装组件128A、128B、128C还包括位于相应半导体衬底的前表面(例如,面朝下的表面)处的集成电路器件(例如有源器件,其包括例如晶体管(未示出))。在一些实施例中,封装组件128A、128B、128C可根据设计要求而具有相同或不同的大小和/或功能。在示例性实施例中的一者中,封装组件128A、128C可为存储器立方体,且封装组件128B可为CPU、GPU、FPGA或其他合适的高性能集成电路。在示例性实施例中,封装组件128A、128C可包括管芯堆叠132以及位于管芯堆叠132的底部处的控制器134。
在一些实施例中,可如图1I所示在包封体136中对封装组件128A、128B、128C的连接件130进行包封。作为另外一种选择,连接件130可设置在介电层(未示出)中,包封体136接着对介电层进行包封。在一些实施例中,重布线层结构RDL2设置在封装组件128A、128B、128C及包封体136之上并电连接到封装组件128A、128B、128C。在一些实施例中,举例而言,重布线层结构RDL2可为扇出型重布线层结构。重布线层结构RDL2可包括多个介电层138及多个导电图案140、140a,且介电层138及导电图案140、140a交替地堆叠在封装组件128A、128B、128C之上。在一些实施例中,使用最外导电图案140a作为导电端子,所述导电端子可包括用于球安装的多个导电柱及位于所述多个导电柱下方的多个球下金属(UBM)图案。在一些实施例中,在结合之后,可分配底部填充胶142来保护电路板结构CBS之上的封装结构PKS与重布线层结构之间的结合结构。在一些实施例中,从底部填充胶142的底部到封装结构PKS的顶部范围内的总厚度可介于50μm到1500μm的范围内。在一些实施例中,封装结构PKS是预先制作的,即,在结合到集成衬底100之前由包封体136包封封装组件128A、128B、128C。然而,本发明并非仅限于此。在一些替代实施例中,举例而言,可将封装组件128A、128B、128C结合到集成衬底100,且接着在集成衬底100之上形成包封体136以包封封装组件128A、128B、128C。
参照图1I,在形成封装结构PKS之后,在开口120中形成多个导电端子144,开口120暴露出第二构成层BL2的最外导电图案115B。导电端子144电连接到电路板结构CBS的第二构成层BL2中的最外导电图案115B。在一些实施例中,导电端子144可为球栅阵列(BGA)连接件、焊料球、金属柱等。在一些实施例中,导电端子144的节距可介于在500μm到1500μm的范围内。在一些实施例中,导电端子144可通过安装工艺及回流工艺形成。在一些实施例中,如图1I所示,开口120填充有导电端子144,且绝缘图案118的顶表面未被导电端子144覆盖。然而,本公开并非仅限于此。在一些替代实施例中,绝缘图案118的顶表面可被导电端子144部分地覆盖,同时导电端子144彼此隔开。作为另外一种选择,导电端子144未完全覆盖最外导电图案115B,且可在导电端子144与绝缘图案118之间形成间隙。在某些实施例中,导电端子144可用于安装到附加电子组件(例如,电路载体、系统板、母板等)上。
此时,半导体封装10被制作出。在一些实施例中,半导体封装10可具有等于70mm×70mm或100mm×100mm或更大的超大大小。在一些实施例中,半导体封装10包括电路板结构CBS、重布线层结构RDL1、介电层122中的导电图案124以及包括重布线层结构RDL2的封装结构PKS。在一些实施例中,首先形成重布线层结构RDL1,且接着将电路板结构CBS及封装结构PKS结合到重布线层结构RDL1的相对侧。因此,如图1I所示,重布线层结构RDL1的导电图案102、102a的配置不同于第一构成层BL1的导电图案114A、115A以及相邻的导电图案124的配置。详细而言,导电图案102、102a中的一些可具有成一体地形成的第一部分148a与第二部分148b,第一部分148a设置在第二部分148b与电路板结构CBS之间,且第二部分148b设置在第一部分148a与封装结构PKG之间。在一些实施例中,举例而言,第一部分148a可为线,且第二部分148b可为通孔。在一些实施例中,第二部分148b的宽度小于第一部分148a的宽度。在一些实施例中,导电图案102、102a的宽度可沿着从电路板结构CBS到封装结构PKG的方向D逐渐减小。换句话说,举例而言,导电图案102、102a可具有帽状横截面。
在一些实施例中,导电图案114A、115A及124中的一些具有成一体地形成的第一部分150a与第二部分150b,第一部分150a设置在第二部分150b与电路板结构CBS之间,且第二部分150b设置在第一部分150a与封装结构PKG之间。在一些实施例中,举例而言,第一部分150a可为线,且第二部分150b可为通孔。在一些实施例中,第二部分150b的宽度大于第一部分150a的宽度。换句话说,导电图案114A、115A、124的宽度可沿着从电路板结构CBS到封装结构PKG的方向D逐渐增大。在一些实施例中,导电图案114A、115A及124具有螺旋状横截面。换句话说,重布线层结构RDL1的导电图案102、102a及与导电图案102、102a相邻的导电图案114A、115A及124可具有倒置的轮廓。
为将电路板结构CBS及封装结构PKS分别结合到重布线层结构RDL1,将结合元件106及126设置在重布线层结构RDL1的相对侧上。详细而言,结合元件106设置在重布线层结构RDL1与电路板结构CBS之间且电连接到重布线层结构RDL1与电路板结构CBS,且结合元件126设置在重布线层结构RDL1与封装结构PKS之间且电连接到重布线层结构RDL1与封装结构PKS。在一些实施例中,每一结合元件126的直径小于每一结合元件106的直径,且每一结合元件106的直径小于每一导电端子144的直径。
在一些实施例中,如之前所述,绝缘材料116可通过包覆模制工艺形成。然而,本发明并非仅限于此。在一些替代实施例中,绝缘材料116可利用压靠在最外导电图案115B的顶表面上的释放膜来通过模具形成,且绝缘图案118可在移除模具及释放膜之后直接形成。换句话说,绝缘图案118可在不进行研磨工艺的情况下形成,且如图2所示半导体封装10A所示,举例而言,绝缘图案118的顶表面可因释放膜而呈盘形凹陷。
图3是根据本公开一些示例性实施例的半导体封装的示意性剖视图。图3中所示的半导体封装10B与图1I中所示的半导体封装10相似,因此使用相同的参考编号来指代相同及类似的部件,且在本文中将不再对其予以赘述。半导体封装10与半导体封装10B之间的差异在于绝缘图案118及绝缘图案118之间的导电图案115B的设计。举例而言,在图1I所示的实施例中,导电图案115B的最外表面从绝缘图案118的最外表面凹陷或相对于绝缘图案118的最外表面凹陷。然而,在图3所示的实施例中,导电图案115B的最外表面实质上与绝缘图案118的最外表面齐平,且导电图案115B的最外表面未被绝缘图案118覆盖。换句话说,可省略图1E所示部分地移除导电图案115B的步骤,且在最外导电图案115B上方不形成开口。在一些实施例中,导电图案115B的厚度可实质上与初始厚度相同。接着,在第二构成层BL2的最外导电图案115B的顶表面上形成导电端子144。
在一些实施例中,用于封装结构的衬底包括半成品电路衬底及重布线层结构。换句话说,与由芯体层及构成层制成的传统电路板相比,用于封装结构的衬底还包括重布线层结构,重布线层结构取代了构成层的一些部分。在一些实施例中,衬底的重布线层结构可在例如标准硅制作环境等环境中通过InFO工艺来制作。因此,衬底可以高良率来制作,且衬底可具有高模量、减小的厚度、低粗糙度和/或良好的电性能。因此,整个半导体封装的刚性、电感和/或电阻增强且成本降低。另外,半导体封装工艺适用于集成衬底上系统(systemon integrated substrate,SoIS)及系统晶片(system on wafer,SoW),且满足高性能计算结构的要求。另外,界定开口的绝缘图案可通过模制工艺由模制化合物形成,而不需要光刻工艺,且因此用于导电端子的开口的形成工艺简单且成本低。因此,用于制作半导体封装的复杂性及成本降低,且半导体封装的良率及性能提高。
根据本公开的一些实施例,一种半导体封装包括电路板结构、第一重布线层结构、多个第一结合元件、封装结构及多个第二结合元件。所述第一重布线层结构设置在所述电路板结构之上且电连接到所述电路板结构。所述第一结合元件设置在所述第一重布线层结构与所述电路板结构之间且电连接到所述第一重布线层结构及所述电路板结构。所述封装结构设置在所述第一重布线层结构之上且电连接到所述第一重布线层结构。所述第二结合元件设置在所述第一重布线层结构与所述封装结构之间且电连接到所述第一重布线层结构及所述封装结构。
在一些实施例中,所述第一结合元件及所述第二结合元件是焊料区。
在一些实施例中,所述第一结合元件中的每一者的直径大于所述第二结合元件中的每一者的直径。
在一些实施例中,所述半导体封装还包括位于所述电路板结构的与上面设置有所述第一重布线层结构的表面相对的表面上的多个导电端子,其中所述导电端子中的每一者的直径大于所述第一结合元件中的每一者的直径。
在一些实施例中,在所述第一结合元件之间设置有模制底部填充胶,且所述模制底部填充胶的侧壁实质上与所述第一重布线层结构的侧壁齐平。
在一些实施例中,所述第一重布线层结构包括导电图案,所述导电图案具有成一体地形成的第一部分与第二部分,且所述第一部分设置在所述第二部分与所述电路板结构之间并具有比所述第二部分的宽度大的宽度。
在一些实施例中,所述封装结构包括多个封装组件及第二重布线层结构,且所述第二重布线层结构设置在所述封装组件与所述第二结合元件之间并电连接到所述封装组件及所述第二结合元件。
根据本公开的替代实施例,一种半导体封装包括电路板结构、封装结构、多个绝缘图案及多个导电端子。所述电路板结构包括多个最外导电图案。所述封装结构位于所述电路板结构的第一侧之上。所述绝缘图案位于所述电路板结构的与所述电路板结构的所述第一侧相对的第二侧之上,其中所述多个最外导电图案与所述多个绝缘图案交替地设置,且所述最外导电图案不被所述绝缘图案覆盖。所述导电端子分别设置在所述最外导电图案上且电连接到所述最外导电图案。
在一些实施例中,所述绝缘图案的顶表面高于所述最外导电图案的顶表面。
在一些实施例中,所述最外导电图案中的一者相对于相邻的绝缘图案凹陷。
在一些实施例中,所述绝缘图案的顶表面实质上与所述最外导电图案的顶表面齐平。
在一些实施例中,所述绝缘图案的顶表面是呈盘形凹陷的。
在一些实施例中,所述最外导电图案中的每一者接触相邻的对应的绝缘图案。
在一些实施例中,所述绝缘图案包含模制化合物。
在一些实施例中,所述半导体封装还包括位于所述电路板结构与所述封装结构之间的重布线层结构。
根据本公开的又一些替代实施例,一种制造半导体封装的方法包括以下步骤。形成第一重布线层结构。将电路板结构的第一侧结合到所述第一重布线层结构,其中所述电路板结构包括位于第二侧上的多个最外导电图案。形成绝缘材料以包封所述电路板结构,其中所述绝缘材料包括设置在所述最外导电图案之间且暴露出所述最外导电图案的多个绝缘图案。移除所述最外导电图案的一些部分,其中所述最外导电图案的顶表面低于所述绝缘图案的顶表面。将封装结构结合到所述第一重布线层结构上。在所述最外导电图案上分别形成多个导电端子。
在一些实施例中,形成所述绝缘材料包括:将所述绝缘材料形成为包封所述最外导电图案的侧壁及所述顶表面;以及移除所述绝缘材料的一些部分,以形成所述绝缘图案且暴露出所述最外导电图案的所述顶表面,其中所述绝缘图案的所述顶表面实质上与所述最外导电图案的所述顶表面齐平。
在一些实施例中,移除所述最外导电图案的一些部分是通过蚀刻工艺执行的。
在一些实施例中,所述制造半导体封装的方法还包括:沿所述电路板结构的侧壁切割所述第一重布线层结构及所述绝缘材料。
在一些实施例中,所述制造半导体封装的方法还包括:在所述第一重布线层结构上形成多个结合元件,其中所述电路板结构通过所述结合元件结合到所述第一重布线层结构。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应知,他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本公开的精神及范围,而且他们可在不背离本公开的精神及范围的条件下对其作出各种改变、代替及变更。
Claims (1)
1.一种半导体封装,其特征在于,包括:
电路板结构;
第一重布线层结构,设置在所述电路板结构之上且电连接到所述电路板结构;
多个第一结合元件,设置在所述第一重布线层结构与所述电路板结构之间且电连接到所述第一重布线层结构及所述电路板结构;
封装结构,设置在所述第一重布线层结构之上且电连接到所述第一重布线层结构;以及
多个第二结合元件,设置在所述第一重布线层结构与所述封装结构之间且电连接到所述第一重布线层结构及所述封装结构。
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