CN107646140A - 用于形成封装结构中的沟槽的方法及由此形成的结构 - Google Patents

用于形成封装结构中的沟槽的方法及由此形成的结构 Download PDF

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CN107646140A
CN107646140A CN201680030244.1A CN201680030244A CN107646140A CN 107646140 A CN107646140 A CN 107646140A CN 201680030244 A CN201680030244 A CN 201680030244A CN 107646140 A CN107646140 A CN 107646140A
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China
Prior art keywords
substrate
die
groove opening
mold compound
interconnection
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N·S·亚格纳默西
费辉阳
P·马拉特卡尔
P·拉加万
R·尼克森
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Intel Corp
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Intel Corp
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Publication of CN107646140A publication Critical patent/CN107646140A/zh
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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    • B29C33/00—Moulds or cores; Details thereof or accessories therefor
    • B29C33/0033—Moulds or cores; Details thereof or accessories therefor constructed for making articles provided with holes
    • B—PERFORMING OPERATIONS; TRANSPORTING
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Abstract

描述了形成包括沟槽的封装结构的方法。实施例包括设置在第一衬底上的第一管芯和设置在第一衬底的外围区上的至少一个互连结构。模制化合物设置在第一衬底的一部分上和第一管芯上，其中沟槽开口设置在位于至少一个互连结构与第一管芯之间的模制化合物中。

Description

用于形成封装结构中的沟槽的方法及由此形成的结构
相关申请的交叉引用
本申请要求于2015年6月24日提交的、标题为“METHODS OF FORMING TRENCHES INPACKAGES STRUCTURES AND STRUCTURES FORMED THEREBY”的美国专利申请14/748,496的优先权。
背景技术
随着封装技术朝着增加最小化前进，可以使用形成模穿互连(TMI)结构的这样的技术，其中可以实现对两个单独封装的管芯的集成以形成较大的整体封装。例如，在堆叠式封装(PoP)结构中，第一封装管芯可以通过使用两个封装管芯之间的焊球连接来与第二封装管芯耦合，焊球连接位于TMI开口内。
附图说明
虽然说明书以特别指出并清楚主张某些实施例的权利要求结束，当结合附图阅读时，可以根据本发明的以下描述更容易确定这些实施例的优点，在附图中：
图1a-1j表示根据实施例的封装结构的截面视图。
图2a-2d表示根据实施例的封装结构的顶平面视图。
图3表示根据实施例的方法的流程图。
图4表示根据实施例的系统的示意图。
具体实施方式
在以下具体实施方式中，参考通过例示的方式示出具体实施例的附图，可以在所述具体实施例中实践方法和结构。这些实施例被足够详细地描述以使本领域中的技术人员能够实践实施例。要理解的是，各种实施例尽管是不同的，但不一定是相互排斥的。例如，结合一个实施例在本文中所述的特定特证、结构或特性可以在其它实施例内实施，而不偏离实施例的精神和范围。另外，要理解的是，在每个所公开的实施例内的个体元件的位置或布置可以被修改，而不偏离实施例的精神和范围。以下具体实施方式因此不应以限制性意义进行理解，并且实施例的范围仅由被适当解释的所附权利要求连同权利要求赋予的等效形式的全范围限定。在附图中，类似的附图标记在全部几个视图中可以指代相同或相似的功能。
提出了形成并利用微电子封装结构(例如封装器件)的方法和相关联的结构。那些方法/结构可以包括提供衬底，其具有布置在其上的第一管芯，其中沟槽可以形成在第一管芯与模穿互连(TMI)结构之间。沟槽用于防止可以设置在TMI结构内的焊剂材料的流动。
图1a-1j描绘了形成包括沟槽开口的封装结构的实施例的截面视图。在图1a-1b中，例如可以在第一衬底100上放置/形成可以包括至少一个焊球102的至少一个互连结构102。第一衬底100可以包括任何类型的衬底材料，例如有机或无机衬底材料。在实施例中，衬底可以包括各种电路元件，例如可以由第一衬底100内的迹线承载的信令电路。在实施例中，第一衬底100可以包括第一侧105和第二侧107，并且可以包括第一封装衬底100。在实施例中，第一衬底100可以由任何标准印刷电路板(PCB)材料(例如图案化铜导体(迹线)和各种绝缘体(例如环氧树脂和诸如玻璃、硅石或其它材料之类的填料)的交替层)形成。
在实施例中，例如至少一个互连结构102可以包括任何类型的互连结构102，例如球栅阵列(BGA)互连和连接盘栅格阵列(LGA)互连。在实施例中，互连结构102可以被定位为邻近第一衬底100的边缘区101/外围。在实施例中，第一管芯104可以放置在第一衬底100上，并且可以被定位为相邻于互连结构102(图1c)。在实施例中，第一管芯104可以放置/定位在衬底100的中心区103中。在实施例中，第一管芯104可以包括片上系统(SOC)，并且在实施例中可以包括任何适当的集成电路器件，其包括但不限于微处理器(单核或多核)、存储器器件、芯片组、图形器件、专用集成电路、中央处理单元(CPU)等。
第一管芯104可以通过多个管芯/导电结构106(例如通过多个焊球)与第一衬底100通信地耦合，所述焊球可以包括例如球栅阵列焊球。在实施例中，模制化合物108可以形成/放置在第一衬底100之上，并且可以围绕第一管芯104和互连结构102(图1d)。在实施例中，第一管芯104可以完全嵌入在模制化合物108中。在其它实施例中，第一管芯104可以至少部分地嵌入在模制化合物108中。在实施例中，模制化合物108可以包括例如环氧树脂材料之类的材料。
在实施例中，开口112可以形成在模制化合物108中，开口112可以暴露衬底100上的焊接连接102(图1e)。可以通过使用过程110(例如激光去除过程)来形成开口112。在实施例中，可以利用其它类型的过程，以便形成开口112，其可以包括模穿互连(TMI)开口/过孔。在图1e中，开口被描绘为包括有角度的侧壁，但开口112的其它实施例可以包括大体上笔直的侧壁，或可以包括U形开口或任何其它适合的剖面。在实施例中，第一衬底100的每个边缘区101上的两个开口/过孔可以存在/形成，然而在其它实施例中，在第一衬底100的每个侧面/边缘区101上可以有一个开口112，并且在其它实施例中，在第一衬底100的边缘区101中可以有多于两个开口112。
在实施例中，至少一个沟槽开口116可以形成在模制化合物108的设置在第一管芯104与互连结构102之间的一部分中(图1f)。至少一个沟槽开口116可以利用过程114(例如激光过程)来形成，例如其中开口可以形成在模制化合物108中。在实施例中，可以在与模具开口112过程步骤相同的过程步骤中形成至少一个沟槽开口116。在一些实施例中，至少一个沟槽开口116可以包括大约10μm(微米)到大约300μm的深度/高度117和大约10μm(微米)到大约1500μm的宽度119，但在其它实施例中可以根据特定的应用变化。在实施例中，可以有被定位为相邻于第一管芯104的至少一个沟槽116。
参考图2a-2c(第一封装衬底200的一部分的顶平面视图)，在实施例中，沟槽216可以包括连续沟槽216(图2a)，其中沟槽216以连续矩形形状形成，并围绕管芯204，例如第一管芯204。连续沟槽216位于互连结构202(位于衬底的边缘区201中)与第一管芯204之间。沟槽216包括模制化合物208中的开口。
在另一实施例中，可以形成沟槽216，使其可以包括不连续的矩形形状，其中沟槽部分216可以包括相邻矩形沟槽部分216之间的不连续性，如图2b中描绘的。在实施例中，模制化合物208包括在沟槽区域中比在不连续的沟槽区域/部分216之间的相邻非沟槽区域中更低的的沟槽高度。在另一实施例中，(图2c)沟槽216可以在第一衬底200的中心区域中以L形形成。L形沟槽部分216设置在第一管芯204与焊接连接202之间，并且包括比模制化合物208的相邻非沟槽L形部分更低的高度。在另一实施例中，至少一个沟槽开口116还可以包括硬化剂材料217(图2d)。例如，硬化剂217(例如包括金属材料的硬化剂217)可以放置/形成在至少一个沟槽开口216内。在实施例中，硬化剂材料217可以包括例如铜和/或不锈钢材料。在一些情况下，硬化剂217可以用于控制/减小本文的实施例的封装结构中的翘曲。在实施例中，可以例如通过使用胶(例如环氧树脂材料)来将硬化剂放置在至少一个沟槽216内。
返回参考图1g，可以在第一衬底100的第二侧107上放置/形成多个焊球118。焊剂材料120可以放置/形成在开口212中，并且可以覆盖/涂覆互连结构102(图1h)。在实施例中，焊剂材料120可以大体上填充开口212，但在其它实施例中，焊剂材料120可以只部分地填充开口212。在图1h-1i中，第二衬底122可以耦合到第一衬底100。在实施例中，第二衬底122可以包括第二管芯124和至少一个焊球126。在实施例中，第二管芯可以包括存储器管芯。
组装过程125可以将第一衬底100连接/耦合到第二衬底122，以形成堆叠式管芯结构130(图1j)。TMI接头(例如TMI焊接接头)可以由来自第二衬底122的焊料球与第一衬底100的至少一个互连结构102的连接形成。在堆叠式管芯结构130(其在实施例中可以包括PoP或3D堆叠式封装结构)的后续处理期间，例如在TMI焊料接头的回流处理期间，例如堆叠式封装结构130可以经历例如在大约150摄氏度到大约260摄氏度之间的温度处理。
沟槽开口116可以用于防止焊剂(例如焊剂120)从开口112例如朝着第一管芯104附近的区域流到封装表面。沟槽开口116另外可以用于在室温下和在更高的温度下改变封装翘曲。沟槽开口116能够通过防止焊剂材料的流动、通过防止/破坏焊剂材料的毛细管作用(capillary)引起的流动来防止堆叠式封装结构130的变形/翘曲。
图3描绘了形成包括沟槽的封装结构的方法的流程图。在步骤302，提供了衬底，其包括在第一衬底的边缘部分上的焊接连接和在第一衬底的中心部分中的第一管芯。在步骤304，在第一管芯上和焊接连接上形成模制化合物。在步骤306，在实施例中在模制化合物中形成可以包括TMI过孔的开口以暴露焊接连接。在步骤308，在第一管芯与焊接连接之间的模制化合物中形成至少一个沟槽。在实施例中，沟槽开口能够破坏可能出现的焊剂从TMI过孔朝着第一管芯的流动的毛细管作用。在实施例中，沟槽开口可以充当用于收集从管芯区内部流动/流到管芯区上的所有预焊剂的贮液器/坝。
在实施例中，本文的实施例的封装结构可以与能够提供设置在本文的封装结构中的微电子器件(例如管芯)与封装结构可以耦合到的下一级部件(例如电路板)之间的电通信的任何适合类型的结构耦合。
本文的实施例的封装结构及其部件可以包括例如电路元件，例如用于在处理器管芯中使用的逻辑电路。金属化层和绝缘材料可以被包括在本文的结构以及可以将金属层/互连耦合到外部设备/层的导电接触部/凸块中。本文的各个附图中描述的结构/设备可以包括例如硅逻辑管芯或存储器管芯或任何类型的适合的微电子设备/管芯的部分。在一些实施例中，设备还可以包括多个管芯，其可以相互堆叠，这取决于特定的实施例。在实施例中，(多个)管芯可以部分地或完全地嵌入在实施例的封装结构中。
本文中所包括的设备结构的各种实施例可以用于片上系统(SOC)产品，并且可以在设备(例如智能电话、笔记本电脑、平板电脑、穿戴式设备和其它电子移动设备)中得到应用。在各种实施方式中，封装结构可以被包括在膝上型电脑、上网本电脑、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录器和穿戴式设备中。在另外的实施方式中，本文中的封装设备可以被包括在处理数据的任何其它电子设备中。
实施例在本文包括显示减少的翘曲和增加的吞吐量和产量的封装结构(例如3D封装结构)的实现。
图4是根据实施例的计算设备400。计算设备400容纳板402，例如母板402。板402可以包括多个部件，包括但不限于处理器404和可以与集成电路管芯403通信地耦合的管芯上存储器406以及至少一个通信芯片408。处理器404可以物理地和电气地耦合到板402。在一些实施方式中，至少一个通信芯片408也可以物理地和电气地耦合到板402。在另外的实施方式中，通信芯片406是处理器404的部分。
根据其应用，计算设备400可以包括可以或可以不物理地和电气地耦合到板402并且可以或可以不通信地彼此耦合的其它部件。这些其它部件可以包括但不限于易失性存储器(例如DRAM)410、非易失性存储器(例如ROM)412、闪速存储器(未示出)、图形处理器单元(GPU)414、数字信号处理器(DSP)416、密码处理器442、芯片组420、天线422、显示器424(例如触摸屏显示器)、触摸屏控制器426、电池428、音频编码解码器(未示出)、视频编码解码器(未示出)、全球定位系统(GPS)设备429、罗盘430、加速度计、陀螺仪和其它惯性传感器432、扬声器434、照相机436和大容量存储设备(例如硬盘驱动器或固态驱动器)440、光盘(CD)(未示出)、数字多功能盘(DVD)(未示出)等。这些部件可以连接到系统板402，安装到系统板或与其它部件中的任一个组合。
通信芯片408实现了无线和/或有线通信，以用于将数据传输到计算设备400以及从计算设备400传输数据。术语“无线”及其派生词可以用于描述可通过使用经调制的电磁辐射来经由非固体介质传送数据的电路、设备、系统、方法、技术、通信信道等。该术语并不暗示相关联的设备不包含任何电线，虽然在一些实施例中它们可以不包含电线。通信芯片606可以实施多种无线标准或协议中的任一种，包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、以太网、其派生物以及被指定为3G、4G、5G和更高代的任何其它无线和有线协议。计算设备400可以包括多个通信芯片408。例如，第一通信芯片408可以专用于较短距离无线通信，例如Wi-Fi和蓝牙，并且第二通信芯片1006可以专用于较长距离无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
术语“处理器”可以指代处理例如来自寄存器和/或存储器的电子数据以将该电子数据转换成可以存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的部分。
在各种实施方式中，计算设备400可以是膝上型电脑、上网本电脑、笔记本电脑、超级本电脑、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、穿戴式设备、移动电话、桌上型计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字视频记录器。在另外的实施方式中，计算设备600可以是处理数据的任何其它电子设备。
实施例可以被实施为一个或多个存储器芯片、控制器、CPU(中央处理单元)、微芯片或使用母板互连的集成电路、专用集成电路(ASIC)和/或现场可编程门阵列(FPGA)的一部分。
尽管前述描述规定了可以在实施例的方法中使用的某些步骤和材料，但本领域中的技术人员将认识到，可以做出很多修改和替换。相应地，所有这样的修改、更替、替换和添加是要被认为是落在如由所附权利要求限定的实施例的精神和范围内。此外，本文提供的附图仅示出与实施例的实践有关的示例性微电子器件及相关联的封装结构的部分。因此，实施例不限于本文所述的结构。

Claims (24)

1.一种微电子封装结构，包括：
第一管芯，其设置在第一衬底上；
至少一个互连结构，其设置在所述第一衬底的边缘区上；
模制化合物，其设置在所述第一衬底的一部分上和所述第一管芯上；
所述模制化合物中的开口，其位于所述第一衬底的所述边缘区中，其中，所述至少一个互连结构设置在所述开口中；以及
所述模制化合物中的沟槽开口，其中，所述沟槽开口位于所述至少一个互连结构与所述第一管芯之间。
2.根据权利要求1所述的结构，其中，位于所述第一衬底的所述边缘区中的所述模制化合物中的所述开口包括模穿互连(TMI)过孔，并且其中，第二衬底的互连结构耦合到设置在所述第一衬底上的所述至少一个互连结构。
3.根据权利要求2所述的结构，其中，所述第二衬底的所述互连结构利用TMI焊接接头结构耦合到设置在所述第一衬底上的所述至少一个互连结构。
4.根据权利要求1-3中的任一项所述的结构，其中，所述沟槽开口能够防止焊剂材料流过所述第一管芯。
5.根据权利要求2-3中的任一项所述的结构，其中，设置在所述第二衬底上的第二管芯包括存储器，并且其中，所述第一管芯包括片上系统。
6.根据权利要求1-3中的任一项所述的结构，其中，所述沟槽开口包括连续形状、不连续形状和L形状的其中之一。
7.根据权利要求1-3中的任一项所述的结构，其中，所述封装结构包括堆叠式封装(PoP)结构。
8.一种微电子封装结构，包括：
板；以及
封装结构，其耦合到所述板，其中，所述封装结构包括：
第一管芯，其设置在第一衬底上；
模制化合物，其设置在所述第一衬底的一部分上和所述第一管芯上，其中，所述第一管芯至少部分地嵌入在所述模制化合物中；以及
所述模制化合物中的沟槽开口，其中，所述沟槽开口位于设置在所述第一衬底上的模穿互连(TMI)过孔与所述第一管芯之间。
9.根据权利要求8所述的结构，进一步包括耦合到所述第一衬底的第二衬底，其中，设置在所述第一衬底上的所述TMI过孔内的至少一个互连结构与设置在所述第二衬底上的互连结构电气和物理地耦合。
10.根据权利要求8所述的结构，其中，所述TMI过孔包括设置在所述至少一个互连结构的一部分上的焊剂材料。
11.根据权利要求8所述的结构，其中，所述第一管芯选自于由中央处理单元(CPU)管芯、逻辑管芯和片上系统(SOC)构成的组。
12.根据权利要求8-10中的任一项所述的结构，其中，所述沟槽开口包括大约10μm到大约300μm的高度。
13.根据权利要求8-10中的任一项所述的结构，其中，所述沟槽开口能够防止所述焊剂流过所述模制化合物的顶表面。
14.根据权利要求8-10中的任一项所述的结构，进一步包括系统，所述系统包括：
通信芯片，其通信地耦合到所述封装结构；以及
DRAM，其通信地耦合到所述通信芯片。
15.根据权利要求8-10中的任一项所述的结构，其中，所述封装结构包括PoP封装结构。
16.根据权利要求8-10中的任一项所述的结构，其中，所述封装结构包括3D可堆叠封装结构。
17.一种形成微电子封装结构的方法，包括：
将第一管芯放置在第一衬底的中心部分上，并且将至少一个焊球放置在所述第一衬底的边缘部分上；
在所述第一衬底的一部分上和所述第一管芯上形成模制化合物；
在所述模制化合物中形成模穿过孔开口，其中，所述模穿过孔开口暴露所述至少一个焊球；以及
在所述模制化合物中形成沟槽开口，其中，所述沟槽开口形成在所述模穿过孔开口与所述第一管芯之间。
18.根据权利要求17所述的方法，进一步包括将第二衬底耦合到所述第一衬底，其中，设置在所述第二衬底上的互连结构与设置在所述第一衬底上的所述模穿过孔开口内的所述至少一个焊球耦合。
19.根据权利要求17所述的方法，其中，所述沟槽开口能够防止设置在所述模穿过孔开口内的焊剂材料流动。
20.根据权利要求18所述的方法，其中，所述第一管芯选自于由中央处理单元(CPU)管芯、逻辑管芯和片上系统(SOC)构成的组，并且其中，所述第二衬底包括第二管芯，其中，所述第二管芯包括存储器管芯。
21.根据权利要求17-20中的任一项所述的方法，其中，所述沟槽开口包括大约10μm到大约300μm的高度。
22.根据权利要求17-20中的任一项所述的方法，其中，所述沟槽开口被形成为包括连续形状、不连续形状和L形状的其中之一。
23.根据权利要求17-20中的任一项所述的方法，其中，所述封装结构包括3D可堆叠封装结构。
24.根据权利要求17-20中的任一项所述的方法，进一步包括将硬化剂置于所述沟槽中。
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