TWI693688B - 微電子封裝體結構及其形成方法 - Google Patents

微電子封裝體結構及其形成方法 Download PDF

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TWI693688B
TWI693688B TW105112429A TW105112429A TWI693688B TW I693688 B TWI693688 B TW I693688B TW 105112429 A TW105112429 A TW 105112429A TW 105112429 A TW105112429 A TW 105112429A TW I693688 B TWI693688 B TW I693688B
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substrate
die
disposed
trench
hole
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TW105112429A
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TW201705424A (zh
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納迦Ｓ 耶納木錫
費輝陽
佩莫德 馬拉特卡
普拉珊那 雷格海文
羅伯特 尼克森
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美商英特爾公司
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C69/00—Combinations of shaping techniques not provided for in a single one of main groups B29C39/00 - B29C67/00, e.g. associations of moulding and joining techniques; Apparatus therefore
    • B29C69/001—Combinations of shaping techniques not provided for in a single one of main groups B29C39/00 - B29C67/00, e.g. associations of moulding and joining techniques; Apparatus therefore a shaping technique combined with cutting, e.g. in parts or slices combined with rearranging and joining the cut parts
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B29C33/0033—Moulds or cores; Details thereof or accessories therefor constructed for making articles provided with holes
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B29L2031/3481—Housings or casings incorporating or embedding electric or electronic elements
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    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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Abstract

本文描述一種形成包含溝槽之封裝體結構的方法。一實施例包括配置在一第一基體上之一第一晶粒，及配置在該第一基體之一周邊區域的至少一互連結構。一模型化複合體係配置在該第一基體之一部分及配置在該第一晶粒上，其中一溝槽孔道係配置在設置在該至少一互連結構與該第一晶粒之間的該模型化複合體中。

Description

微電子封裝體結構及其形成方法
本發明係有關於於封裝體結構中形成溝槽之方法及藉其所形成的結構。
當包裝技術走向日益小型化時，上述技術在形成通模互連(TMI)結構時可被使用，其中可達到整合兩個分別封裝之晶粒以形成一更大的整體封裝體。例如，在層疊封裝(PoP)結構中，一第一封裝晶粒可藉由使用兩個封裝晶粒間之焊球連接體而與一第二封裝晶粒耦接，該等焊球連接體可設置在一TMI孔道內。
依據本發明之一實施例，係特地提出一種微電子封裝體結構，其包含：一第一晶粒，其配置在一第一基體上；至少一互連結構，其配置在該第一基體之一邊緣區域上；一模制化合物，其配置在該第一基體之一部分上及該第一晶粒上；一孔道，其係在該第一基體之該邊緣區域中的該模制化合物中，其中該至少一互連結構配置在該孔道中；以及一溝槽孔道，其係在該模制化合物中，其中該溝 槽孔道係位於該至少一互連結構與該第一晶粒之間。
100:第一基體、第一封裝體基體、基體
101、201:邊緣區
102:互連結構、焊球、焊料連接體
103:中心區域
104:第一晶粒
105:第一側
106:傳導性結構
107:第二側
108、208:模制化合物
110、114:程序
112:孔道、模制孔道
116:溝槽孔道、溝槽
117:深度/高度
118、126:焊球
119:寬度
120:助焊劑材料、助焊劑
122:第二基體
124:第二晶粒
125:裝配程序
130:堆疊晶粒結構
200:第一封裝體基體、第一基體
202:互連結構、焊料連接體
204:晶粒、第一晶粒
216:溝槽、溝槽部分、溝槽區域、溝槽孔道
217:加強件材料、加強件
302、304、306、308:步驟
400:運算裝置
402:板、母板、系統板
403:積體電路晶粒
404:處理器
406:晶粒上記憶體
408:通訊晶片、第一通訊晶片
410:依電性記憶體
412:非依電性記憶體
414:圖形處理器單元
416:數位信號處理器
420:晶片組
422:天線
424:顯示器
426:觸碰螢幕控制器
428:電池
429:全球定位系統裝置
430:羅盤
432:加速度計、陀螺儀、慣性感測器
434:揚聲器
436:攝影機
440:大量儲存裝置
442:密碼處理器
600:運算裝置
606:通訊晶片
雖然本案說明書係以詳細地指出並清楚地界定出某些實施例之申請專利範圍作為結尾，但是可在研讀本發明以下說明內容搭配附圖時更加容易確知該等實施例之優點，其中：圖1a~1j表示依據本發明實施例之封裝體結構的剖面圖。
圖2a~2d表示依據本發明實施例之封裝體結構的俯視圖。
圖3表示依據本發明實施例之方法的流程圖。
圖4表示依據本發明實施例之系統的示意圖。
在以下詳細說明內容中，其係參照了透過圖示說明方式來顯示出具體實施例的附圖，其中方法及結構可於該等實施例中實行。該等實施例被足夠詳細描述，以使熟於此技者能夠實行該等實施例。但應理解的是，本文所述各種實施例儘管不同，但不一定是相互排斥。例如，本文所述與一實施例有關之特定特徵、結構或特性可在其他實施例中實施，而不脫離該等實施例之精神與範圍。此外，應理解的是，本發明所揭各實施例之個別元件的位置或配置組合可被修改，而不脫離該等實施例之精神與範圍。因此，以下詳細說明內容並非採用限制性意義，且該等實施例之範圍係只由合理闡釋之隨附申請專利範圍連同申請專利範圍所享有之全部同等範圍所界定。在圖式中，類似標號在數個視圖中可意指相同或類似的功能性。
本文介紹形成及利用諸如封裝體裝置之微電子封裝體結構的方法及相關聯結構。該等方法/結構可包括提供一個其上配置有一第一晶粒之基體，其中一溝槽可形成於該第一晶粒與一通模互連(TMI)結構之間。該溝槽用以防止可配置於該TMI結構內之助焊劑材料的流動。
圖1a~1j描繪形成包含溝槽孔道之封裝的結構的實施例之剖面圖。在圖1a~1b中，至少一互連結構102，其可包含例如至少一焊球102，可被安置/形成在一第一基體100上。該第一基體100可包含任何類型之基體材料，諸如有機或無機基體材料。在一實施例中，該基體可包含各種電路元件，諸如發信號電路，該發信號電路可於該第一基體100內由跡線所攜帶。在一實施例中，該第一基體100可包含一第一側105及一第二側107，及可包含一第一封裝體基體100。在一實施例中，該第一基體100可由任何標準印刷電路板(PCB)材料所形成，諸如圖案化銅導體(跡線)及各種絕緣體之交替層，該等絕緣體係諸如環氧樹脂及諸如玻璃、二氧化矽或其他材料之填料。
在一實施例中，至少一互連結構102可包含任何類型之互連體結構102，例如諸如球柵陣列(BGA)互連體及平面柵格陣列(LGA)互連體。在一實施例中，互連體結構102可設置鄰近於第一基體100之邊緣區域101/周邊。在一實施例中，一第一晶粒104可放置於第一基體100上，及可鄰近互連結構102設置(圖1c)。在一實施例中，第一晶粒104可放置/設置於基體100之中心區域103。在一實施例中，第一晶 粒104可包含一單晶片系統(SOC)，且在多個實施例中可包含任何適當的積體電路裝置，包括但不限於微處理器(單核或多核)、記憶體裝置、晶片組、圖形裝置、應用特定積體電路、中央處理單元(CPU)或其類似者。
第一晶粒104可藉由多個晶粒/傳導性結構106，諸如藉由可包含例如球柵陣列焊球的多個焊球，而與第一基體100連通地耦接。在一實施例中，一模制化合物108可形成/安置於第一基體100上方，及可包圍第一晶粒104及互連結構102(圖1d)。在一實施例中，第一晶粒104可完全嵌入於模制化合物108中。在其他實施例中，第一晶粒104可至少部分地嵌入於模制化合物108中。在一實施例，模制化合物108可包含諸如環氧材料之材料。
在一實施例中，孔道112可形成於模制化合物108中，孔道112可使焊料連接體102暴露於基體100上(圖1e)。該等孔道112可藉由使用一程序110形成，諸如雷射移除程序。其他類型的程序可被利用，以形成該等孔道112，在一實施例中，其可包含通模互連(TMI)孔道/通孔。在圖1e中，該等孔道被描繪為包含角側壁，但該等孔道112之其他實施例可包括實質上平直的側壁，或可包括U形孔道或任何其他合適的輪廓外形。在一實施例中，第一基體100之各邊緣區101上可呈現/形成兩個孔道/通孔，然而，在其他實施例中，第一基體100之各側/邊緣區101上可有一個孔道112，及在其他實施例中，第一基體100之該等邊緣區101中可有超過兩個孔道112。
在一實施例中，至少一溝槽孔道116可被形成於配置在第一晶粒104與互連結構102間之模制化合物108之一部分中(圖1f)。該至少一溝槽孔道116可以一程序114形成，例如諸如一雷射程序，其中一孔道可形成於模制化合物108中。在一實施例中，該至少一溝槽孔道116可在進行與模制孔道112程序步驟相同的程序步驟時形成。該至少一溝槽孔道116在一些實施例中可包含大約10μm(微米)至大約300μm的一深度/高度117及大約10μm至大約1500μn的一寬度119，但在其他實施例中可根據特定應用而變化。在一實施例中，可有至少一溝槽116鄰近第一晶粒104設置。
參照圖2a~2c(第一封裝體基體200之一部分的俯視圖)，在一實施例中(圖2a)，一溝槽216可包含一連續溝槽216，其中溝槽216形成為一連續矩形形狀，並圍繞一晶粒204，諸如一第一晶粒204。連續溝槽216設置在互連結構202(設置在基體之一邊緣區201)與第一晶粒204之間。溝槽216包含在模制化合物208中之一孔道。
在另一實施例中，溝槽216可被形成使得其可包含一不連續矩形形狀，其中溝槽部分216可包含鄰近矩形溝槽部分216之間的不連續性，如圖2b所描繪。在一實施例中，模制化合物208包含在不連續溝槽區域/部分216間之一溝槽高度，在溝槽區域中之溝槽高度比在鄰近非溝槽區域中之溝槽高度更低。在另一實施例中(圖2c)，溝槽216可於第一基體200之轉角區域中被形成為L形狀。該L形狀的溝槽部分216配置在第一晶粒204與焊料連接體202之間，及包含比 模制化合物208之鄰近非溝槽L形狀部分更低的一高度。在另一實施例中，該至少一溝槽孔道116可進一步包含一加強件材料217(圖2d)。例如，一加強件217，諸如包含金屬材料之加強件217，可被安置/形成於該至少一溝槽孔道216內。在一實施例中，加強件材料217可包含例如銅及/或不銹鋼材料。在一些情況中，加強件材料217可用來控制/減少本文所述實施例之封包體結構中的翹曲。在一實施例中，該加強件可藉由使用黏膠，例如諸如環氧材料，而被安置於該至少一溝槽216內。
回過來參照圖1g，多個焊球118可被安置/形成於第一基體100之第二側107。一助焊劑材料120可被安置/形成於孔道212中，且可覆蓋/塗覆互連結構102(圖1h)。在一實施例中，助焊劑材料120可實質地填充孔道212，但在其他實施例中，助焊劑材料120可僅部分地填充孔道212。在圖1h~1i中，一第二基體122可被耦接至第一基體100。在一實施例中，第二基體122可包含一第二晶粒124，及至少一焊球126。在一實施例中，該第二晶粒可包含一記憶體晶粒。
一裝配程序125可接合/耦接第一基體100至第二基體122，以形成堆疊晶粒結構130(圖1j)。一TMI接合點，諸如TMI焊料接合點，可藉由將來自第二基體122之焊球與第一基體100之至少一互連結構102接合而形成。在堆疊晶粒結構130的後續處理程序期間(其在實施例中可包含Pop或3D堆疊之封裝體結構)，例如諸如在TMI焊料接合點之回 流焊處理程序期間，堆疊之封裝體結構130可經歷例如大約攝氏150度至大約攝氏260度之間的溫度處理程序。
溝槽孔道116可用來防止助焊劑，諸如助焊劑120，從該等孔道112流動至封裝體表面，諸如朝接近第一晶粒104之區域。溝槽孔道116可另外用來改變在室溫及更高之溫度兩者的封裝體翹曲。多個溝槽孔道116能夠防止堆疊之封裝體結構130的變形/翹曲，藉著藉由防止/打斷助焊劑材料之毛細作用誘導的流動來防止助焊劑材料之流動。
圖3描繪形成包含溝槽之封裝體結構之方法的流程圖。在步驟302，一基體被設置，該基體包含一第一基體之一邊緣部分上之焊料連接體，及該第一基體之一中心部分中之一第一晶粒。在步驟304，一模制化合物被形成於該第一晶粒上及於該等焊料連接體上。在步驟306，孔道，其在一實施例中可包含TMI通孔，被形成於該模制化合物中而在該第一晶粒與該等焊料連接體之間。在步驟308，至少一溝槽被形成於該模制化合物中而在該第一晶粒與該等焊料連接體之間。在一實施例中，溝槽孔道能夠破壞從TMI通孔朝該第一晶粒的助焊劑之流動的毛細作用。在一實施例中，該等溝槽孔道可作用為一儲存槽/壩，用以收集所有預先助焊劑以免流進晶粒區域內/流至該晶粒區域上。
在一實施例中，本文所述實施例中之封裝體結構可與能提供一微電子裝置間之電氣通訊的任何適合類型之結構耦接，諸如配置在本文所述封裝體結構中之晶粒，及可耦接有封裝體結構之次級組件(例如電路板)。
本文所述實施例之封裝體結構及其組件可包含例如諸如邏輯電路之電路元件，以供於一處理器晶粒中使用。多個金屬化層及絕緣材料可被含括於本文所述之結構中，以及可將金屬層/互連體耦接至外部裝置/層體之傳導接點/凸塊。本文所揭各種圖式中所描述的結構/裝置可包含例如矽邏輯晶粒或記憶體晶粒之部分或任何類型之合適微電子裝置/晶粒。在一些實施例中，該等裝置可進一步包含多個晶粒，其可被堆疊於彼此上，取決於特定實施例。在一實施例中，該(等)晶粒可部分地或完全地嵌入於多個實施例之封裝體結構中。
本文所含括之裝置結構的各種實施例可用於單晶片系統(SOC)產品，並可於諸如智慧型手機、筆記型電腦、平板電腦、穿戴式裝置及其他電子行動裝置之裝置中找到應用。在各種實施範例中，該等封裝體結構可含括於膝上型電腦、輕省筆電、筆記型電腦、超輕薄筆電、智慧型手機、平板電腦、個人數位助理(PDA)、超移動PC、行動電話、桌上型電腦、伺服器、印表機、掃描機、終端機、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位錄影機、及可穿戴裝置。在進一步的實施範例中，本文所述該等封裝體裝置可被含括於處理資料之任何其他電子裝置中。
本文所述實施例包括諸如3D封裝體結構之封裝體結構的實現，其顯示降低的翹曲及增加的產量及良率。
圖4為依據一實施例之一運算裝置400的示意圖。 運算裝置400擁有一板402，例如諸如一母板402。板402可包括多個組件，包括但不限於一處理器404及一晶粒上記憶體406，該晶粒上記憶體406可通訊地與一積體電路晶粒403耦接，以及至少一通訊晶片408。處理器404可實體及電氣地耦接至板402。在一些實施範例中，至少一些通訊晶片408可實體及電氣地耦接至板402。在進一步的實施實例中，通訊晶片406為處理器404的一部分。
取決於其應用，運算裝置400可包括其他組件，該等其他組件可或不可實體及電氣地耦接至板402，以及彼此可或不可通訊地耦接。該等其他組件包括但不限於依電性記憶體(例如DRAM)410、非依電性記憶體(例如ROM)412、快閃記憶體(未顯示)、圖形處理器單元(GPU)414、數位信號處理器(DSP)416、密碼處理器442、晶片組420、天線422、諸如觸碰螢幕顯示器之顯示器424、觸碰螢幕控制器426、電池428、音訊編解碼器(未顯示)、視訊編解碼器(未顯示)、全球定位系統(GPS)裝置429、羅盤430、加速度計、陀螺儀及其他慣性感測器432、揚聲器434、攝影機436、大量儲存裝置(諸如硬碟驅動器或固態驅動器)440、光碟(CD)(未顯示)、數位通用光碟(DVD)(未顯示)等等。該等組件可連接至系統板402、安裝至系統板、或與任何其他組件結合。
通訊晶片408使對於資料之傳輸的無線及/或有線通訊能夠來回於運算裝置400。用語「無線」及其衍生物可被用來描述電路、裝置、系統、方法、技術、通訊通道 等，其可透過非固態媒體透過調變的電磁輻射之使用而通訊資料。上述用語並未暗示相關聯之裝置未含有任何線路，雖然在一些實施例中該等裝置可能未含有線路。該通訊晶片606可實現任何數目之無線或有線標準或協定，包括但不限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演化(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其乙太網路衍生物、以及被指定為3G、4G、5G及超過此範圍之任何其他無線及有線協定。運算裝置400可包括多個通訊晶片408。例如，一第一通訊晶片408可專用於諸如Wi-Fi及藍牙之較短範圍無線通訊，及一第二通訊晶片1006可專用於諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其他之較長範圍無線通訊。
用語「處理器」可意指處理來自暫存器及/或記憶體之電子資料以將該電子資料轉換為可儲存在暫存器及/或記憶體中之其他電子資料的任何裝置或裝置之部分。
在多個實施範例中，運算裝置400可為膝上型電腦、輕省筆電、筆記型電腦、超輕薄筆電、智慧型手機、平板電腦、個人數位助理(PDA)、超移動PC、可穿戴裝置、行動電話、桌上型電腦、伺服器、印表機、掃描機、終端機、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位錄影機。在進一步的實施範例中，運算裝置600可為處理資料之任何其他電子裝置。
實施例可實施為一或多個記憶體晶片、控制器、 CPU(中央處理單元)、使用母板互連之微晶片或積體電路、應用特定積體電路(ASIC)、及/或現場可規劃閘陣列(FPGA)之一部分。
雖然前述說明已指定某些步驟及可用在該等實施例之方法中的材料，熟於此技者將理解到可做出許多修改及替換。據此，本文意圖將所有該等修改、變更、替換及增加考量落入如隨附申請專利範圍所界定之實施例的精神及範圍內。此外，本文所提供之圖式僅闡釋出屬於該等實施例之實施的示例性微電子裝置及相關聯封裝體結構之一部分。因此，該等實施例不限於本文所述結構。
100:第一基體、第一封裝體基體、基體
101:邊緣區
102:互連結構、焊球、焊料連接體
104:第一晶粒
106:傳導性結構
108:模制化合物
110:程序
112:孔道、模制孔道

Claims (23)

  1. 一種微電子封裝體結構，其包含：一第一晶粒，其配置在一第一基體上；至少一互連結構，其配置在該第一基體之一邊緣區域上；一模制化合物，其配置在該第一基體之一部分上及該第一晶粒上；一孔道，其係在位於該第一基體之該邊緣區域中的該模制化合物中，其中該至少一互連結構配置在該孔道中；以及一溝槽孔道，其係在該模制化合物中，其中該溝槽孔道係位於該至少一互連結構與該第一晶粒之間，其中該溝槽孔道包括一金屬加強件，其中一第二基體之一互連結構被耦接至配置在該第一基體上之該至少一互連結構，且其中該第二基體係與該模制化合物接觸。
  2. 如請求項1之結構，其中於位在該第一基體之該邊緣區域中的該模制化合物中之該孔道包含一通模互連(TMI)通孔。
  3. 如請求項2之結構，其中於配置在該第一基體上之該至少一結構與配置在該第二基體上之該互連體結構之間的耦接包含一TMI焊料接合結構。
  4. 如請求項1之結構，其中該溝槽孔道要防止一助焊劑材料之流動跨越該第一晶粒。
  5. 如請求項2之結構，其中配置在該第二基體上之一第二晶粒包含一記憶體，且其中該第一晶粒包含一單晶片系統。
  6. 如請求項1之結構，其中該溝槽孔道包含連續形狀、不連續形狀及L形狀中之一者。
  7. 如請求項1之結構，其中該封裝體結構包含一層疊封裝(PoP)結構。
  8. 一種微電子封裝體結構，其包含：一板；一封裝體結構，其耦接至該板，其中該封裝體結構包含：一第一晶粒，其配置在一第一基體上；一模制化合物，其配置在該第一基體之一部分上及該第一晶粒上，其中該第一晶粒至少部分地嵌入於該模制化合物中；以及一溝槽孔道，其係在該模制化合物中，其中該溝槽孔道係位於一配置在該第一基體上之TMI通孔與該第一晶粒之間，其中該溝槽孔道包括一金屬加強件；耦接至該第一基體之一第二基體；配置在該第一基體上之該TMI通孔內之至少一互連結構；以及配置在該至少一互連結構之一部分上之一助焊劑材料，其中該助焊劑材料之一部分也在該溝槽孔道中。
  9. 如請求項8之結構，其中配置在該第一基體上之該TMI 通孔內的該至少一互連結構電氣及實體地與配置在該第二基體上之一互連結構耦接。
  10. 如請求項8之結構，其中該第一晶粒係選自於由一中央處理單元(CPU)晶粒、一邏輯晶粒、及一單晶片系統(SOC)所組成之群組。
  11. 如請求項8之結構，其中該溝槽孔道包含大約10μm至大約300μm之一高度。
  12. 如請求項8之結構，其中該溝槽孔道要防止該助焊劑材料流動跨越該模制化合物之一頂表面。
  13. 如請求項8之結構，進一步包含一系統，其包含：一通訊晶片，其通訊地耦接至該封裝體結構；以及一DRAM，其通訊地耦接至該通訊晶片。
  14. 如請求項8之結構，其中該封裝體結構包含一PoP封裝體結構。
  15. 如請求項8之結構，其中該封裝體結構包含一3D可堆疊封裝體結構。
  16. 一種形成一微電子封裝體結構之方法，其包含：將一第一晶粒安置於一第一基體之一中央部分上，及將至少一焊球安置於該第一基體之一邊緣部分上；形成一模制化合物於該第一基體之一部分上及該第一晶粒上；形成一通模通孔孔道於該模制化合物中，其中該通模通孔孔道暴露出該至少一焊球；形成一溝槽孔道於該模制化合物中，其中該溝槽孔 道係形成於該通模通孔孔道與該第一晶粒之間；以及將一金屬加強件安置於該溝槽孔道中。
  17. 如請求項16之方法，其進一步包含將一第二基體耦接至該第一基體，其中配置在該第二基體上之一互連結構係與配置在該第一基體上之該通模通孔孔道內之該至少一焊球耦接。
  18. 如請求項16之方法，其中該溝槽孔道要防止配置在該通模通孔孔道內之一助焊劑材料的流動。
  19. 如請求項17之方法，其中該第一晶粒係選自於由一中央處理單元(CPU)晶粒、一邏輯晶粒、及一SOC所組成之群組，且其中該第二基體包含一第二晶粒，其中該第二晶粒包含一記憶體晶粒。
  20. 如請求項16之方法，其中該溝槽孔道包含大約10μm至大約300μm之一高度。
  21. 如請求項16之方法，其中該溝槽孔道係形成為包含連續形狀、不連續形狀及L形狀中之一者。
  22. 如請求項16之方法，其中該封裝體結構包含一3D可堆疊封裝體結構。
  23. 如請求項16之方法，其中將該金屬加強件安置於該溝槽孔道中包括將該金屬加強件黏合於該溝槽孔道中。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11635456B2 (en) * 2016-02-12 2023-04-25 Yale University Techniques for control of quantum systems and related systems and methods
KR102400101B1 (ko) 2017-11-03 2022-05-19 삼성전자주식회사 Pop 반도체 패키지 및 그를 포함하는 전자 시스템
WO2019156760A1 (en) 2018-01-05 2019-08-15 Yale University Hardware-efficient fault-tolerant operations with superconducting circuits
JP7040032B2 (ja) * 2018-01-17 2022-03-23 株式会社デンソー 半導体装置
CN108346952B (zh) * 2018-01-25 2020-11-24 番禺得意精密电子工业有限公司 电连接器固持装置
KR102497572B1 (ko) 2018-07-03 2023-02-09 삼성전자주식회사 반도체 패키지 및 그의 제조 방법
KR102448238B1 (ko) 2018-07-10 2022-09-27 삼성전자주식회사 반도체 패키지
US10770385B2 (en) 2018-07-26 2020-09-08 International Business Machines Corporation Connected plane stiffener within integrated circuit chip carrier
CN110572593B (zh) * 2019-08-19 2022-03-04 上海集成电路研发中心有限公司 一种3d堆叠式图像传感器
KR20220048532A (ko) 2020-10-12 2022-04-20 삼성전자주식회사 반도체 패키지 및 그 제조방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130187288A1 (en) * 2012-01-20 2013-07-25 Samsung Electronics Co., Ltd. Package-on-package assembly
US20140335656A1 (en) * 2011-12-14 2014-11-13 SK Hynix Inc. Semiconductor stack packages and methods of fabricating the same
US20150070865A1 (en) * 2013-09-12 2015-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-Package Structure with Through Molding Via

Family Cites Families (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3334693B2 (ja) 1999-10-08 2002-10-15 日本電気株式会社 半導体装置の製造方法
SG99331A1 (en) 2000-01-13 2003-10-27 Hitachi Ltd Method of producing electronic part with bumps and method of producing elctronic part
US6504242B1 (en) 2001-11-15 2003-01-07 Intel Corporation Electronic assembly having a wetting layer on a thermally conductive heat spreader
US6597575B1 (en) 2002-01-04 2003-07-22 Intel Corporation Electronic packages having good reliability comprising low modulus thermal interface materials
US7036573B2 (en) 2002-02-08 2006-05-02 Intel Corporation Polymer with solder pre-coated fillers for thermal interface materials
US7436058B2 (en) 2002-05-09 2008-10-14 Intel Corporation Reactive solder material
JP4022100B2 (ja) * 2002-05-30 2007-12-12 京セラ株式会社 電子部品装置の製造方法
US6841867B2 (en) 2002-12-30 2005-01-11 Intel Corporation Gel thermal interface materials comprising fillers having low melting point and electronic packages comprising these gel thermal interface materials
US7252877B2 (en) 2003-02-04 2007-08-07 Intel Corporation Polymer matrices for polymer solder hybrid materials
US7014093B2 (en) 2003-06-26 2006-03-21 Intel Corporation Multi-layer polymer-solder hybrid thermal interface material for integrated heat spreader and method of making same
US7527090B2 (en) 2003-06-30 2009-05-05 Intel Corporation Heat dissipating device with preselected designed interface for thermal interface materials
US7253523B2 (en) 2003-07-29 2007-08-07 Intel Corporation Reworkable thermal interface material
US7170188B2 (en) 2004-06-30 2007-01-30 Intel Corporation Package stress management
JP4137112B2 (ja) 2005-10-20 2008-08-20 日本テキサス・インスツルメンツ株式会社 電子部品の製造方法
JP4963879B2 (ja) * 2006-06-16 2012-06-27 株式会社ソニー・コンピュータエンタテインメント 半導体装置および半導体装置の製造方法
US7823762B2 (en) 2006-09-28 2010-11-02 Ibiden Co., Ltd. Manufacturing method and manufacturing apparatus of printed wiring board
KR100923887B1 (ko) 2008-01-29 2009-10-28 (주)덕산테코피아 반도체 패키지용 솔더볼
US7971347B2 (en) 2008-06-27 2011-07-05 Intel Corporation Method of interconnecting workpieces
US7851894B1 (en) 2008-12-23 2010-12-14 Amkor Technology, Inc. System and method for shielding of package on package (PoP) assemblies
US9006887B2 (en) 2009-03-04 2015-04-14 Intel Corporation Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
KR101055509B1 (ko) 2009-03-19 2011-08-08 삼성전기주식회사 전자부품 내장형 인쇄회로기판
KR101077410B1 (ko) 2009-05-15 2011-10-26 삼성전기주식회사 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR20100132823A (ko) 2009-06-10 2010-12-20 삼성전기주식회사 플립칩용 기판 및 그 제조방법
KR101194549B1 (ko) 2009-06-12 2012-10-25 삼성전기주식회사 인쇄회로기판의 제조방법
KR20110030152A (ko) 2009-09-17 2011-03-23 삼성전기주식회사 패키지기판 및 그 제조방법
KR101037450B1 (ko) 2009-09-23 2011-05-26 삼성전기주식회사 패키지 기판
US20110076472A1 (en) 2009-09-29 2011-03-31 Jin Ho Kim Package substrate
KR20110039879A (ko) 2009-10-12 2011-04-20 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101084910B1 (ko) 2009-10-12 2011-11-17 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101095094B1 (ko) 2009-10-26 2011-12-16 삼성전기주식회사 웨이퍼 레벨 패키지의 제조방법
KR101095130B1 (ko) 2009-12-01 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
US20110240927A1 (en) 2009-12-23 2011-10-06 Samsung Electro-Mechanics Co., Ltd. Conductive polymer composition and conductive film formed using the same
US20110147668A1 (en) 2009-12-23 2011-06-23 Sang Hwa Kim Conductive polymer composition and conductive film prepared using the same
KR101109214B1 (ko) 2009-12-28 2012-01-30 삼성전기주식회사 패키지 기판 및 그 제조방법
KR101119303B1 (ko) 2010-01-06 2012-03-20 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101077408B1 (ko) 2010-02-05 2011-10-26 서강대학교산학협력단 Ｃｍｏｓ 이미지 센서
US8378476B2 (en) * 2010-03-25 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with stacking option and method of manufacture thereof
KR101067109B1 (ko) 2010-04-26 2011-09-26 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR20120026855A (ko) 2010-09-10 2012-03-20 삼성전기주식회사 임베디드 볼 그리드 어레이 기판 및 그 제조 방법
US8313982B2 (en) 2010-09-20 2012-11-20 Texas Instruments Incorporated Stacked die assemblies including TSV die
KR101289140B1 (ko) 2010-09-28 2013-07-23 삼성전기주식회사 임베디드 인쇄회로기판 및 그 제조방법
KR20120035673A (ko) 2010-10-06 2012-04-16 삼성전기주식회사 패키지기판
KR101095161B1 (ko) 2010-10-07 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판
KR20120042240A (ko) 2010-10-25 2012-05-03 삼성전자주식회사 Ｔｍｖ 패키지온패키지 제조방법
KR20120050755A (ko) 2010-11-11 2012-05-21 삼성전기주식회사 반도체 패키지 기판 및 그 제조방법
KR101719822B1 (ko) 2010-11-24 2017-03-27 삼성전기주식회사 솔더링 연결핀, 상기 솔더링 연결핀을 이용한 반도체 패키지 기판 및 반도체칩의 실장방법
KR20120069443A (ko) 2010-12-20 2012-06-28 삼성전기주식회사 패키지 기판용 리드핀과 상기 패키지 기판용 리드핀을 포함하는 반도체 패키지 인쇄회로기판
KR101204233B1 (ko) 2010-12-22 2012-11-26 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101194469B1 (ko) 2010-12-24 2012-10-24 삼성전기주식회사 패키지용 기판 및 그 제조방법
KR101255912B1 (ko) 2010-12-31 2013-04-17 삼성전기주식회사 멀티 칩 패키지
US8162203B1 (en) 2011-02-18 2012-04-24 International Business Machines Corporation Spherical solder reflow method
KR20140007429A (ko) 2011-03-31 2014-01-17 미쓰비시 가가꾸 가부시키가이샤 삼차원 집적 회로 적층체, 및 삼차원 집적 회로 적층체용 층간 충전재
JP5837339B2 (ja) 2011-06-20 2015-12-24 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
KR101237668B1 (ko) 2011-08-10 2013-02-26 삼성전기주식회사 반도체 패키지 기판
JP5658640B2 (ja) * 2011-09-12 2015-01-28 ルネサスエレクトロニクス株式会社 半導体装置
US9950393B2 (en) 2011-12-23 2018-04-24 Intel Corporation Hybrid low metal loading flux
KR20130082298A (ko) 2012-01-11 2013-07-19 삼성전자주식회사 패키지 온 패키지 장치의 제조 방법 및 이에 의해 제조된 장치
JP2013225638A (ja) 2012-03-23 2013-10-31 Toshiba Corp 半導体装置
KR101867955B1 (ko) 2012-04-13 2018-06-15 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
US9283641B2 (en) 2012-09-25 2016-03-15 Intel Corporation Flux materials for heated solder placement and associated techniques and configurations
US8809181B2 (en) 2012-11-07 2014-08-19 Intel Corporation Multi-solder techniques and configurations for integrated circuit package assembly
US9105626B2 (en) 2012-11-21 2015-08-11 Qualcomm Incorporated High-density package-on-package structure
US20140151096A1 (en) 2012-12-04 2014-06-05 Hongjin Jiang Low temperature/high temperature solder hybrid solder interconnects
US9064971B2 (en) 2012-12-20 2015-06-23 Intel Corporation Methods of forming ultra thin package structures including low temperature solder and structures formed therby
US20140175160A1 (en) 2012-12-21 2014-06-26 Rajen S. Sidhu Solder paste material technology for elimination of high warpage surface mount assembly defects
US9394619B2 (en) 2013-03-12 2016-07-19 Intel Corporation Methods of adding dopants to conductive interconnect structures in substrate technologies and structures formed thereby
US8896110B2 (en) 2013-03-13 2014-11-25 Intel Corporation Paste thermal interface materials
US8987918B2 (en) 2013-03-14 2015-03-24 Intel Corporation Interconnect structures with polymer core
US8920934B2 (en) 2013-03-29 2014-12-30 Intel Corporation Hybrid solder and filled paste in microelectronic packaging
KR102067155B1 (ko) 2013-06-03 2020-01-16 삼성전자주식회사 연결단자를 갖는 반도체 장치 및 그의 제조방법
US9082766B2 (en) 2013-08-06 2015-07-14 Google Technology Holdings LLC Method to enhance reliability of through mold via TMVA part on part POP devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140335656A1 (en) * 2011-12-14 2014-11-13 SK Hynix Inc. Semiconductor stack packages and methods of fabricating the same
US20130187288A1 (en) * 2012-01-20 2013-07-25 Samsung Electronics Co., Ltd. Package-on-package assembly
US20150070865A1 (en) * 2013-09-12 2015-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-Package Structure with Through Molding Via

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