TWI385736B - 形成層疊封裝互連之裝置及方法 - Google Patents

形成層疊封裝互連之裝置及方法 Download PDF

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Publication number
TWI385736B
TWI385736B TW098120444A TW98120444A TWI385736B TW I385736 B TWI385736 B TW I385736B TW 098120444 A TW098120444 A TW 098120444A TW 98120444 A TW98120444 A TW 98120444A TW I385736 B TWI385736 B TW I385736B
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Taiwan
Prior art keywords
workpiece
sacrificial
protective layer
carbonate
conductive
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TW098120444A
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English (en)
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TW201013796A (en
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Leonel Arana
Robert Nickerson
Lim Chong Sim
Edward Prack
Yoshihiro Tomita
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Intel Corp
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Publication of TW201013796A publication Critical patent/TW201013796A/zh
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49174—Assembling terminal to elongated conductor
    • Y10T29/49181—Assembling terminal to elongated conductor by deforming
    • Y10T29/49185—Assembling terminal to elongated conductor by deforming of terminal
    • Y10T29/49188—Assembling terminal to elongated conductor by deforming of terminal with penetrating portion
    • Y10T29/4919—Through insulation

Description

形成層疊封裝互連之裝置及方法
本發明之領域一般係關於微電子裝置之領域，更具體而言但非排外地，係關於半導體積體電路封裝。
舉例而言，諸如積體電路之微電子裝置通常與工件組合在一起並組裝於封裝中，該封裝係於使用前焊接或連接於印刷電路板。當微電子裝置效能增加，且該微電子裝置之實體尺寸減少時，多重晶片結構之間的連接以及晶片結構與其它元件之間之連接不符合預期地變大了且有時不可靠。
形成層疊封裝(PoP)互連之裝置及方法係說明於各種不同實施例中。於以下說明內容中，會陳述許多特定細節，諸如形成堆疊封裝之間之可靠互連且同時改善可製造性及減少堆疊封裝之彎曲及高度的有效方法之說明。
將安裝於工件上之晶片連接於另一個工件上之另一個晶片，以形成堆疊封裝，這是多階封裝之技術，其中進步的方式是，達成比先前技術方法更緊密的PoP間距及更小的形狀因數。此外，將堆疊封裝之整體高度減小至最低程度且同時提供兩個工件之間的可靠互連，這種方式是一種優點。再者，使用薄的可撓工件形成堆疊封裝且同時減少或消除工件之彎曲，這種方式亦是一種優點。減少動態彎曲且同時增強封裝平坦性可以降低製造上之破片並有助於將PoP厚度外形減小至最低程度。當前及未來之移動式網際網路裝置及智慧型手機需要增強之能力及速度且同時限制PoP裝置允許之包跡，對於這種當前及未來之移動式網際網路裝置及智慧型手機而言，這些優點特別有用。
藉由組合元件，諸如組合單晶片系統及通訊晶片、處理器及記憶體晶片、兩個或更多處理器、兩個或更多記憶體晶片、處理器及繪圖晶片、或其一或更多之組合，PoP架構可應用於各種多IC組構，以便以小形狀因素來提供增強能力。這種方法包含設置晶片於具導電區的工件上。犧牲結係形成於導電區上，且保護層係被沉積鄰近於犧牲結。犧牲結係被移除以於導電區之上形成空穴。
現在請參考圖式，圖1表示一流程圖，說明形成多封裝互連之方法的實施例。於流程要素100中，設置晶片附著之工件200，其具有一或更多個導電區205。晶片附著之工件200之實施例係以圖2之剖面形式來說明。晶片附著之工件200可包含附著於晶片215之工件210，晶片215具有晶片頂部表面245及保護性下面填充物240。於這個實施例中，上介面225、基板230、及下介面235係組合在一起以形成工件210。上介面225可包括導電區205，使用一或多個隔離區220將該等導電區205彼此分開。導電區205可由過渡金屬、其合金、或另外的導電材料所形成，諸如摻雜半導體，其做為電流傳輸媒介。導電區205可由單一導電材料所形成，或者每一導電區205可各由不同導電材料所形成。隔離區220可由非導電、絕緣介電材料所形成，其用於將該等導電區205彼此隔離。
工件210可為印刷佈線板，其包含適用於提供微電子元件間互連之導電圖案。於一個實施例中，工件210之厚度約小於200微米(μm)。基板230可包含複數個可撓層，諸如有機層之堆疊，其中具有一或更多個導電通孔，用於經由基板230將上介面225連接至下介面235。基板230可由以下之一或更多層所形成：聚醯亞胺或其它聚合膜、環氧樹脂構體、環氧樹脂及石英玻璃之纖維及/或微粒填充物之合成物、難燃劑4(FR4)、雙馬來醯亞胺三嗪(BT)、以及液晶聚合物(LCP)。可使用諸如銅(Cu)、銀(Ag)、或金(Au)之過渡金屬來形成導電通孔，雖然實施例並不限於此。可使用黏著層將每一有機層彼此附著在一起。下界面可架構有複數個焊球(圖未示)，用以介接另外之封裝或電路板。於其它實施例中，使用於當前半導體製造之陶瓷基板、印刷電路板、或諸如矽基板之半導體基板可用於基板230。
晶片215可為諸如處理器之微電子裝置，其可包含基帶及應用程式處理功能及使用一或更多個處理器核心及/或特殊應用積體電路(ASIC)裝置中之韌體及硬體。於晶片215是處理器之實施例中，晶片215可處理抓取指令、產生解碼、找尋運算元、以及執行適當動作、然後儲存結果之功能。使用多核心可允許一個核心被指定為處理特殊應用功能，例如繪圖、調變解調功能等等。替代地，多處理器核心可允許處理工作負荷被分攤於該等處理器核心之間。於另一個實施例中，晶片215是另一種微電子裝置，諸如單晶片系統、通訊晶片、或繪圖晶片。
於流程要素105中，形成犧牲結於導電區205上。圖3說明晶片附著之工件200之剖面圖，其中複數個犧牲結305係形成於複數個導電區205上。可使用諸如聚原冰片烯或聚碳酸酯材料之觸變性及/或黏性材料來形成犧牲結305，並使用諸如塗佈(dispense)、印刷、旋塗、及取放之一或更多種方法來沉積犧牲結305。一旦沉積了犧牲結305，便可熱固化及/或紫外線(UV)固化犧牲結305，以形成高的高寬(高：寬)比特徵。於一個實施例中，高寬比之範圍約介於1:1與4:1之間，或較佳為，犧牲結305之高寬比約為2:1或更大。
於一個實施例中，形成犧牲結305之犧牲材料為選擇性地設計成熱分解成為非常輕之分子，而一旦受熱處理，僅留下微量或不留下犧牲材料。於一個實施例中，犧牲材料於攝氏150度及300度(℃)間分解，或較佳為於100℃及225℃間分解。例如，可使用諸如聚乙烯碳酸酯(PEC)、聚丙烯碳酸酯(PPC)、聚環己烷碳酸酯(PCC)、聚環己烷丙烯碳酸酯(PCPC)、聚原冰片烯碳酸酯(PNC)、聚原冰片烯及聚原冰片烯碳酸酯之共聚物、及彼等之組合之觸變性材料來形成犧牲結305。於一個實施例中，以UV照射處理之PPC之組合實質上在低於攝氏150度(℃)分解。於另一個實施例中，以UV照射處理之PPC實質上在低於攝式300度(℃)分解。
於流程要素110中，沉積保護層鄰近犧牲結305。圖4說明圖3之剖面圖，其中保護層405係形成於工件210上並在犧牲結305及晶片215之上。具有保護層頂部表面410之保護層405係一種多功能層，其可由選擇性設計成保護諸如晶片215及犧牲結305之下方結構之模製複合物所形成，保護層405可選擇性地用於控制工件210之彎曲。保護層405可由諸如環氧樹脂之聚合物所形成。例如，可使用諸如Sumitomo Bakelite Co. SFM或Henkel/Dexter模製封裝材料之一或更多種材料來形成保護層405。可使用後模製處理來熱處理保護層405，諸如使用溫度範圍為150℃及200℃之間之熱處理，或較佳為使用溫度範圍為165℃及185℃之間之熱處理。可根據保護層405對應之熱固化處理溫度來選擇保護層405，以允許犧牲結305之熱分解，藉以於熱分解犧牲結305之同時提供固化保護層405之有效率處理。此外，保護層405可選擇性地設計成防止形成於導電區205上之犧牲結305發生損壞或變形。
圖5說明圖3之工件210及所附著之晶片215之一替代實施例，其中保護層405係形成於工件210上並鄰近於犧牲結305及晶片215。於這個實施例中，保護層405之厚度係選擇性地設計成使犧牲結305暴露於保護層頂部表面410之上方，同時覆蓋晶片頂部表面245。於另一個實施例中(圖未示)，保護層頂部表面410係位於晶片頂部表面245之下方，同時設置暴露之犧牲結305。
於一個實施例中，浸蝕圖4之保護層405，以形成變薄之保護層605，如圖6所示。使用背硏磨處理、背磨光處理、濕式蝕刻、乾式蝕刻、或熟悉本項技術之人士所知之其它處理來浸蝕變薄之保護層605，以形成暴露之結610。從晶片頂部表面245之變薄之保護層605的厚度可高至約300微米(μm)，而在晶片215之上。於另一個實施例中(圖未示)，可浸蝕變薄之保護層605，以暴露晶片頂部表面245(圖未示)。替代地，對於圖5中所說明之實施例，犧牲結305已經受暴露，而且保護層405仍保持原狀。
於流程要素115中，移除犧牲結305，以在導電區205之上形成空穴。圖7說明圖6之剖面圖，其中犧牲結305係被移除，以形成空穴710於導電區205之上，以形成底部封裝700。在分解犧牲結305之後所產生之空穴710可為橢圓形，其空穴寬度715實質上是介於50μm與500μm間的範圍，且空穴高度720實質上是介於50μm與500μm間的範圍，如圖7所示。每一空穴710依其應用而定可彼此有不同之尺寸與形狀。此外，每一空穴710可實質上為圓形、矩形、正方形、不規則形狀。在這個中間階段，如有必要，可選擇性對底部封裝700進行用探針探測及/或測試及除錯。
圖8所示之PoP互連800說明圖7之底部封裝700，其中頂部封裝820係位於底部封裝600上。於這個實施例中，頂部封裝820包含焊料805，焊料805與埋設於覆蓋層825中之金屬墊815電接觸，以於頂部封裝820及圖7之底部封裝700之間形成互連。在將頂部封裝820定位於底部封裝700上之前，可選擇性地施加助熔劑於圖7之導電區205或圖8之焊料805。圖8之焊料805係為橢圓球體，雖然實施例不限於此。亦可使用其它之焊料形狀，諸如圓柱針狀或圓球體。如果要施加助熔劑，則可使用熟悉本項技術之人士所知之一或更多種方法，包括噴灑、印刷及旋塗，用以施加助熔劑(圖未示)。
然後使用使焊料805重熔流佈的選擇性設計之熱處理，使焊料805藉由熱處理重熔流佈以形成PoP互連800。用以使焊料805重熔流佈之熱處理係依所使用之焊料805之材料種類而定。使用可壓擠材料(諸如低熔點焊料合金)或實際上不可壓擠材料(諸如Cu及Sn/Ag合金)之一種或更多種材料來形成焊料805。於另一個實施例中，焊料805係由另外之可熔金屬所形成，該可熔金屬包含錫、銅、銀、鉍、銦、鋅及/或銻。
已經說明了用以於頂部封裝820與底部封裝700之間形成PoP互連800之裝置及方法之複數個實施例。於另外之實施例中(圖未示)，可將複數個底部封裝700與一頂部封裝820堆疊在一起，以形成另一個多階PoP結構。以上本發明之實施例的說明內容係用於解說之目的。其並非說盡所有一切，或其並非在於將本發明限於所揭示之精確形式。本說明內容及後附之申請專利範圍包含了一些用語，諸如左、右、頂部、底部、之上、之下、上、下、第一、第二，等等，其係僅用於說明之目的，並不在於構成限制。例如表示相對垂直位置之用語代表之情況為：基板或積體電路之裝置側(或作用表面)係為基板之「頂部」表面；該基板可實際上在任何方向上，致使在參考之標準地球架構中，基板之「頂部」側可低於「底部」側，且仍落入用語「頂部」之意義。此處(包含申請專利範圍)使用之用語「於..上」並非表示在第二層上之第一層係直接在第二層上並與第二層立即接觸，除非有特別說明；或許有第三層或其它結構位於第一層與在第一層上之第二層之間。此處說明之裝置或物件之實施例可以若干個位置及方向來製造、使用或運送。
然而，熟悉相關技術人士會認同，不需以一或更多項該特定細節便可實施各種不同實施例，或以其他取代及/或額外方法、材料或元件便可實施各種不同實施例。於其它例子中，並未詳細表示或說明熟知之結構、材料或操作，以避免使本發明所之各種實施例態樣變得不易明瞭。同樣地，為了解釋之目的，說明了特定數字、材料及組態，以便能完全瞭解本發明。然而，並不須特定細節便可實施本發明。此外，必須瞭解者為，圖式中所示之各種實施例是以圖解方式表示，並不需要依比例繪製。
在整個本說明書中所提到的「一個實施例」或「實施例」代表關於該實施例所說明之特性、結構、材料或特徵係包含於本發明之至少一個實施例中，但不表示它們存在於每一個實施例中。因此，在整個本說明書之不同部份中出現用語「於一個實施例中」或「於實施例中」並不一定表示本發明之相同實施例。此外，該特性、結構、材料或特徵可以任何適當方式組合於一個或更多實施例中。各種不同額外層及/或結構可包含於其它實施例中，及/或所說明之特性可於其它實施例中省略。
各種不同操作會被依次說明成多種分離之操作，以使最有幫助來瞭解本發明。然而，所說明之順序並非意謂著這些操作必須依著順序。尤其是，這些操作不須以所說明之順序進行。所說明之操作可以不同於所說明之實施例之順序來進行。各種不同額外操作可進行於額外實施例中，及/或所說明操作可省略於額外實施例中。
熟悉相關技術人士會認同，根據以上教示，可有許多修改及變化。熟悉本項技術人士會認同圖式中所示之各種不同元件之各種不同均等組合及置換。因此，本發明之範圍不受限於此詳細說明，而是為後附之申請專利範圍所界定。
200．．．工件
205．．．導電區
210．．．工件
215．．．晶片
220．．．隔離區
225．．．上介面
230．．．基板
235．．．下介面
240．．．保護性下面填充物
245．．．晶片頂部表面
305．．．犧牲結
405．．．保護層
410．．．保護層頂部表面
610．．．結
605．．．變薄之保護層
700．．．底部封裝
710．．．空穴
800．．．PoP互連
805．．．焊料
815．．．金屬墊
820．．．頂部封裝
825．．．覆蓋層
本發明係以圖式中之實例來加以說明，且其不構成限制。
圖1是流程圖，說明製程之實施例，該製程係用於在保護層中形成空穴。
圖2是剖面圖，說明附著於工件之晶片，其中導電區係形成於該工件之上表面上。
圖3說明圖2之工件及所附著之晶片，其中犧牲結係形成於導電區之至少一部份上。
圖4說明圖3之工件及所附著之晶片，其中保護層係形成於晶片及犧牲結上。
圖5說明圖3之工件及所附著之晶片之一替代實施例，其中保護層係形成於工件上並鄰近於犧牲結及晶片。
圖6說明圖4之工件及所附著之晶片，其具有暴露之犧牲結。
圖7說明圖6之工件及所附著之晶片，其中空穴係形成於導電區之至少一部份之上。
圖8說明位於圖7之底部封裝上之頂部封裝，其用於形成層疊封裝互連。
200．．．工件
205．．．導電區
210．．．工件
215．．．晶片
220．．．隔離區
225．．．上介面
230．．．基板
235．．．下介面
240．．．保護性下面填充物
245．．．晶片頂部表面

Claims (19)

  1. 一種形成多封裝互連之方法，包含：設置晶片於工件上，該工件包含導電區；形成犧牲結於該導電區上；鄰近於該犧牲結及該晶片，沉積保護層於該工件上；以及移除該犧牲結，以形成空穴在該導電區之上，其中，該方法進一步包含浸蝕該保護層以暴露該犧牲結之表面。
  2. 根據申請專利範圍第1項之方法，進一步包含將導體定位於該導電區上及在該空穴中。
  3. 根據申請專利範圍第2項之方法，其中該空穴是橢圓形。
  4. 根據申請專利範圍第1項之方法，其中該工件是多層有機結構。
  5. 根據申請專利範圍第1項之方法，其中使用熱處理移除該犧牲結。
  6. 根據申請專利範圍第4項之方法，其中該保護層抵抗該多層有機結構之彎曲。
  7. 一種互連工件之方法，包含：沉積觸變性材料在第一工件之導電區之上；固化該觸變性材料，以形成犧牲結於該等導電區上； 以保護層塗覆該第一工件；浸蝕該保護層，以暴露該等犧牲結；移除該等犧牲結，以暴露該等導電區；設置第二工件，其複數個導電元件係附著於該第二工件；以及將該第二工件之導電元件定位於該等導電區上。
  8. 根據申請專利範圍第7項之方法，其中該觸變性材料係選自由以下組成之群組：聚乙烯碳酸酯(PEC)、聚丙烯碳酸酯(PPC)、聚環己烷碳酸酯(PCC)、聚環己烷丙烯碳酸酯(PCPC)、聚原冰片烯碳酸酯(PNC)、聚原冰片烯及聚原冰片烯碳酸酯之共聚物。
  9. 根據申請專利範圍第7項之方法，進一步包含熱處理該等導電元件，以使該等導電元件流佈(flow)。
  10. 根據申請專利範圍第7項之方法，其中該等犧牲結是橢圓形球體。
  11. 根據申請專利範圍第7項之方法，其中該第一工件是多層有機結構。
  12. 根據申請專利範圍第7項之方法，其中當移除該等犧牲結時，固化該保護層。
  13. 一種形成互連之方法，包含：藉由施加足以使工件之導電區上的犧牲結蒸發之熱，形成空穴於保護層中，其中該熱之溫度範圍介於150℃至200℃之間。
  14. 根據申請專利範圍第13項之方法，進一步包含 藉由研磨該保護層之頂部表面，暴露該等犧牲結。
  15. 根據申請專利範圍第13項之方法，進一步包含將導體定位於該導電區上及在該空穴中。
  16. 根據申請專利範圍第13項之方法，其中該等空穴是橢圓形。
  17. 根據申請專利範圍第13項之方法，其中該工件是多層有機結構。
  18. 根據申請專利範圍第13項之方法，其中使用熱處理移除該等犧牲結。
  19. 根據申請專利範圍第13項之方法，其中使用觸變性材料來形成該等犧牲結，該觸變性材料係選自由以下組成之群組：聚乙烯碳酸酯(PEC)、聚丙烯碳酸酯(PPC)、聚環己烷碳酸酯(PCC)、聚環己烷丙烯碳酸酯(PCPC)、聚原冰片烯碳酸酯(PNC)、聚原冰片烯及聚原冰片烯碳酸酯之共聚物。
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