TW201637138A - 半導體元件的堆疊結構 - Google Patents

半導體元件的堆疊結構 Download PDF

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Publication number
TW201637138A
TW201637138A TW104111140A TW104111140A TW201637138A TW 201637138 A TW201637138 A TW 201637138A TW 104111140 A TW104111140 A TW 104111140A TW 104111140 A TW104111140 A TW 104111140A TW 201637138 A TW201637138 A TW 201637138A
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Taiwan
Prior art keywords
substrate
buffer layer
conductive
stacked structure
semiconductor device
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TW104111140A
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English (en)
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TWI662657B (zh
Inventor
郭柏辰
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聯華電子股份有限公司
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Application filed by 聯華電子股份有限公司 filed Critical 聯華電子股份有限公司
Priority to TW104111140A priority Critical patent/TWI662657B/zh
Priority to US14/700,160 priority patent/US9640502B2/en
Priority to CN201510216467.4A priority patent/CN106206554A/zh
Publication of TW201637138A publication Critical patent/TW201637138A/zh
Application granted granted Critical
Publication of TWI662657B publication Critical patent/TWI662657B/zh

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    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Abstract

本發明提供之一種半導體元件的堆疊結構包含一第一基板和一第二基板，一第一導電墊設於第一基板上，一導電柱接觸第一導電墊以及至少一第一緩衝層設於導電柱內部，其中導電柱包覆第一緩衝層，第一緩衝層之彈性係數和導電柱之彈性係數不同，一第二導電墊設於第二基板上，一鍚球設置於第二基板和第一基板之間，其中鍚球和導電柱電連結，此外導電柱可以選擇性地包含截頭錐形。

Description

半導體元件的堆疊結構
本發明係關於一種半導體元件的堆疊結構，尤其是關於一種半導體元件的堆疊結構中的導電柱，前述導電柱可以協助降低半導體元件因為溫度變化造成材料層剝落之情形。
在現今的資訊社會中，電子產品的設計是朝向輕、薄、短、小的趨勢邁進，因此發展出諸如堆疊式半導體元件封裝等有利於微型化的封裝技術。
堆疊式半導體元件封裝是利用垂直堆疊的方式將多個半導體元件封裝於同一封裝結構中，如此可提升封裝密度以及減少封裝體於水平方向的尺寸，且可利用立體堆疊的方式縮短半導體元件之間的訊號傳輸的路徑長度，以提升半導體元件之間訊號傳輸的速度，並可將不同功能的半導體元件組合於同一封裝體中。
通常堆疊的各層半導體元件係利用導電元件互相電連接，然而堆疊的各個半導體元件之間所使用的材料可能不同，因此造成堆疊的各個半導體元件之間的熱膨脹係數不同，因此發生溫度變化時，會發生各層元件變形的方向和變形的程度不同因而產生應力，而應力就會由導電元件傳送至各層半導體元件，造成半導體元件上的材料層剝離或破壞的情況。
根據本發明之一較佳實施例，本發明提供之一種半導體元件的堆疊結構包含一第一基板，一第一導電墊設於第一基板上，一導電柱接觸第一 導電墊以及至少一第一緩衝層設於導電柱內部，其中導電柱包覆第一緩衝層，第一緩衝層之彈性係數和導電柱之彈性係數不同，一第二基板，一第二導電墊設於第二基板上以及一鍚球設置於第二基板和第一基板之間，其中鍚球和導電柱電連結。
根據本發明之一較佳實施例本發明提供之一種半導體元件的堆疊結構，包含一第一基板，一第一導電墊設於第一基板上以及一導電柱接觸第一導電墊，其中導電柱包含一截頭錐形一第二基板一第二導電墊設於第二基板上以及一鍚球設置於第二基板上，其中鍚球和導電柱電連結。
10‧‧‧第一基板
12‧‧‧金屬內連線
14/44/114‧‧‧緩衝層
16‧‧‧導電墊
18/48‧‧‧保護層
20/24/30/50/58/68‧‧‧開口
26‧‧‧導電塊
22/28/56/66‧‧‧光阻層
32‧‧‧凹槽
34‧‧‧導電蓋
36‧‧‧導電柱
38/52‧‧‧鍚膏
40‧‧‧第二基板
42‧‧‧電路
46‧‧‧第二導電墊
54‧‧‧鍚球
62‧‧‧側壁
64‧‧‧上表面
100/200/300/400‧‧‧半導體元件的堆疊結構
361‧‧‧第一部分
362‧‧‧第二部分
363‧‧‧梯形
365‧‧‧第一底部
367‧‧‧第二底部
500‧‧‧半導體元件的堆疊結構
第1圖至第7圖為根據本發明之第一較佳實施例所繪示的半導體元件的堆疊結構之製作方法。
第8圖繪示的是根據本發明之第四較佳實施例所繪示的半導體元件的堆疊結構。
第9圖和第10圖為根據本發明之第二較佳實施例所繪示的半導體元件的堆疊結構之製作方法。
第11圖和第12圖為根據本發明之第五較佳實施例所繪示的半導體元件的堆疊結構之製作方法。
第13圖繪示的是根據本發明之第七較佳實施例所繪示的半導體元件的堆疊結構。
第14圖繪示的是根據本發明之第八較佳實施例所繪示的半導體元件的堆疊結構。
第1圖至第7圖為根據本發明之第一較佳實施例所繪示的半導體元件的堆疊結構之製作方法。如第1圖所示，首先提供一第一基板10，第一基板10可以為晶片、中介層、電路板或載板，在第一基板10上設置有電路， 舉例而言第一基板10可以為完成後段製程具有金屬內連線12的基板，之後在金屬內連線12上選擇性地形成一緩衝層14，緩衝層14的形成方式可以例如為全面形成一緩衝材料層(圖未示)，然後再圖案化緩衝材料層為緩衝層14，接著形成一導電層(圖未示)順應地覆蓋緩衝層14，接續再圖案化導電層為一第一導電墊16與金屬內連線12相電連接，再形成一保護層18覆蓋第一導電墊16，保護層18具有一開口20使得第一導電墊16由開口20曝露出來。
如第2圖所示，在保護層18上形成一防銲層(solder mask)，例如光阻層22，光阻層22具有一開口24曝露出第一導電墊16和部分的保護層18，接著選擇性在第一導電墊16上形成一底層凸塊金屬化層(under bump metallization,UBM)(圖未示)以及一晶種層(圖未示)，之後以電鍍的方式形成一導電塊26於光阻層22的開口24中和保護層18的開口20中，可以藉由調整光阻層22的開口24的形狀來控制導電塊26的形狀，例如開口24為立方體或截頭錐形，則在保護層18之上的導電塊26就會相對應地形成立方體或截頭錐形，之後，移除光阻層22。
如第3圖所示，形成一光阻層28，光阻層28具有一開口30曝露出部分的導電塊26，接著利用濕式蝕刻移除部分的導電塊26以在導電塊26中形成一凹槽32，但濕式蝕刻移除導電塊26的程度在使第一導電墊16曝露出來之前就需停止，此時凹槽32的底部依然由導電塊26構成。如第4圖所示，在凹槽32中填入至少一緩衝層114，之後再以電鍍方式形成一導電蓋34完全覆蓋緩衝層114，導電蓋34和導電塊26共同構成一個中空的導電柱36將緩衝層114包覆在其中。移除光阻層28後，如第5圖所示，在導電柱36上選擇性形成一鎳層(圖未示)，再形成一鍚膏38於鎳層上，鍚膏38係用來在後續的回銲(reflow)製程中形成鍚球。
如第6圖所示，提供一第二基板40，在第二基板40可以為晶片、中介層、電路板或載板，在第二基板上設置有電路42，舉例而言第二基板40可以為一載板，之後在電路42上選擇性地形成一緩衝層44，緩衝層44的形 成方式可以例如為全面形成一緩衝材料層(圖未示)，然後再圖案化緩衝材料層為緩衝層44，接著形成一導電層(圖未示)順應地覆蓋緩衝層44，接續再圖案化導電層為一第二導電墊46與金屬內連線42相電連接，再形成一保護層48覆蓋第二導電墊46，保護層48具有一開口50使得第二導電墊46由開口50曝露出來，最後在第二導電墊46上形成一鍚膏52。第二基板40上的第二導電墊46和緩衝層44的製作和在第一基板10上的導電柱36、緩衝層14/114、第一導電墊16的製作為獨立進行，也就是說在第一基板10上製作元件的時點和在第二基板40上製作元件的時點互不影響，只要在回銲製程之前將第一基板10上的鍚膏38和第二基板40上的鍚膏52完成即可。
如第7圖所示，進行回銲製程，將第一基板10和第二基板40上的鍚膏38/52接觸並且回銲後形成一鍚球54，至此，本發明之一半導體元件的堆疊結構100業已完成。
第1圖、第4圖至第6圖、第9圖和第10圖為根據本發明之第二較佳實施例所繪示的半導體元件的堆疊結構之製作方法，第二較佳實施例中之製作方法，同樣可以形成如第7圖中所示的半導體元件的堆疊結構。如第1圖所示，提供一第一基板10，在第一基板10上選擇性地形成緩衝層14，之後形成第一導電墊16、保護層18和開口20，其製作過程已在前文敘述，在此不再贅述。如第9圖所示，形成一防銲層，例如光阻層56，光阻層56具有一開口58曝露出第一導電墊16和部分的保護層18，之後以電鍍的方式形成一底層凸塊金屬化層(UBM)(圖未示)、一晶種層(圖未示)以及一導電塊26於光阻層56的開口58中和保護層18的開口20中。如第10圖所示，在開口58中填入緩衝層114，使得緩衝層114形成在導電塊26上，緩衝層114的形成方式可以為全面形成一緩衝材料層(圖未示)覆蓋光阻層56和導電塊26，之後圖案化緩衝材料層為緩衝層114，此外在圖案化緩衝材料層時，也可以形成多個小塊的緩衝層(圖未示)在導電塊26上。接著移除光阻層56，然後利用電鍍方式形成一導電蓋(圖未示)於緩衝層114上，詳細來說導電蓋覆蓋緩衝層 114的側壁62和上表面64，並且導電蓋成ㄇ字形由側壁62延伸到導電塊26，此時即形成如第4圖中所示的導電柱36，並且中空的導電柱36將緩衝層114完全包覆其中。接著如第5圖所示，在導電柱36上選擇性形成一鎳層(圖未示)，再形成一鍚膏38於鎳層上，鍚膏38係用來在後續的回銲(reflow)製程中形成鍚球。如第6圖所示，提供一第二基板40，如同前文所述在其上形成第二導電墊46、緩衝層44、保護層48和鍚膏52。最後如第7圖所示，進行回銲製程，將第一基板10和第二基板40上的鍚膏38/52接觸並且回銲後形成一鍚球54，至此完成半導體元件的堆疊結構100。
第7圖繪示的是根據本發明之第三較佳實施例所繪示的半導體元件的堆疊結構。請參閱第7圖，一半導體元件的堆疊結構100包含一第一基板10，第一基板10可以為晶片、中介層、電路板或載板，在第一基板10上設置有電路，舉例而言第一基板10可以為完成後段製程具有金屬內連線12的基板，一第一導電墊16設於第一基板10上，第一導電墊16電連接金屬內連線12，一緩衝14層選擇性地設置第一基板10上，並且位在第一導電墊16和金屬內連線12之間，也就是說金屬內連線12和第一導電墊16共同將緩衝層14完全包覆，根據不同的需求，在金屬內連線12和第一導電墊16之間也可以不設置緩衝層14。緩衝層14之彈性係數和第一導電墊16之彈性係數不同，較佳地緩衝層14之彈性係數大於第一導電墊16之彈性係數，此外緩衝層14也可視情況需要調整其數量，也就是說緩衝層14可以為複數個彼此不相接觸的方式分布於金屬內連線12表面，並且其形狀不限定，舉例而言，緩衝層14之截面可以為圓形、矩形和梯形等。一保護層18覆蓋第一導電墊16，保護層18具有一開口20使得第一導電墊18由開口20曝露出來，保護層18包含氧化矽、氮化矽等絕緣材料。一導電柱36接觸並電連接第一導電墊16，導電柱36分為第一部分361和第二部分362，第一部分361係位在保護層18的開口20中，第二部分362係位在保護層18的開口20之外，在第7圖中以虛線將導電柱36的第一部分361和第二部分362劃分開來，以協助清楚分辨第一部分361和第二部分362之位置。一 緩衝層114設於導電柱36內部，其中導電柱36完全包覆緩衝層114，此外緩衝層114之彈性係數和導電柱36之彈性係數不同，較佳地緩衝層114之彈性係數大於導電柱36之彈性係數，導電柱36可以為一立方體或是其它的形狀，導電柱36的材料包含銅或是其它的金屬或合金，根據本發明之較佳實施例，導電柱36較佳只用銅製成。
請繼續參閱第7圖，半導體元件的堆疊結構100另包含一第二基板40，第二基板40可以為晶片、中介層、電路板或載板，在第二基板40上設置有電路42，一第二導電墊46設於第二基板40上，第二導電墊46電連接電路42，一緩衝層44選擇性地設置在第二基板40上，詳細來說緩衝層44位在第二導電墊46和電路42之間，也就是說電路42和第二導電墊46共同將緩衝層44完全包覆，緩衝層44之彈性係數和第二導電墊46之彈性係數不同，此外緩衝層44也可視情況需要調整其數量，也就是說緩衝層44可以為複數個彼此不相接觸的方式分布於金屬內連線42表面，並且其形狀不限定，舉例而言，緩衝層44之截面可以為圓形、矩形和梯形等。一鍚球54設置於第一基板10和第二基板40之間，其中鍚球54和導電柱36電連結，詳細來說鍚球54係位在導電柱36和第二導電墊46之間，在導電柱36和鍚球54之間可以選擇性地設置有一鎳層(圖未示)。此外，鍚球54中不含有任何緩衝層或是其它異於鍚球54本身的材料，由於錫球本身在高溫為液體狀，在常溫則為比較軟的材質且容易潛變，相較其他導電材料更容易藉由變形來吸收應力，因此於本發明中，錫球不需加緩衝層，然而於其它的情況下，於錫球內也是可以加緩衝層。根據本發明之較佳實施例，緩衝層14/44/114可以為高分子聚合物，例如聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobuten)或聚苯並噁唑(polybenzoxazole)、塑膠或橡膠等，緩衝層14/44/114也可以為導電材料形成的塊狀結構或導電材料形成的多孔、蜂巢狀或網狀結構。此外，鍚球54的材料為鍚混合銀和銅，並且視情況可以選擇性地加入鉛。此外，鍚球54中不含有任何緩衝層或是其它相異於鍚球54的材料。值得注意的是：導電柱36的第二部分362具有一截面，截面包含 如第7圖所示的矩形，也就是說導電柱36為一立方體，或者如第14圖所示的導電柱36，其第二部分362之截面可包含一梯形363，在第14圖中以虛線將導電柱36的第一部分361和第二部分362劃分開來，以協助清楚分辨第一部分361和第二部分362之位置。梯形363較佳為一等腰梯形，也就是說導電柱36為一截頭錐形，梯形363包含一第一底部365和一第二底部367，第二底部367較第一底部365接近鍚球54，第一底部365可以大於第二底部367，也可以如第13圖中所示的第一底部365小於第二底部367。請再度參閱第7圖，緩衝層14/44/114也可視情況需要調整其數量，也就是說緩衝層14/44/114可以為複數個，並且其形狀不限定，舉例而言，緩衝層14/44/114之截面可以為圓形、矩形和梯形等，但較佳地緩衝層114和導電柱36的形狀相同。
第8圖繪示的是根據本發明之第四較佳實施例所繪示的半導體元件的堆疊結構，其中具有相同功能的元件將使用相同符號。第8圖中的半導體元件的堆疊結構和第7圖中的半導體元件的堆疊結構之差異在於：在第8圖中的半導體元件的堆疊結構200，其導電柱36中設置有複數個緩衝層114，並且各個緩衝層114之間互不接觸，此外在第8圖中第一導電墊16和金屬內連線12之間沒有緩衝層，第二導電墊46和電路42之間也沒有緩衝層。第7圖和第8圖中的半導體元件的堆疊結構100/200其最主要的特點在於導電柱36中一定設有緩衝層114，再搭配選擇性設置在第一導電墊14和第二導電墊42下的緩衝層14/42，利用緩衝層14/42/114吸收第一基板10和第二基板40在溫度改變時造成的變形拉扯所產生的應力，如此可以有效降低第一基板10和第二基板40上之材料層剝落的現象。
第11圖和第12圖為根據本發明之第五較佳實施例所繪示的半導體元件的堆疊結構之製作方法，其中具有相同功能的元件將使用相同符號。如第11圖所示，提供一第一基板10，在第一基板10上形成第一導電墊16、保護層18和開口20，第一導電墊16、保護層18和開口20之製作過程大致和第1圖中之步驟相同在此不再贅述。接著在保護層18上形成一光阻層66， 光阻層66具有一開口68曝露出第一導電墊16和部分的保護層18，開口68為一梯形，接著選擇性在第一導電墊16上形成一晶種層(圖未示)，之後以電鍍的方式形成一導電柱36於光阻層66的開口68和保護層18的開口20中，之後移除光阻66，然後在導電柱68上形成一鍚膏(圖未示)。請繼續參閱第11圖，在第五較佳實施例中，另外提供一第二基板40，第二基板40上設有第二導電墊46、保護層48和鍚膏52，其製作方式如同前文第6圖所述，但相異之處在於第11圖中的第二導電墊46和電路42之間沒有緩衝層。如第12圖所示，進行回銲製程，將第一基板10和第二基板上40的鍚膏接觸並且回銲後形成一鍚球54，至此，本發明之一半導體元件的堆疊結構300業已完成。
第12圖繪示的是根據本發明之第六較佳實施例所繪示的半導體元件的堆疊結構，第13圖繪示的是根據本發明之第七較佳實施例所繪示的半導體元件的堆疊結構，其中具有相同功能的元件將使用相同符號。第12圖中的半導體元件的堆疊結構300和第7圖中的半導體元件的堆疊結構100的差異在於：第12圖的導電柱36中、第一基板10和第二基板40上皆沒有設置緩衝層。除此之外，第12圖中的導電柱36分為第一部分361和第二部分362，在保護層18之開口20外的第二部分362為截頭錐形，其中第二部分362具有一截面，截面包含一梯形363，梯形較佳為一等腰梯形，梯形363包含一第一底部365和一第二底部367，第二底部367較第一底部365接近鍚球54，第一底部365可以大於第二底部367，也可以如第13圖中所示的半導體元件的堆疊結構400，其第一底部365小於第二底部367，其餘元件的材料和位置皆和第7圖中的半導體元件的堆疊結構100大致相同，在此不再贅述。在第12圖和第13圖中的半導體元件的堆疊結構特別利用導電柱的截頭錐形的特性，分散第一基板和第二基板在溫度改變時造成的變形拉扯所產生的應力，如此可以有效降低第一基板和第二基板上之材料層剝落的現象。
第14圖繪示的是根據本發明之第八較佳實施例所繪示的半導體元件的堆疊結構，其中具有相同功能的元件將使用相同符號。第14圖中的半導 體元件的堆疊結構500和第12圖中的半導體元件的堆疊結構300的差異在於：第14圖中的導電柱36內設有緩衝層114，第一導電墊16和金屬內連線12間設有緩衝層14以及第二導電墊46和電路42間皆設有緩衝層44。在第14圖中的半導體元件的堆疊結構500不但利用導電柱36的截頭錐形的特性，分散第一基板10和第二基板40在溫度改變時造成的變形拉扯所產生的應力，還加上以緩衝層14/44/114吸收溫度改變時生成的應力，如此可以更有效降低第一基板10和第二基板40上之材料層剝落的現象。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧第一基板
12‧‧‧金屬內連線
14/44/114‧‧‧緩衝層
16‧‧‧導電墊
18/48‧‧‧保護層
20‧‧‧開口
36‧‧‧導電柱
40‧‧‧第二基板
42‧‧‧電路
46‧‧‧第二導電墊
54‧‧‧鍚球
100‧‧‧半導體元件的堆疊結構
361‧‧‧第一部分
362‧‧‧第二部分

Claims (23)

  1. 一種半導體元件的堆疊結構，包含：一第一基板；一第一導電墊設於該第一基板上；一導電柱接觸該第一導電墊；以及至少一第一緩衝層設於該導電柱內部，其中該導電柱包覆該第一緩衝層，該第一緩衝層之彈性係數和該導電柱之彈性係數不同；一第二基板；一第二導電墊設於該第二基板上；以及一鍚球設置於該第二基板和該第一基板之間，其中該鍚球和該導電柱電連結。
  2. 如請求項1所述之半導體元件的堆疊結構，另包含一第二緩衝層設於該第一基板上，其中該第一導電墊覆蓋該第二緩衝層，該第二緩衝層之彈性係數和該第一導電墊之彈性係數不同。
  3. 如請求項2所述之半導體元件的堆疊結構，其中該第二緩衝層包含聚醯亞胺、苯並環丁烯或聚苯並噁唑。
  4. 如請求項1所述之半導體元件的堆疊結構，另包含一第三緩衝層設於該第二基板上，其中該第二導電墊覆蓋該第三緩衝層，該第三緩衝層之彈性係數和該第二導電墊之彈性係數不同。
  5. 如請求項4所述之半導體元件的堆疊結構，其中該第三緩衝層包含聚醯亞胺、苯並環丁烯或聚苯並噁唑。
  6. 如請求項1所述之半導體元件的堆疊結構，其中該第一緩衝層包含聚醯亞胺、苯並環丁烯或聚苯並噁唑。
  7. 如請求項1所述之半導體元件的堆疊結構，其中該導電柱包含一第一部分和一第二部分，該第二部分具有一截面，該截面包含一矩形或一梯形。
  8. 如請求項7所述之半導體元件的堆疊結構，其中該梯形具有一第一底部和一第二底部，該第二底部較該第一底部接近該鍚球。
  9. 如請求項8所述之半導體元件的堆疊結構，其中該第一底部大於該第二底部。
  10. 如請求項8所述之半導體元件的堆疊結構，其中該第一底部小於該第二底部。
  11. 如請求項7所述之半導體元件的堆疊結構，另包含一保護層覆蓋該第一導電墊，其中該保護層中包含一開口，該導電柱的該第一部分位在該開口中，並且該第一部分接觸該第一導電墊，該導電柱的該第二部分位在該開口之外。
  12. 如請求項1所述之半導體元件的堆疊結構，另包含複數個該第一緩衝層設置於該導電柱內部。
  13. 如請求項1所述之半導體元件的堆疊結構，其中該第一基板包含晶片、中介層、電路板或載板，該第二基板包含晶片、中介層、電路板或載板。
  14. 一種半導體元件的堆疊結構，包含： 一第一基板；一第一導電墊設於該第一基板上；以及一導電柱接觸該第一導電墊，其中該導電柱包含一截頭錐形；一第二基板；一第二導電墊設於該第二基板上；以及一鍚球設置於該第二基板上，其中該鍚球和該導電柱電連結。
  15. 如請求項14所述之半導體元件的堆疊結構，其中該導電柱包含一第一部分和一第二部分，該第二部分包含該截頭錐形，並且該第二部分具有一截面，該截面包含一梯形。
  16. 如請求項15所述之半導體元件的堆疊結構，其中該截面具有一第一底部和一第二底部，該第二底部較該第一底部接近該鍚球。
  17. 如請求項16所述之半導體元件的堆疊結構，其中該第一底部大於該第二底部。
  18. 如請求項16所述之半導體元件的堆疊結構，其中該第一底部小於該第二底部。
  19. 如請求項15所述之半導體元件的堆疊結構，另包含一保護層覆蓋該第一導電墊，其中該保護層中包含一開口，該導電柱的該第一部分位在該開口中，並且該第一部分接觸該第一導電墊，該導電柱的該第二部分位在該開口之外。
  20. 如請求項14所述之半導體元件的堆疊結構，另包含至少一第一緩衝層設於該導電柱內部，其中該導電柱包覆該第一緩衝層，該第一緩衝層之彈性係數和該導電柱之彈性係數不同。
  21. 如請求項20所述之半導體元件的堆疊結構，其中該第一緩衝層包含聚醯亞胺、苯並環丁烯或聚苯並噁唑。
  22. 如請求項14所述之半導體元件的堆疊結構，另包含一第二緩衝層設於該第一基板上，其中該第一導電墊覆蓋該第二緩衝層，其中該第二緩衝層包含聚醯亞胺、苯並環丁烯或聚苯並噁唑。
  23. 如請求項14所述之半導體元件的堆疊結構，另包含一第三緩衝層設於該第二基板上，其中該第二導電墊覆蓋該第三緩衝層，其中該第三緩衝層包含聚醯亞胺、苯並環丁烯或聚苯並噁唑。
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