CN1992246A - 复合凸块 - Google Patents

复合凸块 Download PDF

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CN1992246A
CN1992246A CNA2005101352827A CN200510135282A CN1992246A CN 1992246 A CN1992246 A CN 1992246A CN A2005101352827 A CNA2005101352827 A CN A2005101352827A CN 200510135282 A CN200510135282 A CN 200510135282A CN 1992246 A CN1992246 A CN 1992246A
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elastic body
composite projection
weld pad
projection according
layer
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林基正
林耀生
张世明
陆苏财
郑仙志
陈泰宏
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Industrial Technology Research Institute ITRI
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Priority to CNA2005101352827A priority Critical patent/CN1992246A/zh
Priority to US11/308,180 priority patent/US7378746B2/en
Publication of CN1992246A publication Critical patent/CN1992246A/zh
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Abstract

本发明提出一种复合凸块,其适于设置在基板的焊垫上。此复合凸块主要包括弹性主体以及外导电层,其中弹性主体的热膨胀系数介于5ppm/℃与200ppm/℃之间,而外导电层覆盖弹性主体,并与焊垫电连接。复合凸块内的弹性主体可在接合时提供应力缓冲的效果,且由于弹性主体的热膨胀系数位于较佳的范围内,因此有助于降低热应力的作用,进而提高接合效果。

Description

复合凸块
技术领域
本发明涉及一种电子封装元件间的接合结构,且特别涉及一种可提供良好接合特性的凸块结构。
背景技术
在高密度的电子封装技术中,如何提高集成电路元件与载板之间的接合效果,提高工艺合格率,一直是相当重要的研究课题。
以液晶显示器(Liquid Crystal Display,LCD)为例,基于高图像分辨率的需求以及电子产品的轻薄短小化,液晶显示器的封装技术也由载芯片板技术(Chip On Board,COB)转变为柔性带自动连接技术(Tape AutomatedBonding,TAB),再演进为现今的微间距(fine pitch)的玻璃覆晶封装技术(Chip On Glass,COG)。
然而,公知应用凸块的封装工艺中,由于芯片与载板之热膨胀系数(coefficient of thermal expansion,CTE)的差异甚大,因此当芯片与载板接合后,往往会因为芯片、凸块、载板之间的热膨胀系数不匹配(CTE mismatch),而产生翘曲(warpage)的现象,并使得凸块受到热应力(thermal stress)的作用。更甚者,随着集成电路之集成度的增加,上述热应力与翘曲对接合效果的影响也日渐严重,其结果将导致芯片与载板之间的可靠度(reliability)下降,并且造成信赖性测试的失败。
K.Hatada在美国专利第4,749,120号中便提出了以金凸块作为芯片与基板之间的电连接,同时以树脂(resin)作为两者之间的接着剂。然而,由于金属的杨氏模量(Young’s modulus)比树脂高出许多,因此在将芯片与载板接合,并对树脂进行固化(curing)时,必须施以相当大的接触应力(contactstress),且在接合完成后,金凸块也会相对受到较大的剥离应力(peelingstress)作用,而可能自芯片或载板上剥离。
另一种方法是由Y.Tagusa等人在美国专利第4,963,002号中提出,其主要是利用镀镍(镍)的小球(beads)或银颗粒来达到电连接的目的。然而,此种方法的接合面积较小,且若采用银颗粒进行接合,仍然会因为银的杨氏模量较大,而发生上述凸块剥离的问题。
此外,Sokolovsky等人在美国专利第4,916,523号中提出一种通过单向(unidirectional)的导电接着剂来接合芯片与载板的方法。另外,Brady等人提出的美国专利第5,134,460提出了在导电金属凸块上涂布金层的设计。
发明内容
鉴于上述情况,本发明的目的之一便是要解决电子封装中因为热膨胀系数不匹配而产生之热应力的问题。
本发明之另一目的便是针对杨氏模量作用而导致凸块接合不良的问题进行改善,以提高工艺合格率。
为达上述或是其它目的,本发明提出一种复合凸块,其适于设置在基板的焊垫上。此复合凸块主要包括弹性主体以及外导电层,其中弹性主体的热膨胀系数介于5ppm/℃与200ppm/℃之间,而外导电层覆盖弹性主体,并与焊垫电连接。
在本发明之一实施例中,弹性主体的杨氏模量例如是介于0.1GPa与2.8GPa之间,或是介于3.5GPa与20GPa之间。
在本发明之一实施例中,弹性主体的材质可以是高分子材料。举例而言,弹性主体的材质例如是聚酰亚胺(polyimide)或是环氧基高分子材料(epoxy base polymer)。
在本发明之一实施例中,复合凸块例如还包括焊料层,其设置于外导电层上。其中,焊料层的材质例如是锡铅焊料。
在本发明之一实施例中,弹性主体例如是块状,并设置于焊垫上,其中弹性主体远离焊垫的表面可以是平面、粗糙面或曲面。
在本发明之一实施例中,弹性主体例如是由多个突起物所构成。其中,突起物例如可以全部设置于焊垫上,或是全部设置于焊垫外围。此外,亦可以有部分突出物设置于焊垫上,而其余突出物设置于焊垫外围。
在本发明之一实施例中,复合凸块还包括基底导电层,其设置于弹性主体与基板之间,且外导电层连接基底导电层。其中,弹性主体例如是呈块状,并延伸至焊垫外。此外,弹性主体远离焊垫的表面可以是平面、粗糙面或曲面,而基底导电层的材质例如是金属。
基于上述,本发明之复合凸块内的弹性主体可在接合时提供应力缓冲的效果,且本发明调整弹性主体的热膨胀系数,并可搭配弹性主体的杨氏模量进行设计,因此有助于降低热应力的作用,提高接合效果。
为让本发明的上述和其它目的、特征和优点能更明显易懂,下文特举本发明之较佳实施例,并配合附图,作详细说明如下。
附图说明
图1A与1B分别为本发明之较佳实施例之复合凸块,其设置在基板上的示意图。
图2为弹性主体之热膨胀系数与翘曲量的关系曲线。
图3为弹性主体之热膨胀系数与接触应力的关系曲线。
图4为弹性主体之热膨胀系数与剥离应力的关系曲线。
图5为弹性主体之杨氏模量与翘曲量的关系曲线。
图6为弹性主体之杨氏模量与接触应力的关系曲线。
图7为弹性主体之杨氏模量与剥离应力的关系曲线。
图8为整合弹性主体之材料参数(包括热膨胀系数与杨氏模量)对于接合效果的分析表。
图9为本发明之一种半球状的复合凸块。
图10为本发明之一种具有粗糙表面的复合凸块。
图11~13为本发明之一种具有多个突起的复合凸块。
图14A~14I依次表示本发明之一种复合凸块的制造方法。
图15A~15J依次表示本发明具有基底导电层之复合凸块的制造方法。
图16~18为本发明其它几种具有基底导电层之不同形态的复合凸块。
主要元件标记说明
26:焊垫
28:保护层
30:基底
32:弹性主体、弹性材料层
36:外导电(材料)层
38:基底导电(材料)层
40:光刻胶
52:焊料层
具体实施方式
本发明所揭示的复合凸块例如可以设置于芯片上或是任何适用的载板,如线路板或胶卷式卷带(tape)上,而以下实施例以基板通称之。此外,为了简化图示,下述实施例以相同的标记表示相同的构件。
图1A与1B分别为本发明之较佳实施例之复合凸块,其设置在基板上的示意图。如图1A与1B所示,基板30上具有焊垫26和保护层28,其中焊垫26直径例如约为90μm。弹性主体32设置于焊垫26上,其中弹性主体32的厚度约介于5μm至25μm之间。在本实施例中,弹性主体32的材质例如是高分子材料,包括聚酰亚胺(polyimide)、环氧基高分子材料(epoxy base polymer)等。当然,在本发明之其它实施例中,亦可以选用具有相同性质的材质来制造弹性主体32。
此外,外导电层36覆盖弹性主体32,其中外导电层36的材质可以是铝、镍等金属材质或是镍/金、铬/金、铬/银、钛/铂等合金材质。当然,外导电层36也可以是由黏着(adhesion)层/阻障(barrier)层/导体(conductor)层所构成的复合层,例如是铬/铜/金、铬/镍/金、铬/银/金、钛/铂/金、钛/钯/金或钛/钨/银等。请参照图1B,若考虑搭配焊料(solder)进行接合,则外导电层36上还例如可设置焊料层52,例如锡铅(PbSn)、铟镓(InGa)或铟锡(InSn)等焊料。
本发明为了避免因热膨胀系数不匹配(CTE mismatch)所造成的热应力,对弹性主体32的热膨胀系数进行设计。请分别参照图2~4,其中图2为弹性主体32之热膨胀系数与翘曲量的关系曲线,图3为弹性主体32之热膨胀系数与接触应力的关系曲线,而图4为弹性主体32之热膨胀系数与剥离应力的关系曲线。由图2~4中可以观察到,若要降低翘曲量,则弹性主体32应选用热膨胀系数较小的材质;若要提高接触应力,以增进接合强度,则弹性主体32应选用热膨胀系数较小的材质;然而若要降低剥离应力,以避免接合效果遭受破坏,则弹性主体32应选用热膨胀系数较大的材质。基于上述的分析,本发明特别将弹性主体32的热膨胀系数设定在一个较佳的范围:5ppm/℃与200ppm/℃之间,以得到较佳的接合效果。其中,最佳之热膨胀系数的范围应介于10ppm/℃与150ppm/℃之间。
另外,由于弹性主体32的杨氏模量也会对接合效果造成影响,因此为了达到最佳化的设计,本发明还可搭配对于弹性主体32之杨氏模量的选择,以进一步提高接合效果。请分别参照图5~7,其中图5为弹性主体32之杨氏模量与翘曲量的关系曲线,图6为弹性主体32之杨氏模量与接触应力的关系曲线,而图7为弹性主体32之杨氏模量与剥离应力的关系曲线。由图5~7中可以观察到,若要降低翘曲量,则弹性主体32应选用杨氏模量较小的材质;若要提高接触应力,则选用杨氏模量较大的弹性主体32;而若要降低剥离应力,则弹性主体32应选用杨氏模量较小的材质。
图8即表示整合上述弹性主体32之材料参数(包括热膨胀系数与杨氏模量)对于接合效果的分析表。搭配上述所选用的较佳热膨胀系数范围,并考虑到弹性主体32的杨氏模量对接合效果的影响,本发明所选用之弹性主体32的杨氏模量可以介于0.1GPa与2.8GPa之间,以及介于3.5GPa与20GPa之间。其中,选用杨氏模量介于0.1GPa与2.8GPa之间的弹性主体32,虽然接触应力较小,但相对可降低翘曲量与剥离应力。此外,选用杨氏模量介于3.5GPa与20GPa之间的弹性主体32,可增加接触应力,提高接合强度。因此,本发明可以通过对于弹性主体32之杨氏模量选择,而在接触应力与相应的剥离应力之间取得较佳的平衡。
除了图1A与1B所示的复合凸块之外,本发明还可提出其它具有不同形状或设置方式的复合凸块。图9~13为本发明其它多种不同形态的复合凸块。图9为一种半球状(hemispherical)的复合凸块,其中弹性主体32远离焊垫26的表面例如是曲面。图10为一种具有粗糙表面的复合凸块,其中弹性主体32远离焊垫26的表面例如是粗糙面(rough surface)。图11为具有多个突起的复合凸块,其中弹性主体32是由多个突起物所构成,且突起物是设置于焊垫26上。图12与13同样为具有多个突起的复合凸块,但图12的突起物是同时设置于焊垫26上以及焊垫26外围,而图13的突起物皆设置于焊垫26外围。
为了更清楚说明本发明之特征,图14A~14I依次表示上述实施例之复合凸块的其中一种制造方法。首先,如图14A所示,提供具有焊垫26与保护层28之基板30,其中焊垫26的直径例如是90μm,且焊垫26表面已经过蚀刻(etch)、清洗(clean)等步骤。
接着,如图14B所示,在基板30上形成弹性材料层32,其例如是前述实施例所提及的高分子材料。并且,在本实施例中,弹性材料层32为非感旋光性(nonphotosensitive)的材料,例如非感旋光性的聚酰亚胺或环氧基高分子材料,其厚度例如是介于5~25μm之间。
然后,如图14C所示,在焊垫26上方的弹性材料层32上形成图案化的光刻胶层40,并且如图14D所示,通过光刻胶层40为掩膜(mask),对弹性材料层32进行蚀刻工艺,以形成弹性主体32。其中,对于弹性材料层32的蚀刻工艺可以参照Wilson,Stenzenberger与Hergenrother所著之《POLYIMIDES》一书中之第8章的描述。
接着,如图14E所示移除光刻胶层40,并如图14F所示,在基板30上全面形成外导电材料层36,其例如是铬/金合金层,包括厚度为500埃(Angstroms)的铬层,以及厚度为2000埃的金层。外导电材料层36也可以是铝、镍等单层的金属层,或是镍/金、铬/银、钛/铂等合金层。另外,外导电材料层36还可以是由黏着层/阻障层/导体层所构成的复合层,例如是铬/铜/金、铬/镍/金、铬/银/金、钛/铂/金、钛/钯/金或钛/钨/银等。
之后,如图14G所示,在外导电材料层36上形成另一图案化的光刻胶层40,并如图14H所示以光刻胶层40作为掩膜对外导电材料层36进行蚀刻,而形成外导电层36。然后,如图14I所示,移除光刻胶层40,而得到复合凸块。
上述实施例中的复合凸块还可包括基底导电层38(如图15J所示),其设置于弹性主体32与基板30之间,并可延伸至焊垫26外围的保护层28上,使得弹性主体32可延伸至焊垫26外,而覆盖弹性主体32的外导电层36会与基底导电层38连接。其中,基底导电层38的材质例如是铝。
以下将针对此具有基底导电层38之复合凸块的工艺进行说明,请依次参照图15A~15J所示的制造流程,其中对于相同构件的说明(例如材质、厚度或工艺参数)请参照上述实施例,下文中不再重复赘述。首先,如图15A所示,提供具有焊垫26与保护层28之基板30,并如图15B所示在基板30上形成基底导电材料层38,其材质例如是铝等金属材质或是其它导电材质。接着,便可如图15C~15I所示,进行如同上述实施例之弹性主体32与外导电层36的制造步骤。其中,如图15H与15I所示在蚀刻导电材料层36的同时,也对基底导电材料层38进行蚀刻,而在移除光刻胶层40之后,形成如图15J所示之复合凸块。
上述实施例所揭示的是以非感旋光性材料制造弹性主体的方法,当然本发明还例如可采用感旋光性材料来制造弹性主体,其中由于大部分的步骤已在前述实施例详细说明,因此将不再赘述。
下文还举出本发明几种具有基底导电层之不同形态的复合凸块,其中图16为外导垫层36上还形成有焊料层52的复合凸块,图17为弹性主体32远离焊垫26之表面为曲面的复合凸块,而图18为弹性主体32远离焊垫26之表面为粗糙面的复合凸块。关于这些实施例之构件的材质、厚度与形成方法请参照前述多个实施例,在此不再赘述。
综上所述,本发明主要提出一种复合凸块,其具有弹性主体用以提供应力缓冲的效果,且由于弹性主体的热膨胀系数介于较佳的范围,因此还可大幅降低热应力的作用,提高接合效果。此外,本发明还可对弹性主体的杨氏模量进行设计,以在接合时所需的接触应力与对应的剥离应力之间取得较佳的平衡,进而提高工艺合格率。另外,本发明还可改变复合凸块的形状、位置等,以达到最佳化的设计。
虽然本发明已以较佳实施例披露如上,然其并非用以限定本发明,任何所属技术领域的技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与改进,因此本发明的保护范围当视权利要求所界定者为准。

Claims (19)

1.一种复合凸块,适于设置在基板的焊垫上,其特征是该复合凸块包括:
弹性主体,其中该弹性主体的热膨胀系数介于5ppm/℃与200ppm/℃之间;以及
外导电层,覆盖该弹性主体,并与该焊垫电连接。
2.根据权利要求1所述之复合凸块,其特征是该弹性主体的杨氏模量介于0.1GPa与2.8GPa之间。
3.根据权利要求1所述之复合凸块,其特征是该弹性主体的杨氏模量介于3.5GPa与20GPa之间。
4.根据权利要求1所述之复合凸块,其特征是该弹性主体的材质包括高分子材料。
5.根据权利要求4所述之复合凸块,其特征是该弹性主体的材质包括聚酰亚胺。
6.根据权利要求4所述之复合凸块,其特征是该弹性主体的材质包括环氧基高分子材料。
7.根据权利要求1所述之复合凸块,其特征是还包括焊料层,其设置于该外导电层上。
8.根据权利要求7所述之复合凸块,其特征是该焊料层的材质包括锡铅焊料。
9.根据权利要求1所述之复合凸块,其特征是该弹性主体呈块状,并设置于该焊垫上。
10.根据权利要求9所述之复合凸块,其特征是该弹性主体远离该焊垫的表面为粗糙面。
11.根据权利要求9所述之复合凸块,其特征是该弹性主体远离该焊垫的表面为曲面。
12.根据权利要求1所述之复合凸块,其特征是该弹性主体由多个突起物所构成。
13.根据权利要求12所述之复合凸块,其特征是上述这些突起物设置于该焊垫上或设置于该焊垫外围。
14.根据权利要求12所述之复合凸块,其特征是部分突出物设置于该焊垫上,而其余突出物设置于该焊垫外围。
15.根据权利要求1所述之复合凸块,其特征是还包括基底导电层,其设置于该弹性主体与该基板之间,且该外导电层连接该基底导电层。
16.根据权利要求15所述之复合凸块,其特征是该弹性主体呈块状,并延伸至该焊垫外。
17.根据权利要求16所述之复合凸块,其特征是该弹性主体远离该焊垫的表面为粗糙面。
18.根据权利要求16所述之复合凸块,其特征是该弹性主体远离该焊垫的表面为曲面。
19.根据权利要求15所述之复合凸块,其特征是该基底导电层的材质包括金属。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101582399B (zh) * 2008-05-13 2011-02-09 台湾薄膜电晶体液晶显示器产业协会 接点结构与接合结构
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US20080017981A1 (en) * 2006-05-26 2008-01-24 Nano-Proprietary, Inc. Compliant Bumps for Integrated Circuits Using Carbon Nanotubes
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Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508228A (en) * 1994-02-14 1996-04-16 Microelectronics And Computer Technology Corporation Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
US5707902A (en) * 1995-02-13 1998-01-13 Industrial Technology Research Institute Composite bump structure and methods of fabrication
TW324847B (en) 1996-12-13 1998-01-11 Ind Tech Res Inst The structure of composite bump
US6337445B1 (en) * 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US7524617B2 (en) * 2004-11-23 2009-04-28 E.I. Du Pont De Nemours And Company Low-temperature curable photosensitive compositions

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