CN1750258A - 包括混合金凸点的微电子器件芯片及其封装、应用和制造 - Google Patents

包括混合金凸点的微电子器件芯片及其封装、应用和制造 Download PDF

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CN1750258A
CN1750258A CNA2005101039194A CN200510103919A CN1750258A CN 1750258 A CN1750258 A CN 1750258A CN A2005101039194 A CNA2005101039194 A CN A2005101039194A CN 200510103919 A CN200510103919 A CN 200510103919A CN 1750258 A CN1750258 A CN 1750258A
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salient point
cyanogen
coating
chip
microelectronic device
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CN100479140C (zh
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朴炯建
张宇镇
金荣浩
文泰成
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明涉及包括混合金凸点的微电子器件芯片及其封装、应用和制造。本发明提供一种包括混合Au凸点的微电子器件芯片，其中在电芯片筛选(EDS)测试中在探针尖处不产生异物。该微电子器件芯片包括芯片焊盘，其连接到形成在衬底上的微电子器件，其上的微电子器件与芯片外部电接触。另外，微电子器件芯片包括形成在芯片焊盘上、由包括两层或更多层的复合层构成的凸点。

Description

包括混合金凸点的微电子器件芯片及其封装、应用和制造
技术领域
本发明涉及包括混合金(Au)凸点的微电子器件芯片、该微电子器件芯片的封装、包括该微电子器件芯片的液晶显示(LCD)装置及制造该微电子器件芯片的方法。
背景技术
随着技术的快速发展和朝向可移动性的转移，诸如便携式电话、个人数字助理(PDA)、例如LCD装置的平板显示器、及笔记本计算机的电子装置已经发展为薄、轻、小。因此，安装于这些电子装置中的芯片已经被开发成为微型。导电凸点已经广泛用作将芯片封装连接到外部电子器件的手段。
近来，该导电凸点主要利用涉及无氰系列镀液(non-cyan series platingsolution)的电镀方法(electrolytic plating method)形成。以前使用氰系列镀液(cyan series plating solution)；然而，近来主要使用无氰系列镀液。与使用包括KAu(CN)2的氰系列镀液相比，在使用包括Na3Au(SO3)2的无氰系列镀液形成导电凸点的情况中，所完成的凸点的表面不粗糙，而是具有精细结构(fine structure)，使得易于进行后续的结合工艺。另外，由于不产生如HCN的有毒气体，所以能够减小环境污染并获得安全的工作环境。
对形成在晶片上的微电子器件进行电测试-被称为电芯片筛选(EDS)测试，从而检查芯片的质量。通过将探针尖与电连接微电子器件的导电凸点接触，然后通过该探针尖将电信号传送到该微电子器件来进行EDS测试。
在导电凸点利用无氰系列镀液形成的情况中，由导电凸点产生的异物(foreign material)粘附到探针尖上，由此在EDS测试的电信号中经常产生错误。这些异物导致错误的测试结果，其中正常的芯片被认为短路或开路。而且，异物改变探针尖与导电凸点之间的接触电阻，由此产生错误的测试结果。
为解决上述问题，每当进行芯片测试时，需要清洁探针尖。即，在测试20-50个芯片后，必须进行探针尖清洁工艺。这导致探针尖磨损，增加生产成本。而且，EDS测试时间增加，由此导致生产率下降。
发明内容
为解决上述问题，本发明的一个特征是提供一种包括混合Au凸点的微电子器件芯片，该混合Au凸点在电芯片筛选(EDS)测试中不在探针尖中产生异物。
本发明的另一特征是提供一种包括该微电子器件芯片的封装。
本发明的又一特征是提供一种包括该微电子器件芯片的液晶显示(LCD)装置。
本发明的另一特征是提供一种制造该微电子器件芯片的方法。
通过下面的描述，本发明的上述特征及其它特征和优点对于本领域的技术人员来说将变得清楚。
根据第一方面，本发明涉及一种微电子器件芯片，包括：芯片焊盘，其连接到形成在衬底上的微电子器件上，从而使所述微电子器件与所述芯片的外部电接触；及凸点，其形成在芯片焊盘上并包括复合层，所述复合层包括两层或更多层。
在一个实施例中，所述凸点为混合Au凸点，其中堆叠氰Au镀层和无氰Au镀层。在一个实施例中，所述混合Au凸点具有1-20μm范围内的厚度。在一个实施例中，所述氰Au镀层的厚度及所述无氰Au镀层的厚度不小于0.5μm。在一个实施例中，所述混合Au凸点的所述氰Au镀层位于所述芯片焊盘上，并且所述混合Au凸点的所述无氰Au镀层位于所述氰Au镀层上。在一个实施例中，所述混合Au凸点的所述无氰Au镀层位于所述芯片焊盘上，并且所述混合Au凸点的所述氰Au镀层位于所述无氰Au镀层上。
根据另一方面，本发明涉及一种微电子器件芯片，包括芯片焊盘，其连接到形成在衬底上的微电子器件上，从而使所述微电子器件与所述芯片的外部电接触。钝化层保护所述微电子器件并暴露所述芯片焊盘。凸点形成在由所述钝化层暴露的芯片焊盘上并包括复合层，所述复合层包括两层或更多层。凸点下部导电层形成在所述芯片焊盘与所述凸点之间，从而防止所述芯片焊盘与所述凸点之间的相互扩散，并改善所述芯片焊盘与所述凸点之间的附着。
在一个实施例中，所述凸点为混合Au凸点，其中堆叠氰Au镀层和无氰Au镀层。在一个实施例中，所述混合Au凸点具有1-20μm范围内的厚度。
在一个实施例中，所述氰Au镀层的厚度及所述无氰Au镀层的厚度不小于0.5μm。在一个实施例中，所述混合Au凸点的所述氰Au镀层位于所述芯片焊盘上，并且所述混合Au凸点的所述无氰Au镀层位于所述氰Au镀层上。在一个实施例中，所述混合Au凸点的所述无氰Au镀层位于所述芯片焊盘上，并且所述混合Au凸点的所述氰Au镀层位于所述无氰Au镀层上。
在一个实施例中，所述凸点下部导电层由TiW、Cr、Cu、Ti、Ni、NiV、Pd、Cr/Cu、TiW/Cu、TiW/Au及NiV/Cu中的至少一种形成。在一个实施例中，所述凸点下部导电层具有包括0.005-0.5μm厚的TiW和0.005-0.5μm厚的Au的堆叠结构。
在一个实施例中，所述混合Au凸点具有一个或更多氰Au镀层与一个或更多无氰Au镀层交替堆叠的结构。
根据另一方面，本发明涉及一种封装，其包括根据上面所列的任意一种的微电子器件芯片、以及带布线板(tape wiring board)，所述带布线板包括由外部连接端子和电连接所述微电子器件芯片的凸点的内部连接端子构成的布线。
根据另一方面，本发明涉及一种液晶显示装置，包括根据上面所列的任意一种的微电子器件芯片、以及其中形成有用于连接到所述微电子器件芯片的布线的液晶显示面板组件；其中所述微电子器件芯片的凸点电连接到所述布线。
在一个实施例中，所述微电子芯片利用玻璃上芯片(COG)方法、带载封装(TCP)方法和膜上芯片(COF)方法中的一种连接到该液晶显示面板组件上。
根据另一方面，本发明涉及一种制造微电子器件芯片的方法，包括：制备芯片焊盘，其连接到形成在衬底上的微电子器件上，从而使所述微电子器件与所述芯片的外部电接触；及形成凸点，其形成在芯片焊盘上，并包括复合层，所述复合层包括两层或更多层。
在一个实施例中，所述凸点的形成包括于所述芯片焊盘上形成其中堆叠氰Au镀层和无氰Au镀层的混合Au凸点。在一个实施例中，所述凸点利用电镀方法形成。在一个实施例中，所述氰Au镀层利用KAu(CN)2系列镀液形成，并且所述无氰Au镀层利用Na3Au(SO3)2系列镀液形成。在一个实施例中，所述混合Au凸点具有1-20μm范围内的厚度。在一个实施例中，所述氰Au镀层的厚度及所述无氰Au镀层的厚度不小于0.5μm。
在一个实施例中，所述凸点的形成包括在所述芯片焊盘上形成所述氰Au镀层，然后在其上形成所述无氰Au镀层。
在一个实施例中，所述凸点的形成包括在所述芯片焊盘上形成所述无氰Au镀层，然后在其上形成所述氰Au镀层。
在一个实施例中，所述方法还包括在形成所述凸点后进行热处理。在一个实施例中，在氧气和氮气环境中的一种中在250-360℃范围内的温度进行所述热处理。
根据另一方面，本发明涉及一种制造微电子器件芯片的方法，包括：形成暴露芯片焊盘的钝化层；在所得结构上形成凸点下部导电层；在所述凸点下部导电层上形成非导电层图案，其限定将要形成凸点的区域；利用所述非导电层图案作为掩模在凸点下部导电层上形成所述凸点，其由包括两层或更多层的复合层构成；及去除所述非导电层图案。
在一个实施例中，所述凸点的形成包括形成氰Au镀层和无氰Au镀层堆叠于其中的混合Au凸点。在一个实施例中，所述凸点的形成利用电镀方法进行。在一个实施例中，所述氰Au镀层利用KAu(CN)2系列镀液形成，并且所述无氰Au镀层利用Na3Au(SO3)2系列镀液形成。在一个实施例中，所述混合Au凸点具有1-20μm范围内的厚度。在一个实施例中，所述氰Au镀层的厚度及所述无氰Au镀层的厚度不小于0.5μm。在一个实施例中，所述凸点的形成包括在所述芯片焊盘上形成所述氰Au镀层，然后在其上形成所述无氰Au镀层。在一个实施例中，所述凸点的形成包括在所述芯片焊盘上形成所述无氰Au镀层，然后在其上形成所述氰Au镀层。
在一个实施例中，所述凸点下部导电层的形成包括利用TiW、Cr、Cu、Ti、Ni、NiV、Pd、Cr/Cu、TiW/Cu、TiW/Au及NiV/Cu中的一种形成所述凸点下部导电层。在一个实施例中，所述凸点下部导电层的形成包括通过依次溅射TiW和Au形成具有TiW/Au结构的所述凸点下部导电层。在一个实施例中，所述凸点下部导电层形成为具有TiW/Au结构，其中堆叠0.005-0.5μm厚的TiW和0.005-0.5μm厚的Au。
在一个实施例中，所述方法还包括在去除所述非导电层图案之后，利用所述混合Au凸点作为掩模去除所述凸点下部导电层。在一个实施例中，所述方法还包括在去除所述凸点下部导电层之后进行热处理。在一个实施例中，在氧气和氮气环境中的一种中在250-360℃范围内的温度进行所述热处理。
在一个实施例中，所述非导电层图案是光致抗蚀剂图案。
附图说明
从如附图所示的本发明的优选方面的更具体的描述中，本发明的上述和其它特征及优点将变得明显，附图中相同的附图标记在不同视图中表示相同的部件。图不必按比例，相反，重点在于示出本发明的原理。为清晰起见，图中层的厚度和区域被放大。
图1至图8为截面图，示出制造根据本发明一实施例的液晶显示器驱动集成电路(LDI)芯片的方法；
图9A至9C为根据本发明一实施例的形成在LDI芯片上的混合Au凸点的扫描电子显微镜(SEM)图像；
图10为曲线图，示出根据本发明一实施例的混合Au凸点的X射线衍射(XRD)峰；
图11是探针尖的表面的SEM图像，示出进行电芯片筛选(EDS)测试后探针尖的污染程度；
图12为截面图，示出制造根据本发明另一实施例的LDI芯片的方法；
图13A为LCD(液晶显示器)面板组件的平面图，其上利用玻璃上芯片(COG)方法安装了根据本发明一实施例的LDI芯片；
图13B为沿图13A的线B-B’截取的截面图；
图14为带布线板(tape wiring board)的平面图，其上安装了根据本发明不同实施例的LDI芯片；
图15为带载封装(TCP)的截面图，其上安装了根据本发明一实施例的LDI芯片；
图16为膜上芯片(COF)封装的截面图，其上安装了根据本发明一实施例的LDI芯片；
图17为LCD面板组件的示意图，其中以COF封装的形式安装了根据本发明实施例的LDI芯片。
具体实施方式
现在将参照附图更充分地描述本发明，附图中示出了本发明的优选实施例。
现在将参照作为微电子器件芯片(以下简单地称为芯片)的液晶显示器驱动集成电路(LDI)芯片给出说明，其中凸点的特性通过示例的方式描述。
参照图1至8描述制造LDI芯片的方法，该芯片包括根据本发明一实施例的混合Au凸点结构。图1至图8为截面图，示出制造根据本发明一实施例的LDI芯片的方法。
参照图1，在晶片层次上制备衬底100。微电子器件(未示出)及连接至微电子器件并由最上层互连形成的芯片焊盘110形成在衬底100上。微电子器件与芯片外部之间的电接触通过芯片焊盘110实现。芯片焊盘110可由诸如金属的导电材料形成。优选地，芯片焊盘110由铝或铜形成。
保护微电子器件并暴露芯片焊盘110的钝化层120形成在衬底100上。为实现芯片焊盘110中的电接触，优选的是，钝化层120在芯片焊盘110的上面部分上具有预定开口。钝化层120的开口可利用掩模通过光刻蚀刻工艺(photolithographic etching process)形成。
然后，如图2所示，凸点下部导电层130形成在其上形成了钝化层120的衬底100上。直接在铝或铜芯片焊盘110上形成凸点(例如混合Au凸点)是困难的，因此形成凸点下部导电层130。另外，凸点下部导电层130能在防止芯片焊盘110与上部互连之间的相互扩散中起作用。因此，优选的是，凸点下部导电层130与芯片焊盘110和钝化层120具有良好附着，从而最小化作用到衬底100上的应力并用作扩散阻挡层。此外，凸点下部导电层130与芯片焊盘110之间的低电阻是优选的。因此，凸点下部导电层130使用TiW、Cr、Cu、Ti、Ni、NiV、Pd、Cr/Cu、TiW/Cu、TiW/Au或NiV/Cu通过蒸镀、溅射、电镀或化学镀形成。在本发明的一实施例中，TiW和Au依次通过溅射方法沉积，于是形成TiW/Au结构凸点下部导电层130。然而，本发明不限于此。凸点下部导电层130可通过各种制造工艺由各种材料制成。TiW层可用作芯片焊盘110与上部互连之间的扩散阻挡层。另外，Au层增加芯片焊盘110与凸点之间的附着力，并能用作后续的用于形成上部互连的电镀工艺中的籽层(seed 1ayer)。
在本发明的一实施例中，凸点下部导电层130可形成至0.01-1μm的厚度。如果凸点下部导电层130太薄，凸点下部导电层130的功能不能良好完成。另外，如果凸点下部导电层130太厚，电阻增加。例如，具有0.005-0.5μm厚度的TiW层或具有0.005-0.5μm厚度的Au层可形成为凸点下部导电层130。
然后，如图3所示，非导电层140形成在凸点下部导电层130上。任何具有下述功能的绝缘材料可用作非导电层140。即，在后续用于形成混合Au凸点的电镀工艺(参见图5和6)中，通过阻挡电流流至凸点下部导电层130，该绝缘材料防止在除了凸点下部导电层130的将形成混合Au凸点的部分区域之外的凸点下部导电层130的其余区域上被电镀。考虑到非导电层140与凸点下部导电层130之间的附着及构图非导电层140的方便性，优选的是，光致抗蚀剂被用作非导电层140。非导电层140可利用化学镀、溅射、蒸镀、旋涂、辊涂(roll-coating)、狭缝或狭槽模(slit-or slot-die)、或类似方法形成。在本发明的光致抗蚀剂用作非导电层140的一实施例中，非导电层140利用旋涂、辊涂、或者狭缝或狭槽模形成。正或负光致抗蚀剂可用作非导电层140。光致抗蚀剂的沉积厚度可根据光致抗蚀剂的特性而改变。在沉积光致抗蚀剂之后，光致抗蚀剂通过软烘烤工艺在热炉(hot plate)中固化，从而去除溶剂。利用曝光源和其上形成有图案的掩模，在固化了的光致抗蚀剂上选择性地进行曝光工艺。然后，通过硬烘烤工艺，该光致抗蚀剂在热炉中被热固化，从而区别光照射的区域与光未照射的区域。
参照图4，当在凸点下部导电层130上形成非导电层140后，非导电层140通过光刻蚀刻工艺构图。结果，形成非导电层图案142，其定义其中形成混合Au凸点(参照图6的附图标记170)的区域。如图4所示，优选的是，混合Au凸点区域在芯片焊盘110之上。
在形成非导电层图案142后，使用O2等离子体进行灰化工艺，从而去除有机材料，即留在凸点下部导电层130上的光致抗蚀剂。凸点下部导电层130通过此O2灰化工艺形成亲水特性。
参照图5和6，混合Au凸点170形成在非导电层图案142暴露的凸点下部导电层130区域上。首先，如图5所示，氰Au镀层150通过电镀方法形成在凸点下部导电层130通过非导电层图案142暴露的区域上。这里，包括KAu(CN)2的氰系列镀液可用于形成氰Au镀层150。然后，使用清洗溶液清洁衬底100。随后，如图6所示，通过电镀方法在氰Au镀层150上形成无氰Au镀层160。这里，包括Na3Au(SO3)2的无氰系列镀液可用作用于形成该无氰Au镀层160的镀液。
根据本发明一实施例的混合Au凸点170具有一结构，其中氰Au镀层150和无氰Au镀层160被堆叠。在根据现有技术只使用氰Au镀层制造Au凸点的情况下，所完成的Au凸点的表面是起伏不平的并具有粗糙结构，使得难以进行后续的结合工艺(combining process)，并产生环境污染问题。另外，在根据现有技术只使用无氰Au镀层制造Au凸点的情况下，由Au凸点产生异物，其污染后续电芯片筛选(EDS)测试中使用的探针尖。然而，根据本发明的混合Au凸点170具有光滑的表面，并且在EDS测试中不污染探针尖。而且，与只使用氰Au镀层的情况相比，环境污染可减小。另外，尽管通过交替地镀氰Au镀层150和无氰Au镀层160形成混合Au凸点170，但是镀层150和160的特性没有降低。即，即使通过交替地使用氰系列镀液和无氰系列镀液来进行电镀工艺，两种溶液不被非导电层图案142吸收，并且镀液不彼此影响。另外，非导电层图案142在上述工艺中未被明显破坏。下面将详细描述本发明的操作和效果。
参照图6，优选的是，根据本发明一实施例的混合Au凸点170形成至1-20μm的厚度t。优选的是，混合Au凸点170和凸点下部导电层130的总厚度在此范围内尽可能地薄，并且混合Au凸点170和凸点下部导电层130与芯片外部电连接。因此，制造时间和生产成本可以最小化。如上所述，优选的是，凸点下部导电层130形成至0.01-1μm的厚度，并且混合Au凸点170形成至1-20μm的厚度。在LDI芯片的情况中，可以容易地应用TiW/Au凸点下部导电层130与由Au或Au合金形成的混合Au凸点170的结合。
由于应用于氰Au镀层150和无氰Au镀层160的热处理，混合Au凸点170形成新的晶体结构。为此，氰Au镀层150和无氰Au镀层160每个具有新晶体结构所要求的最低厚度。即，氰Au镀层150的厚度t1和无氰Au镀层160的厚度t2在本发明中可为0.5μm或更大。另外，厚度t1和t2可为1μm或更大。
然后，如图7所示，非导电层图案142通过灰化和剥离工艺去除。
如图8所示，凸点下部导电层130根据混合Au凸点170的形状被蚀刻，由此完成LDI芯片200。凸点下部导电层130在本发明的一实施例中可利用湿蚀刻工艺蚀刻。例如，在凸点下部导电层130具有TiW/Au结构的情况中，Au可使用包含比例为1∶3∶5的HCl、HNO3、去离子水的蚀刻剂在约23℃的温度蚀刻，并且TiW可以使用浓过氧化氢溶液在约70℃的温度蚀刻。然后，在250-360℃的温度，在氧气、氮气或氢气的环境中对LDI芯片200进行热处理。优选的是，在约280℃的温度在氮气环境中进行LDI芯片200的热处理。
其后，衬底100被切割，从而LDI芯片200被分割成若干单独的LDI芯片。所获得的单独的LDI芯片利用各种安装方法安装，诸如玻璃上芯片(COG)、膜上芯片(COF)或带载封装(TCP)。
图9A至9C为根据本发明一实施例的形成在LDI芯片上的混合Au凸点170的扫描电子显微镜(SEM)图像。图9A为在倾斜方向上获得的长方体形混合Au凸点170的SEM图像。部分B表示混合Au凸点170的上表面，部分A表示混合Au凸点170的侧壁。图9B是放大图9A的混合Au凸点170的侧壁部分A的SEM图像。如图9B所示，氰Au镀层150和无氰Au镀层160之间的边界C是可见的。图9C是进一步放大图9B的混合Au凸点170的侧壁部分A的SEM图像。氰Au镀层150和无氰Au镀层160之间的边界C清晰可见。
图10为曲线图，示出根据本发明一实施例的混合Au凸点的X射线衍射(XRD)峰。本实施例中所用的混合Au凸点具有3μm厚的氰Au镀层和14μm厚的无氰Au镀层的堆叠结构。图10示出进行热处理之前和之后的根据本发明一实施例的混合Au凸点、仅由氰Au镀层形成的Au凸点(以下称作单一氰Au凸点)、仅由无氰Au镀层形成的Au凸点(以下称作单一无氰Au凸点)的XRD峰。
下面，参照图10说明混合Au凸点、单一氰Au凸点、及单一无氰Au凸点的晶体结构。
在单一氰Au凸点中，示出了热处理之前和之后的相对于<111>Au晶面和<200>Au晶面的XRD峰。该XRD峰是可忽略的。即，进行热处理之前和之后氰Au凸点具有差的晶体结构(参见图10所示的单一氰Au的XRD峰)。在单一无氰Au凸点中，<111>Au晶面主要出现在进行热处理之前，但在进行热处理之后消失，并且<200>Au晶面出现(参见图10所示的单一无氰Au的XRD峰)。在根据本发明一实施例的混合Au凸点中，无氰Au镀层中的<111>Au晶面的XRD峰出现在进行热处理之前，但比单一无氰Au凸点的低(参见图10所示的混合Au的XRD峰)。因此，尽管混合Au凸点的<111>Au晶面主要出现在进行热处理之前，但其不如单一无氰Au凸点的相同面那样普遍。另外，<200>Au晶面在进行热处理之后出现。这里，混合Au凸点的<200>Au晶面的结晶度大于单一无氰Au凸点的结晶度。
因而，由混合Au凸点的XRD峰可见，构成混合Au凸点170的无氰Au镀层160的晶体结构与单一无氰Au凸点的不同；这是因为混合Au凸点170通过堆叠氰Au镀层150和无氰Au镀层160形成。另外，显然的是，对混合Au凸点170进行热处理之后，构成混合Au凸点170的无氰Au镀层160的晶体结构与单一无氰Au凸点的不同。如上所述，根据本发明一实施例的混合Au凸点具有一结构，其中氰Au镀层150和无氰Au镀层160的晶体结构通过热处理彼此影响。因此，混合Au凸点170在防止探针尖在后续EDS测试工艺中被污染中起作用。
图11为探针尖表面的SEM图像，示出进行EDS测试后探针尖的污染程度。本发明一实施例中所用的混合Au凸点具有其中氰Au镀层和无氰Au镀层被堆叠的结构。图11是在根据本发明一实施例的混合Au凸点、单一氰Au凸点和单一无氰Au凸点上进行500次EDS测试后探针尖的表面的SEM图像。参照图11，在根据现有技术的单一氰Au凸点中，在进行EDS测试后探针尖几乎不变差，但存在诸如上述的环境污染和更危险的工作环境的其它问题。根据现有技术的单一无氰Au凸点没有这些问题，但进行EDS测试后探针尖严重变差。然而，根据本发明一实施例的混合Au凸点即使在进行500或更多次EDS测试之后也几乎不导致探针尖的退化，并且环境污染和危险的工作环境的问题不再是问题。
尽管具有其中氰Au镀层150得以形成且之后无氰Au镀层160形成于其上的堆叠结构的混合Au凸点170用于制造根据发明一实施例的LDI芯片，但是当然的是，如图12所示，根据需要，在制造根据发明另一实施例的LDI芯片200中可使用具有一堆叠结构的混合Au凸点170’，在该堆叠结构中首先形成无氰Au镀层160，然后在其上形成氰Au镀层150。即，用于本发明的混合Au凸点170和170’不受镀层150和160的堆叠顺序限制，因为混合Au凸点170和170’的物理性质只由氰Au镀层150和无氰Au镀层160的结合来决定，每个镀层具有由热处理导致的新的结晶性。另外，本发明不限于具有其中一层氰Au镀层和一层无氰Au镀层堆叠的结构的混合Au凸点。显然，具有其中一个或更多个氰Au镀层和一个或更多个无氰Au镀层交替堆叠的结构的混合Au凸点可应用于本发明。
表1示出了具有本发明实施例中各种结构的混合Au凸点的EDS测试的结果。表1示出对685个芯片进行EDS测试后由探针尖的退化引起的开路故障芯片的数量。下面，参照表1解释混合Au凸点的EDS测试结果。
表1-EDS测试条件和结果
  结构   热处理条件   开路故障芯片数量(Bin 20)
 实验例1   C(13)/N(2)   N2，280℃   0
 实验例2   C(13)/N(2)   O2，355℃   0
 实验例3   C(2)/N(13)   O2，355℃   0
 实验例4   C(2)/N(13)   N2，280℃   0
 实验例5   N(2)/C(13)   O2，355℃   0
 实验例6   N(2)/C(13)   N2，280℃   0
 实验例7   N(13)/C(2)   N2，280℃   0
 实验例8   N(13)/C(2)   O2，355℃   0
 对比例1   C(0.35)/N(14)   N2，280℃   57
这里，C表示氰Au镀层，N表示无氰Au镀层，括号中的值表示镀层的厚度。
实验例1的混合Au凸点具有一结构，其中13μm氰Au镀层和2μm无氰Au镀层依次堆叠在凸点下部导电层上，并且热处理在280℃的温度在氮气环境中进行。实验例2的混合Au凸点具有一结构，其中13μm氰Au镀层和2μm无氰Au镀层依次堆叠，并且热处理在355℃的温度在氧气环境中进行。实验例3的混合Au凸点具有一结构，其中氰Au镀层(2μm)和无氰Au镀层(13μm)依次堆叠，并且热处理在355℃的温度在氧气环境中进行。实验例4的混合Au凸点具有一结构，其中2μm氰Au镀层和13μm无氰Au镀层依次堆叠，并且热处理在280℃的温度在氮气环境中进行。实验例5的混合Au凸点具有一结构，其中2μm无氰Au镀层和13μm氰Au镀层依次堆叠，并且热处理在355℃的温度在氧气环境中进行。实验例6的混合Au凸点具有一结构，其中2μm无氰Au镀层和13μm氰Au镀层依次堆叠，并且热处理在280℃的温度在氮气环境中进行。实验例7的混合Au凸点具有一结构，其中13μm无氰Au镀层和2μm氰Au镀层依次堆叠，并且热处理在280℃的温度在氮气环境中进行。实验例8的混合Au凸点具有一结构，其中13μm的无氰Au镀层和2μm的氰Au镀层依次堆叠，并且热处理在355℃的温度在氧气环境中进行。对比例1的混合Au凸点具有一结构，其中0.35μm的氰Au镀层和14μm的无氰Au镀层依次堆叠，并且热处理在280℃的温度在氮气环境中进行。
参照表1，尽管根据实验例1至8对本发明的混合Au凸点的685个芯片进行了EDS测试而没有探针尖清洁工艺，但没有发现开路故障芯片。然而，在具有0.35μm氰Au镀层的对比例1中发现了很多开路故障芯片。如前所述，本发明的混合Au凸点不依赖于构成混合Au凸点的氰Au镀层和无氰Au镀层的堆叠顺序。另外，当构成混合Au凸点的氰Au镀层和无氰Au镀层的厚度为0.5μm或更大，更优选地为1μm或更大时，探针尖被最小化。这意味着氰Au镀层和无氰Au镀层每个必须具有很低的厚度，以将它们结合来形成其新的晶体结构。
尽管在上述实施例中给出了对LDI芯片例子的描述，但是显然，根据本发明实施例的混合Au凸点的结构可应用于各种微电子器件芯片。例如，根据本发明的凸点的结构可以有益地应用于诸如DRAM、SRAM、闪存、FRAM、MRAM的高度集成的半导体存储器件的芯片、微机电系统(MEMS)芯片、诸如CPU或DSP的处理器芯片。另外显然，根据本发明的凸点的结构可以应用于包括单元件的芯片、包括同类元件的芯片、及包括各种元件并需要提供完整功能或完整系统的系统芯片(SOC)。
图1至12描述的根据本发明各种实施例的LDI芯片可以根据各种安装方法安装在各种结构上。例如，通过玻璃上芯片(COG)方法，LDI芯片可以直接安装在显示面板上。它也可以安装在封装衬底上，例如模制引线框架(molded lead frame)、印刷电路板(PCB)、柔性带布线板(flexible tape wiringboard)、或直焊铜(direct bond copper：DBC)上。另外，在半导体芯片和组件衬底之间提供电连接和/或机械柔性的插入物(interposer)可用作封装衬底。插入物可由弹性材料如带、聚酰亚胺、或塑料材料制成，并可包括单个的图案化的再分布层或大量的图案化的再分布层及无源元件。在根据本发明实施例的LDI芯片通过带载封装(TCP)方法或膜上芯片(COF)封装方法安装在柔性带布线板上之后，LDI芯片可最终安装在PCB或显示面板上。
图13A是LCD(液晶显示器)面板组件的平面图，其上通过COG方法安装了根据本发明一实施例的LDI芯片200，图13B是沿图13A的线B-B’截取的截面图。
参照图13A和13B，本发明的LCD装置300包括LDI芯片200和LCD面板组件325。LDI芯片200直接安装在包括薄膜晶体管(TFT)面板310和滤色器面板320的LCD面板组件325上。此外，PCB335通过柔性衬底330连接到LCD面板组件325。TFT面板310包括TFT矩阵。滤色器面板320包括格栅形黑矩阵、红/绿/蓝(RGB)像素、及氧化铟锡(ITO)电极。液晶(未示出)注入在面板310和320之间。诸如数据线340、栅线350、用于栅驱动信号的传输线345和355的布线邻近有效显示区形成在TFT面板310上。
参照图13B，根据本发明具有混合Au凸点170的LDI芯片200通过面向下键合(face-down bonding)方法直接连接至TFT面板310上的布线340、350、345、355或与布线340、350、345、355相连的焊盘360。同时，使用各向异性导电膜(ACF)370来连接LDI芯片200。ACF 370包括分散在粘合膜(adhesive film)372中的小导电颗粒374。粘合膜372大约15-35μm，并且导电颗粒374的直径大约3-15μm。粘合膜372可由诸如丁苯橡胶(styrene-butadiene rubber)、聚乙烯丁烯(polyvinyl butylene)的热塑性膜、诸如环氧树脂、聚氨酯、丙烯酸树脂的热固性膜形成，或者可以使用热塑性膜和热固性膜的混合膜。导电颗粒374可由金、银、镍、涂覆了金属的玻璃或聚合物制成。在ACF 370粘合到LCD面板组件325的布线340、350、345、355或连接布线340、350、345、355的焊盘360上，并且混合Au凸点170粘合到ACF 370从而对应焊盘360之后，将它们热压。结果，通过导电颗粒374实现混合Au凸点170与焊盘360之间的电连接。
尽管图13B示出了使用ACF的COG安装方法，显然，可以使用利用非导电糊(NCP)的COG安装方法。尽管图中未示出利用NCP的COG安装方法，但混合Au凸点170直接连接至焊盘360，并且LDI芯片200通过NCP粘附到LCD面板组件325上。
COG安装方法具有下述优点。它易于修复；树脂不必填满LDI芯片200与LCD面板组件325之间的间隙(空洞)；并且由于不需要额外的封装衬底，减少了安装成本。
图14是带布线板400的平面图，其上安装有图1至12描述的根据本发明各种实施例的LDI芯片。参照图14，布线420形成在由诸如聚酰亚胺的可弯曲材料形成的柔性膜410上。在带布线板400用于带载封装(TCP)的情况下，LDI芯片粘附的区域，即窗口425在柔性膜410的中部。用于COF封装的带布线板与用于TCP的带布线板不同，该不同在于布线420布置在柔性膜410上而没有窗口425。布线420由铜(Cu)和在Cu的表面上镀锡、金、镍、或焊料的材料形成至约5-20μm的厚度。
附图标记430表示涂覆有焊料抵抗剂(solder resist)的区域。该区域430防止布线420在暴露于外部时被氧化及被异物开路。附图标记440表示从柔性膜410切出的使用区。附图标记A1和A2是直接粘附到PCB或LCD面板上的外部连接端子。
图15和16是TCP和COF封装的截面图，其上分别安装了根据本发明一实施例的LDI芯片200。参照图15和16，根据本发明具有混合Au凸点170的LDI芯片200通过面向上键合(face-up bonding)方法连接到柔性膜410上的布线420的内部连接端子。树脂450形成在LDI芯片200的两侧，从而覆盖包括焊料抵抗剂430、布线420、及混合Au凸点170的键合结构。
图17为LCD面板组件325的示意图，其中以COF封装的形式安装了根据本发明实施例的LDI芯片。与图13A所示的LCD面板组件325的元件相同或等价的元件的描述被省略。带布线板400上的外部连接端子的第一侧分别连接到TFT面板310上的数据线340或栅线350，其它侧连接到用于栅驱动信号的传输线345和355。虽然本实施例中描述了其中以COF封装的形式安装LDI芯片的LCD面板组件325，但本发明不限于此。显然，可以应用其中以TCP形式安装LDI芯片的LCD面板组件325。
总之，本领域技术人员理解，在不偏离本发明的原理的情况下，可以对优选实施例进行多种变化和修改。因此，所公开的本发明的优选实施例只在一般的和描述的意义上得以使用，而不用于限制的目的。
如上所述，根据包括根据本发明的混合Au凸点的微电子器件芯片，在后续EDS测试中异物不产生在探针尖处，并且混合Au凸点具有精细结构。另外，与只使用氰Au镀层的情况相比，环境污染可以减少。
本申请要求2004年9月15日在韩国知识产权局提交的第10-2004-0073801号韩国专利申请的优先权，其全部内容在此引入作为参考。

Claims (43)

1.一种微电子器件芯片，包括：
芯片焊盘，其连接至形成在衬底上的微电子器件，从而使所述微电子器件与所述芯片的外部电接触；以及
凸点，其形成在该芯片焊盘上并包括复合层，所述复合层包括两层或更多层。
2.如权利要求1的微电子器件芯片，其中所述凸点为混合Au凸点，其中氰Au镀层和无氰Au镀层得以堆叠。
3.如权利要求2的微电子器件芯片，其中所述混合Au凸点具有1-20μm范围内的厚度。
4.如权利要求3的微电子器件芯片，其中所述氰Au镀层的厚度及所述无氰Au镀层的厚度不小于0.5μm。
5.如权利要求4的微电子器件芯片，其中所述混合Au凸点的所述氰Au镀层位于所述芯片焊盘上，并且所述混合Au凸点的所述无氰Au镀层位于所述氰Au镀层上。
6.如权利要求4的微电子器件芯片，其中所述混合Au凸点的所述无氰Au镀层位于所述芯片焊盘上，并且所述混合Au凸点的所述氰Au镀层位于所述无氰Au镀层上。
7.一种微电子器件芯片，包括：
芯片焊盘，其连接至形成在衬底上的微电子器件，从而使所述微电子器件与所述芯片的外部电接触；
钝化层，其保护所述微电子器件并暴露所述芯片焊盘；
凸点，其形成在由所述钝化层暴露的所述芯片焊盘上并包括复合层，所述复合层包括两层或更多层；以及
凸点下部导电层，其形成在所述芯片焊盘与所述凸点之间，从而防止所述芯片焊盘与所述凸点之间的相互扩散，并改善所述芯片焊盘与所述凸点之间的附着。
8.如权利要求7的微电子器件芯片，其中所述凸点为混合Au凸点，其中氰Au镀层和无氰Au镀层得以堆叠。
9.如权利要求8的微电子器件芯片，其中所述混合Au凸点具有1-20μm范围内的厚度。
10.如权利要求9的微电子器件芯片，其中所述氰Au镀层的厚度及所述无氰Au镀层的厚度不小于0.5μm。
11.如权利要求10的微电子器件芯片，其中所述混合Au凸点的所述氰Au镀层位于所述芯片焊盘上，并且所述混合Au凸点的所述无氰Au镀层位于所述氰Au镀层上。
12.如权利要求10的微电子器件芯片，其中所述混合Au凸点的所述无氰Au镀层位于所述芯片焊盘上，并且所述混合Au凸点的所述氰Au镀层位于所述无氰Au镀层上。
13.如权利要求9的微电子器件芯片，其中所述凸点下部导电层由TiW、Cr、Cu、Ti、Ni、NiV、Pd、Cr/Cu、TiW/Cu、TiW/Au及NiV/Cu中的至少一种形成。
14.如权利要求13的微电子器件芯片，其中所述凸点下部导电层具有堆叠结构，该堆叠结构包括0.005-0.5μm厚的TiW和0.005-0.5μm厚的Au。
15.如权利要求8的微电子器件芯片，其中所述混合Au凸点具有一结构，其中一个或更多个氰Au镀层与一个或更多个无氰Au镀层交替堆叠。
16.一种封装，包括根据权利要求1至15中的任一项的微电子器件芯片、以及带布线板，所述带布线板包括由外部连接端子和电连接到所述微电子器件芯片的凸点的内部连接端子构成的布线。
17.一种液晶显示装置，包括根据权利要求1至15中的任一项的微电子器件芯片、以及其中形成有用于连接到所述微电子器件芯片的布线的液晶显示面板组件；其中所述微电子器件芯片的凸点电连接到所述布线。
18.如权利要求17的液晶显示装置，其中所述微电子器件芯片利用玻璃上芯片(COG)方法、带载封装(TCP)方法和膜上芯片(COF)方法中的一种连接至所述液晶显示面板组件。
19.一种制造微电子器件芯片的方法，包括：
制备芯片焊盘，其连接到形成在衬底上的微电子器件，从而使所述微电子器件与所述芯片的外部电接触；以及
形成凸点，其形成在所述芯片焊盘上并包括复合层，所述复合层包括两层或更多层。
20.如权利要求19的方法，其中所述凸点的形成包括于所述芯片焊盘上形成混合Au凸点，在该混合Au凸点中氰Au镀层和无氰Au镀层被堆叠。
21.如权利要求20的方法，其中所述凸点利用电镀方法形成。
22.如权利要求21的方法，其中所述氰Au镀层利用KAu(CN)2系列镀液形成，所述无氰Au镀层利用Na3Au(SO3)2系列镀液形成。
23.如权利要求21的方法，其中所述混合Au凸点具有1-20μm范围内的厚度。
24.如权利要求23的方法，其中所述氰Au镀层的厚度及所述无氰Au镀层的厚度不小于0.5μm。
25.如权利要求21的方法，其中所述凸点的形成包括在所述芯片焊盘上形成所述氰Au镀层，然后在其上形成所述无氰Au镀层。
26.如权利要求21的方法，其中所述凸点的形成包括在所述芯片焊盘上形成所述无氰Au镀层，然后在其上形成所述氰Au镀层。
27.如权利要求20的方法，在形成所述凸点后还包括进行热处理。
28.如权利要求27的方法，其中在氧气和氮气环境中的一种中在250-360℃范围内的温度进行所述热处理。
29.一种制造微电子器件芯片的方法，包括：
形成暴露芯片焊盘的钝化层；
在所得结构上形成凸点下部导电层；
在所述凸点下部导电层上形成非导电层图案，其限定其中将要形成凸点的区域；
利用所述非导电层图案作为掩模在所述凸点下部导电层上形成所述凸点，所述凸点由包括两层或更多层的复合层构成；以及
去除所述非导电层图案。
30.如权利要求29的方法，其中所述凸点的形成包括形成混合Au凸点，其中氰Au镀层和无氰Au镀层被堆叠。
31.如权利要求30的方法，其中所述凸点的形成利用电镀方法进行。
32.如权利要求31的方法，其中所述氰Au镀层利用KAu(CN)2系列镀液形成，所述无氰Au镀层利用Na3Au(SO3)2系列镀液形成。
33.如权利要求31的方法，其中所述混合Au凸点具有1-20μm范围内的厚度。
34.如权利要求33的方法，其中所述氰Au镀层的厚度及所述无氰Au镀层的厚度不小于0.5μm。
35.如权利要求33的方法，其中所述凸点的形成包括在所述芯片焊盘上形成所述氰Au镀层，然后在其上形成所述无氰Au镀层。
36.如权利要求33的方法，其中所述凸点的形成包括在所述芯片焊盘上形成所述无氰Au镀层，然后在其上形成所述氰Au镀层。
37.如权利要求30的方法，其中所述凸点下部导电层的形成包括利用TiW、Cr、Cu、Ti、Ni、NiV、Pd、Cr/Cu、TiW/Cu、TiW/Au及NiV/Cu中的一种形成所述凸点下部导电层。
38.如权利要求37的方法，其中所述凸点下部导电层的形成包括通过依次溅射TiW和Au形成具有TiW/Au结构的所述凸点下部导电层。
39.如权利要求38的方法，其中所述凸点下部导电层被形成为具有TiW/Au结构，其中堆叠0.005-0.5μm厚的TiW和0.005-0.5μm厚的Au。
40.如权利要求30的方法，在去除所述非导电层图案之后还包括利用所述混合Au凸点作为掩模去除所述凸点下部导电层。
41.如权利要求40的方法，在去除所述凸点下部导电层之后还包括进行热处理。
42.如权利要求41的方法，其中在氧气和氮气环境中的一种中在250-360℃范围内的温度进行所述热处理。
43.如权利要求30的方法，其中所述非导电层图案是光致抗蚀剂图案。
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CN100479140C (zh) 2009-04-15
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KR20060024928A (ko) 2006-03-20
JP4773167B2 (ja) 2011-09-14
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US20060055037A1 (en) 2006-03-16
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