CN1881572A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1881572A
CN1881572A CNA200610091292XA CN200610091292A CN1881572A CN 1881572 A CN1881572 A CN 1881572A CN A200610091292X A CNA200610091292X A CN A200610091292XA CN 200610091292 A CN200610091292 A CN 200610091292A CN 1881572 A CN1881572 A CN 1881572A
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plating layer
pad electrode
peristome
semiconductor device
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CN100527401C (zh
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森田佑一
石部真三
野间崇
大塚久夫
高尾幸弘
金森宽
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

本发明涉及一种半导体装置。其是可靠性高的BGA型的半导体装置。其具有：形成在半导体衬底(1)之上的焊盘电极(4)；覆盖该焊盘电极(4)的端部并在上述焊盘电极(4)之上具有第一开口部(6)的第一钝化膜(5)；经由上述第一开口部(6)而形成在上述焊盘电极(4)之上的镀敷层(7)；覆盖上述第一钝化膜(5)的端和上述镀敷层(7)之间的上述焊盘电极(4)的露出部(8)且进而覆盖上述镀敷层(7)的端部并在上述镀敷层(7)上具有第二开口部(10)的第二钝化膜(9)；经由第二开口部(10)而形成在上述镀敷层(7)上的导电端子(11)。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种可靠性高的BGA型半导体装置及其制造方法。
背景技术
近年来，作为新型封装技术，CSP(chip size package：芯片尺寸封装)受到关注。所谓CSP是指与半导体芯片的外形尺寸具有大致相同尺寸的外形尺寸的小型封装部件。
目前，作为CSP的一种，BGA(Ball Grid Array：球栅阵列)型的半导体装置被众所周知。该BGA型的半导体装置上设有与半导体衬底表面的焊盘电极电连接的球状的导电端子。
并且，将该BGA型的半导体装置装入电子设备中时，各导电端子压固在印刷基板上的配线图案上，从而使半导体芯片和搭载在印刷基板上的外部电路电连接。
这样的BGA型电子装置，与具有向侧部突出的导线引脚的SOP(SmallOutline Package：小外面封装)和QFP(Quad Flat Package：四线扁平封装)等其他CSP型的半导体装置相比，可设置多个导电端子，而且能够实现小型化，由于具有这些优点，可作为例如搭载在手提电话上的数码像头的图像传感芯片等被广泛使用。
下面，参照附图(图7～图10)说明上述现有的BGA型的半导体装置。图7～图10分别是按照工序顺序表示的剖面图。
首先，如图7所示，在由硅(Si)构成的半导体衬底100之上形成硅氧化膜101、层间绝缘膜102(聚酰亚胺类树脂膜、PSG膜等)。
并且，在层间绝缘膜102上形成金属层(铝层)，用未图示的掩模对该金属层进行构图，从而在层间绝缘膜102上形成焊盘电极103。
接着，如图8所示，在含有焊盘电极103的半导体衬底100的表面侧形成由阻焊剂等构成的钝化膜104，通过在该钝化膜104上实施曝光显影，形成使焊盘电极103的规定的表面露出的开口部105。
接着，如图9所示，通过电解镀敷法或无电解镀敷法，在从开口部105露出的焊盘电极103的表面上形成由镍(Ni)和金(Au)的层叠结构构成的镀敷层106。
在此，在焊盘电极103的各角部上，不被镀敷层106覆盖，而呈露出部107残留的状态。出现该露出部107的原因有多种多样。其中之一是，受到为防止钝化膜104翘曲而在该膜上添加的添加料(添加剂)等影响，在上述开口部105的形成时，在钝化膜104的侧壁(图案面)上容易残留其残渣，侧壁变成凹凸状，而使镀敷层106难以紧密粘贴。
另外，在此，露出部107是指钝化膜104和镀敷层106之间的焊盘电极103露出的部位。
接着，如图10所示在镀敷层106的规定区域上通过电解镀敷法或无电解镀敷法固定焊锡球，形成导电端子108。
另外，也可通过丝网印刷焊锡，而由热处理使该焊锡进行回流焊，从而形成导电端子108(焊锡突起)。
本发明的技术文献列举：
日本专利公开(特开)2000-299406号公报
但是，上述的现有的BGA型的半导体装置，存在这样的缺陷，即，会造成腐蚀的物质例如水、药剂、腐蚀性气体、金属离子等经由露出部107侵入，焊盘电极103被腐蚀，而使半导体装置的可靠性降低。
发明内容
本发明是鉴于上述问题而研发的，其主要特征如下。
即，本发明的半导体装置具有：焊盘电极，其形成在半导体衬底上；第一钝化膜，其覆盖上述焊盘电极的端部，并在上述焊盘电极之上具有第一开口部；镀敷层，其经由上述第一开口部而形成在上述焊盘电极之上；第二钝化膜，其覆盖上述第一钝化膜的端部和上述镀敷层之间的上述焊盘电极的露出部，进而覆盖上述镀敷层的端部，并在上述镀敷层之上具有第二开口部；导电端子，其经由上述第二开口部形成在上述镀敷层之上。
本发明的半导体装置的制造方法，具有以下工序：形成覆盖形成在半导体衬底上的焊盘电极的端部，并在上述焊盘电极上具有第一开口部的第一钝化膜；经由上述第一开口部在上述焊盘电极上形成镀敷层；形成覆盖上述第一钝化膜的端部和上述镀敷层之间的上述焊盘电极的露出部，进而覆盖上述镀敷层的端部，并在上述镀敷层之上具有第二开口部的第二钝化膜；经由上述第二开口部在上述镀敷层之上形成导电端子。
发明效果
根据本发明的半导体装置及其制造方法，分两次形成第一和第二钝化膜，从而使镀敷层的区域扩大，另外，焊盘电极的露出部由第二钝化膜覆盖，所以可防止焊盘电极的腐蚀，提供可靠性高的半导体装置。
附图说明
图1是说明本发明的半导体装置及其制造方法的剖面图；
图2是说明本发明的半导体装置及其制造方法的剖面图；
图3是说明本发明的半导体装置及其制造方法的剖面图；
图4是说明本发明的半导体装置及其制造方法的剖面图；
图5是说明本发明的半导体装置及其制造方法的剖面图；
图6是说明本发明的半导体装置及其制造方法的平面图；
图7是说明现有的半导体装置及其制造方法的剖面图；
图8是说明现有的半导体装置及其制造方法的剖面图；
图9是说明现有的半导体装置及其制造方法的剖面图；
图10是说明现有的半导体装置及其制造方法的剖面图。
附图标记说明
1   半导体衬底
2   绝缘膜
3   层间绝缘膜
4   焊盘电极
5   第一钝化膜
6   开口部
7   镀敷层
8   露出部
9   第二钝化膜
10  开口部
11  导电端子
100  半导体衬底
101  硅氧化膜
102  层间绝缘膜
103  焊盘电极
104  钝化膜
105  开口部
106  镀敷层
107  露出部
108  导电端子
具体实施方式
下面参照附图详细说明本发明的实施例。图1～图5分别是表示本发明的半导体装置中的工序顺序的剖面图。另外，图6是本发明的半导体装置的平面图，图5是沿图6的X-X线的剖面图。另外，半导体衬底上适当形成有MOS晶体管、多个配线、连接配线间的插塞等元件、硅氧化膜构成的元件分离区，其图示省略。
首先，如图1所示，在由硅(Si)等构成的半导体衬底1的表面上形成例如2μm膜厚的绝缘膜2(例如利用热氧化法或CVD法形成的硅氧化膜)。接着，利用涂敷(塗布)、涂覆(coating)法(利用旋涂或喷溅(spray)的涂覆)在绝缘膜2的表面上形成例如膜厚10μm的层间绝缘膜3(聚酰亚胺类树脂膜等有机膜)。
本实施例中，从确保耐压的观点来看，形成层间绝缘膜3，但也可形成不特别设有层间绝缘膜3的结构。另外，层间绝缘膜3可以是由CVD法等形成的硅氧化膜、硅氮化膜、PSG膜、BPSG膜其他绝缘膜。
接着，利用CVD法、溅射(sputtering)法、其他成膜方法形成构成焊盘电极4的铝(Al)和铜(Cu)等金属层，之后，用未图示的掩模对该金属层进行构图，在层间绝缘膜3上形成例如1μm膜厚的焊盘电极4。
另外，焊盘电极4是与半导体衬底上的未图示的输入电路和输出电路连接的外部连接用焊盘。另外，在本发明的焊盘电极4中，形成比现有的焊盘103的外形尺寸大1.1～1.2倍的尺寸。当然，焊盘电极4的外形尺寸在芯片尺寸允许的范围内可以形成得大一些。
接着，如图2所示，以例如10μm的厚度形成覆盖层间绝缘膜3的表面和焊盘电极4的端部并在焊盘电极4上具有开口部6的第一钝化膜5。该第一钝化膜5的形成中，用涂敷、涂覆法将聚酰亚胺类树脂膜、阻焊剂膜等有机类材料涂敷在层间绝缘膜3和焊盘电极4表面上，实施热处理(预烤：プリベ一ク)。另外，从防止膜的翘曲的观点来看，也可在第一钝化膜5中添加有添加料(添加剂)。
接着，将被涂敷的有机类材料曝光、显影，形成使焊盘电极4的规定表面露出的上述开口部6，之后实施热处理(热烤：ホストベ一ク)。该第一钝化膜5和后述的第二钝化膜9具有使半导体衬底1的表面稳定化，作为使其不受腐蚀等影响的保护膜的作用。
接着，将上述第一钝化膜5作为掩模使用，如图3所示，用电解镀敷法或无电解镀敷法，在从开口部6露出的焊盘电极4的表面上形成顺次层叠主要由镍构成的镍(Ni)层和主要由金构成的金(Au)层而得的镀敷层7(下层镍、上层金)。在此，在焊盘电极4的各角部不由镀敷层7覆盖，而呈露出部8残留的状态。
接着，如图4所示，在半导体衬底1的表面上，通过涂敷、涂覆法形成例如10μm厚度的由聚酰亚胺类树脂膜、阻焊剂膜等有机类材料构成的第二钝化膜9(修复钝化膜：repair passivation)。该第二钝化膜9覆盖露出部8，进而覆盖镀敷层7的端部，并在镀敷层7上具有开口部10。
该第二钝化膜9的形成中，与形成第一钝化膜5的方法一样，由涂敷、涂覆法，在第一钝化膜5和镀敷层7表面涂敷聚酰亚胺树脂膜、阻焊剂膜等有机类材料，实施热处理(预烤)。接着，使涂敷的有机类材料曝光、显影，形成使镀敷层7的规定表面露出的开口部10，之后实施处理(热烤)。
其次，如图5、6所示，经由上述开口部10在镀敷层7的规定区域上，采用利用镀敷层7作为镀敷电极的电解镀敷法，固定焊锡球，形成导电端子11。
在由焊锡球构成导电端子11的情况下，具有可容易地形成导电端子11的优点。导电端子11的高度例如为100μm。
另外，也可通过对焊锡进行丝网印刷，而由热处理使焊锡进行回流焊，从而形成同样的导电端子11(焊锡突起)。导电端子11由焊锡突起构成的情况下，具有可以将微细的形状的端子以更高的精度形成的优点。另外，导电端子11可以是以金为材料的，但其材料不作特别限定。
根据以上的结构，分两次形成钝化膜，所以镀敷层7形成为比以往宽阔的区域，该镀敷层7的端部由第二钝化膜9覆盖。另外，焊盘电极4的露出部8也由第二钝化膜9覆盖。因此，可防止焊盘电极4的腐蚀，提高半导体装置的可靠性。
进而，镀敷层7形成为比以往更宽阔的区域，所以即使第二钝化膜9和导电端子11之间出现间隙，由于从该间隙到焊盘电极4的露出部8的距离也变长，所以对腐蚀的抵抗变强。
另外，如以上所述，产生露出部8的原因有多种多样(添加料的影响、第一钝化膜5和镀敷层7的密接性等)，但是，本发明不限于这些原因，而广泛适用于产生露出部8的半导体装置及其制造方法。

Claims (6)

1.一种半导体装置，其特征在于，具有：
焊盘电极，其形成在半导体衬底上；
第一钝化膜，其覆盖上述焊盘电极的端部，并在上述焊盘电极之上具有第一开口部；
镀敷层，其经由上述第一开口部而形成在上述焊盘电极之上；
第二钝化膜，其覆盖上述第一钝化膜的端部和上述镀敷层之间的上述焊盘电极的露出部，进而覆盖上述镀敷层的端部，并在上述镀敷层之上具有第二开口部；
导电端子，其经由上述第二开口部形成在上述镀敷层之上。
2.如权利要求1所述的半导体装置，其特征在于，上述第一和第二钝化膜由有机材料构成。
3.如权利要求1或2所述的半导体装置，其特征在于，上述镀敷层由镍层以及金层的层叠结构构成。
4.一种半导体装置的制造方法，其特征在于，具有以下工序：
形成覆盖形成在半导体衬底上的焊盘电极的端部，并在上述焊盘电极上具有第一开口部的第一钝化膜；
经由上述第一开口部在上述焊盘电极上形成镀敷层；
形成覆盖上述第一钝化膜的端部和上述镀敷层之间的上述焊盘电极的露出部，进而覆盖上述镀敷层的端部，并在上述镀敷层之上具有第二开口部的第二钝化膜；
经由上述第二开口部在上述镀敷层之上形成导电端子。
5.如权利要求4所述的半导体装置的制造方法，其特征在于，上述第一和第二钝化膜由有机材料构成。
6.如权利要求4或5所述的半导体装置的制造方法，其特征在于，形成上述镀敷层的工序包括：由电解镀敷法或无电解镀敷法形成镍层的工序和在上述镍层的表面上由电解镀敷法或无电解镀敷法形成金层的工序。
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