CN1881573A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

Info

Publication number
CN1881573A
CN1881573A CNA2006100926710A CN200610092671A CN1881573A CN 1881573 A CN1881573 A CN 1881573A CN A2006100926710 A CNA2006100926710 A CN A2006100926710A CN 200610092671 A CN200610092671 A CN 200610092671A CN 1881573 A CN1881573 A CN 1881573A
Authority
CN
China
Prior art keywords
mentioned
pad electrode
semiconductor device
film
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2006100926710A
Other languages
English (en)
Inventor
森田佑一
石部真三
野间崇
大塚久夫
高尾幸弘
金森宽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1881573A publication Critical patent/CN1881573A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及一种半导体装置。其是可靠性高的BGA型的半导体装置。其具有：经由绝缘膜2、3形成在半导体衬底(1)之上的焊盘电极(4)；形成在上述焊盘电极(4)的表面上的镀敷层(7)；形成在上述镀敷层(7)的表面上并与上述焊盘电极电连接的导电端子(9)；覆盖上述绝缘膜(2、3)之上和上述焊盘电极(4)的侧端部而形成的第一钝化膜(5)。通过覆盖上述第一钝化膜(5)之上和上述镀敷层(7)和上述导电端子(9)的侧壁的一部分而形成第二钝化膜(10)，覆盖造成腐蚀的焊盘电极(4)的露出部(8)。

Description

半导体装置及其制造方法
技术领域
本发明涉及一种可靠性高的BGA型半导体装置及其制造方法。
背景技术
近年来，作为新型封装技术，CSP(chip size package：芯片尺寸封装)受到关注。所谓CSP是指与半导体芯片的外形尺寸具有大致相同的外形尺寸的小型封装部件。
目前，作为CSP的一种，BGA(Ball Grid Array：球栅阵列)型的半导体装置被众所周知。该BGA型的半导体装置上设有与半导体衬底表面的焊盘电极电连接的球状的导电端子。
并且，将该BGA型的半导体装置装入电子设备中时，将各导电端子压固在印刷基板上的配线图案上，从而使半导体芯片和搭载在印刷基板上的外部电路电连接。
这样的BGA型电子装置，与具有向侧部突出的导线引脚的SOP(SmallOutline Package：小外面封装)和QFP(Quad Flat Package：四线扁平封装)等其他CSP型的半导体装置相比，可设置多个导电端子，而且能够实现小型化，由于具有这些优点，可作为例如搭载在手提电话上的数码像头的图像传感芯片等被广泛使用。
下面，参照附图(图7～图10)说明上述现有的BGA型的半导体装置。图7～图10分别是按照制造工序顺序表示的剖面图。
首先，如图7所示，在由硅(Si)构成的半导体衬底100之上形成硅氧化膜101、层间绝缘膜102(聚酰亚胺类树脂膜、PSG膜等)。
并且，在层间绝缘膜102上形成金属层(铝层)，用未图示的掩模对该金属层进行构图，从而在层间绝缘膜102上形成焊盘电极103。接着，如图8所示，在含有焊盘电极103的半导体衬底100的表面侧形成由阻焊剂等构成的钝化膜104，通过在该钝化膜104上实施曝光显影，形成使焊盘电极103的规定的表面露出的开口部105。
接着，如图9所示，通过电解镀敷法或无电解镀敷法，在从开口部105露出的焊盘电极103的表面上形成由镍(Ni)和金(Au)的层叠结构构成的镀敷层106。
在此，在焊盘电极103的各角部上，不被镀敷层106覆盖，而呈露出部107残留的状态。出现该露出部107的原因有多种多样。其中之一是，受到为防止钝化膜104翘曲而在该膜上添加的添加料(添加剂)等影响，在上述开口部105形成时，在钝化膜104的侧壁(图案面)上容易残留其残渣，侧壁变成凹凸状，而使镀敷层106难以紧密粘贴。
另外，在此，露出部107是指钝化膜104和镀敷层106之间的焊盘电极103露出的部位。
接着，如图10所示，在镀敷层106的规定区域上通过电解镀敷法或无电解镀敷法固定焊锡球，形成导电端子108。
另外，也可通过丝网印刷焊锡，而由热处理使该焊锡进行回流焊，从而形成导电端子108(焊锡突起)。
本发明的技术文献列举：
日本专利公开(特开)2000-299406号公报
但是，上述的现有的BGA型的半导体装置，存在这样的缺陷，即，会造成腐蚀的物质例如水、药剂、腐蚀性气体、金属离子等经由露出部107侵入，焊盘电极103被腐蚀，而使半导体装置的可靠性降低。
发明内容
本发明是鉴于上述问题而研发的，其主要特征如下。
即，本发明的半导体装置具有：焊盘电极，其经由绝缘膜形成在半导体衬底上；第一钝化膜，其覆盖上述焊盘电极的端部，并在上述焊盘电极之上具有开口部；镀敷层，其经由上述开口部而形成在上述焊盘电极之上；导电端子，其形成在上述镀敷层的表面上，与上述焊盘电极电连接；第二钝化膜，其覆盖上述镀敷层和上述第一钝化膜之间的上述焊盘电极的露出部而形成。
该装置中，优选地，上述第二钝化膜覆盖上述导电端子的侧壁的一部分。
本发明的半导体装置的制造方法，其特征在于，具有以下工序：形成覆盖形成在半导体衬底上的焊盘电极的端部的第一钝化膜的工序；在上述焊盘电极表面通过电解镀敷法或无电解镀敷法形成镀敷层的工序；在上述镀敷层的表面形成导电端子的工序；覆盖上述镀敷层和上述第一钝化膜之间的上述焊盘电极的露出部而形成第二钝化膜的工序。
该制造方法中，优选地，上述第二钝化膜覆盖上述导电端子的侧壁的一部分。
发明效果
根据本发明的半导体装置及其制造方法，由于覆盖造成腐蚀的焊盘电极上出现的露出部而形成钝化膜，所以配线等的尺寸不会变化，可防止焊盘电极的腐蚀，可提供可靠性高的BGA型的半导体装置。另外，通过由该钝化膜覆盖导电端子的侧壁的一部分来进一步提高可靠性。
附图说明
图1是说明本发明的半导体装置及其制造方法的剖面图；
图2是说明本发明的半导体装置及其制造方法的剖面图；
图3是说明本发明的半导体装置及其制造方法的剖面图；
图4是说明本发明的半导体装置及其制造方法的剖面图；
图5是说明本发明的半导体装置及其制造方法的剖面图；
图6是说明本发明的半导体装置及其制造方法的平面图；
图7是说明现有的半导体装置及其制造方法的剖面图；
图8是说明现有的半导体装置及其制造方法的剖面图；
图9是说明现有的半导体装置及其制造方法的剖面图；
图10是说明现有的半导体装置及其制造方法的剖面图。
附图标记说明
1半导体衬底
2绝缘膜
3层间绝缘膜
4焊盘电极
5第一钝化膜
6开口部
7镀敷层
8露出部
9导电端子
10第二钝化膜
100半导体衬底
101硅氧化膜
102层间绝缘膜
103焊盘电极
104钝化膜
105开口部
106镀敷层
107露出部
108导电端子
具体实施方式
下面参照附图详细说明本发明的实施例。图1～图5分别是表示工序顺序的剖面图。另外，图6是本发明的半导体装置的平面图，图5是图6的X-X线剖面图。另外，半导体衬底上适当形成有MOS晶体管、多个配线、连接配线间的插塞等元件、硅氧化膜构成的元件分离区，其图示省略。另外，图6中从焊盘电极4延伸设置的配线也省略图示。
首先，如图1所示，在由硅(Si)等构成的半导体衬底1的表面上形成例如2μm膜厚的绝缘膜2(例如利用热氧化法或CVD法形成的硅氧化膜)。接着，利用涂敷(塗布)、涂覆(coating)法(利用旋涂或喷溅(spray)的涂覆)在绝缘膜2的表面上形成例如膜厚10μm的层间绝缘膜3(聚酰亚胺类树脂膜等的有机膜)。
本实施例中，由于仅绝缘膜2在耐压上有不稳定的情况，所以从确保耐压的观点来看，形成层间绝缘膜3，但也可形成不特别设有层间绝缘膜3的结构。另外，层间绝缘膜3可以是由CVD法等形成的硅氧化膜、硅氮化膜、PSG膜、BPSG膜其他绝缘膜。
接着，利用CVD法、溅射(sputtering)法、其他成膜方法形成构成焊盘电极4的铝(Al)和铜(Cu)等金属层，之后，用未图示的掩模对该金属层进行构图，在层间绝缘膜3上形成例如1μm膜厚的焊盘电极4。焊盘电极4是与半导体衬底上的未图示的输入电路和输出电路连接的外部连接用焊盘。
接着，如图2所示，以例如10μm的厚度形成覆盖焊盘电极4的端部并在焊盘电极4上具有开口部6的第一钝化膜5。为形成该第一钝化膜5，用涂敷、涂覆法将聚酰亚胺类树脂膜、阻焊剂膜等有机类材料涂敷在层间绝缘膜3和焊盘电极4表面上，实施热处理(预烤：プリベ一ク)。另外，从防止膜的翘曲的观点考虑，也可在第一钝化膜5中添加添加料(添加剂)。
接着，将被涂敷的有机类材料曝光、显影，形成使焊盘电极4的规定表面露出的上述开口部6，之后实施热处理(热烤：ホストベ一ク)。另外，第一钝化膜5覆盖层间绝缘膜3之上和焊盘电极4的端部。该第一钝化膜5和后述的第二钝化膜10是使半导体衬底1的表面稳定化，并具有使其不受腐蚀等影响的保护膜的作用的膜。
接着，将上述第一钝化膜5作为掩模使用，如图3所示，用电解镀敷法或无电解镀敷法，在从开口部6露出的焊盘电极4的表面上形成顺次层叠主要由镍构成的镍(Ni)层和主要由金构成的金(Au)层而得的镀敷层7(下层为镍层、上层为金层)。在此，在焊盘电极4的各角部不由镀敷层7覆盖，而呈露出部8残留的状态。另外，在此，露出部8是指覆盖第一钝化膜5和镀敷层7之间的焊盘电极4露出的部位。
接着，如图4所示，在镀敷层7的规定区域上，通过将镀敷层7作为镀敷电极适用的电解镀敷法，固定焊锡球，形成导电端子9。导电端子9由焊锡球构成的情况下，具有容易形成导电端子9的优点。导电端子9的高度例如是100μm。
另外，通过丝网印刷焊锡，并由热处理使该焊锡进行回流焊，从而也可形成同样的导电端子9(焊锡突起)。导电端子9由焊锡突起构成的情况下，具有可更加高精度地形成微细形状的端子的优点。另外，导电端子9可以以金为材料，但其材料不作特别限定。
其次，如图5、6所示，在半导体衬底1的表面上通过涂敷、涂覆法形成例如10μm厚度的由聚酰亚胺类树脂膜、阻焊剂膜等的有机类材料构成的第二钝化膜10(修复钝化膜：repair passivation)。另外，形成第二钝化膜10时的热处理(预烤、热烤)、曝光、显影工序与形成上述第一钝化膜5时的工序相同。第二钝化膜10覆盖镀敷层7和第一钝化膜5之间的焊盘电极4的露出部8而形成。
由此，可防止水、药剂等经由露出部8侵入到焊盘电极4的表面，所以能够防止焊盘电极4的腐蚀，提高半导体装置的可靠性。另外，第二钝化膜10覆盖导电端子9的侧壁的一部分形成。因此，可防止水、药剂等在导电端子9的侧壁传递而侵入焊盘电极4，进一步提高可靠性。
另外，如已述，产生露出部8的原因有多种多样(添加料的影响、第一钝化膜5和镀敷层7的密接性等)，但是，本发明不限于这些原因，而广泛适用于产生露出部8的半导体装置及其制造方法。

Claims (10)

1.一种半导体装置，其特征在于，具有：
焊盘电极，其经由绝缘膜形成在半导体衬底上；
第一钝化膜，其覆盖上述焊盘电极的端部，并在上述焊盘电极之上具有开口部；
镀敷层，其经由上述开口部而形成在上述焊盘电极之上；
导电端子，其形成在上述镀敷层的表面上，与上述焊盘电极电连接；
第二钝化膜，其覆盖上述镀敷层和上述第一钝化膜之间的上述焊盘电极的露出部而形成。
2.如权利要求1所述的半导体装置，其特征在于，上述第二钝化膜覆盖上述导电端子的侧壁的一部分。
3.如权利要求1或2所述的半导体装置，其特征在于，上述第一和第二钝化膜由有机材料构成。
4.如权利要求1～3任一项所述的半导体装置，其特征在于，上述镀敷层由镍层以及金层的层叠结构构成。
5.如权利要求1～4任一项所述的半导体装置，其特征在于，上述绝缘膜由氧化膜和层间绝缘膜构成。
6.一种半导体装置的制造方法，其特征在于，具有以下工序：
形成覆盖经由绝缘膜形成在半导体衬底上的焊盘电极的端部的第一钝化膜的工序；
在上述焊盘电极表面通过电解镀敷法或无电解镀敷法形成镀敷层的工序；
在上述镀敷层的表面形成导电端子的工序；
覆盖上述镀敷层和上述第一钝化膜之间的上述焊盘电极的露出部而形成第二钝化膜的工序。
7.如权利要求6所述的半导体装置的制造方法，其特征在于，上述第二钝化膜覆盖上述导电端子的侧壁的一部分。
8.如权利要求6或7所述的半导体装置的制造方法，其特征在于，
上述第一和第二钝化膜由有机材料构成。
9.如权利要求6～8任一项所述的半导体装置的制造方法，其特征在于，形成上述镀敷层的工序包括：由电解镀敷法或无电解镀敷法形成镍层的工序和在上述镍层的表面上由电解镀敷法或无电解镀敷法形成金层的工序。
10.如权利要求6～9任一项所述的半导体装置的制造方法，其特征在于，上述绝缘膜由氧化膜和层间绝缘膜构成。
CNA2006100926710A 2005-06-15 2006-06-13 半导体装置及其制造方法 Pending CN1881573A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP174921/05 2005-06-15
JP2005174921A JP2006351766A (ja) 2005-06-15 2005-06-15 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
CN1881573A true CN1881573A (zh) 2006-12-20

Family

ID=37076003

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2006100926710A Pending CN1881573A (zh) 2005-06-15 2006-06-13 半导体装置及其制造方法

Country Status (7)

Country Link
US (1) US20060289991A1 (zh)
EP (1) EP1737036A2 (zh)
JP (1) JP2006351766A (zh)
KR (1) KR20060131642A (zh)
CN (1) CN1881573A (zh)
SG (1) SG128597A1 (zh)
TW (1) TW200735313A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110007502A (zh) * 2012-09-11 2019-07-12 三星显示有限公司 传感器基板及其制造方法
CN111492093A (zh) * 2017-12-19 2020-08-04 Ｊｘ金属株式会社 半导体晶片及其制造方法
CN111564423A (zh) * 2019-02-14 2020-08-21 东芝存储器株式会社 半导体装置及其制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7952200B2 (en) * 2008-07-16 2011-05-31 Infineon Technologies Ag Semiconductor device including a copolymer layer
US8455361B2 (en) * 2010-01-07 2013-06-04 Texas Instruments Incorporated Electroless plating of porous and non-porous nickel layers, and gold layer in semiconductor device
DE102012223904A1 (de) * 2012-10-05 2014-04-10 Continental Automotive Gmbh Verfahren zum Herstellen eines elektronischen Hochstrom-Schaltkreises mittels Gasspritz-Technologie und Abdichten mit isolierendem Polymer
JP6424610B2 (ja) * 2014-04-23 2018-11-21 ソニー株式会社 半導体装置、および製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003037129A (ja) * 2001-07-25 2003-02-07 Rohm Co Ltd 半導体装置およびその製造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110007502A (zh) * 2012-09-11 2019-07-12 三星显示有限公司 传感器基板及其制造方法
CN111492093A (zh) * 2017-12-19 2020-08-04 Ｊｘ金属株式会社 半导体晶片及其制造方法
CN111492093B (zh) * 2017-12-19 2022-03-15 Ｊｘ金属株式会社 半导体晶片及其制造方法
CN111564423A (zh) * 2019-02-14 2020-08-21 东芝存储器株式会社 半导体装置及其制造方法
CN111564423B (zh) * 2019-02-14 2023-09-29 铠侠股份有限公司 半导体装置及其制造方法

Also Published As

Publication number Publication date
SG128597A1 (en) 2007-01-30
KR20060131642A (ko) 2006-12-20
TW200735313A (en) 2007-09-16
US20060289991A1 (en) 2006-12-28
EP1737036A2 (en) 2006-12-27
JP2006351766A (ja) 2006-12-28

Similar Documents

Publication Publication Date Title
US7459729B2 (en) Semiconductor image device package with die receiving through-hole and method of the same
US7812434B2 (en) Wafer level package with die receiving through-hole and method of the same
US8749048B2 (en) Package structure
US7271024B2 (en) Method for fabricating sensor semiconductor device
US8703600B2 (en) Electronic component and method of connecting with multi-profile bumps
CN1881573A (zh) 半导体装置及其制造方法
CN1658387A (zh) 半导体装置及其制造方法
CN1941340A (zh) 半导体装置及其制造方法
JP2008235869A (ja) イメージセンサモジュール構造および半導体デバイスパッケージの形成方法
CN1722429A (zh) 半导体器件
JP2008228308A (ja) ビルドインパッケージキャビティを有するイメージセンサモジュールおよびその方法
KR20080064090A (ko) 멀티-칩 패키지 및 그 제조 방법
CN1881572A (zh) 半导体装置及其制造方法
CN101064294A (zh) 电路装置及电路装置的制造方法
CN1828883A (zh) 半导体装置及其制造方法
CN1700458A (zh) 具有第一和第二导电凸点的半导体封装及其制造方法
CN1462072A (zh) 半导体封装件及其制造方法
JP2005235860A (ja) 半導体装置及びその製造方法
US20210057380A1 (en) Semiconductor package
KR20080114603A (ko) 의사 칩을 가진 반도체 소자 패키지
CN1747161A (zh) 半导体装置及半导体装置的制造方法
CN100350581C (zh) 整合打线及倒装封装的芯片结构及工艺
TWI744825B (zh) 晶片嵌入式基板結構與晶片封裝結構及其製造方法
TWI817377B (zh) 具有中介結構的半導體裝置及其製備方法
JP5036217B2 (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication