CN111564423A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN111564423A
CN111564423A CN201910604143.6A CN201910604143A CN111564423A CN 111564423 A CN111564423 A CN 111564423A CN 201910604143 A CN201910604143 A CN 201910604143A CN 111564423 A CN111564423 A CN 111564423A
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metal
electrode pad
metal bump
copper
semiconductor device
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CN111564423B (zh
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丹羽恵一
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明涉及一种半导体装置及其制造方法。本实施方式的半导体装置具备衬底。绝缘膜设置在衬底的上方。电极垫设置在绝缘膜上。金属凸块设置在电极垫的表面。侧壁膜设置在金属凸块的侧面且包含金属氧化物或金属氢氧化物。障壁金属层具有第1部分及第2部分，所述第1部分设置在金属凸块与电极垫之间且包含金属，所述第2部分在金属凸块的周边至少设置在电极垫且包含金属氧化物或金属氢氧化物。

Description

半导体装置及其制造方法
相关申请案的引用
本申请案以2019年2月14日申请的先行的日本专利申请案第2019-24640号的优先权的利益为基础，且追求其利益，其内容整体通过引用包含在本文中。
技术领域
本发明的实施例涉及一种半导体装置及其制造方法。
背景技术
为了能够进行倒装芯片接合，有在半导体晶圆的电极垫上形成金属凸块的情况。为了形成金属凸块，在电极垫上形成障壁金属层，在该障壁金属层上形成金属凸块。在形成金属凸块之后，为了抑制金属凸块间的短路，必须将障壁金属层去除。
然而，在该障壁金属层的去除步骤中，存在蚀刻至金属凸块的侧壁而导致金属凸块变细的情况。另外，在障壁金属层的去除步骤中，也存在导致电极垫的表面腐蚀的情况。
如果金属凸块变细，那么存在金属凸块从电极垫偏离或折断的担忧。如果电极垫的表面腐蚀，那么密封树脂与电极垫的密接性变差。这些情况会使半导体装置的可靠性劣化。
发明内容
本实施方式的半导体装置具备衬底。绝缘膜设置在衬底的上方。电极垫设置在绝缘膜上。金属凸块设置在电极垫的表面。侧壁膜设置在金属凸块的侧面且包含金属氧化物或金属氢氧化物。障壁金属层具有第1部分及第2部分，所述第1部分设置在金属凸块与电极垫之间且包含金属，所述第2部分在金属凸块的周边至少设置在电极垫且包含金属氧化物或金属氢氧化物。
附图说明
图1是表示本实施方式的半导体装置的局部构成的剖视图。
图2(A)、(B)是表示本实施方式的半导体装置的制造方法的一例的剖视图。
图3(A)、(B)是表示继图2之后的半导体装置的制造方法的剖视图。
图4(A)、(B)是表示继图3之后的半导体装置的制造方法的剖视图。
图5(A)、(B)是表示继图4之后的半导体装置的制造方法的剖视图。
图6(A)、(B)是表示继图5之后的半导体装置的制造方法的剖视图。
图7(A)、(B)是表示继图6之后的半导体装置的制造方法的剖视图。
图8是表示障壁金属层的蚀刻步骤中的金属凸块的侧蚀刻量的曲线图。
图9是表示所述实施方式的变化例的构成例的剖视图。
图10(A)、(B)是表示所述实施方式的变化例2的构成例的剖视图。
具体实施方式
以下，参照附图对本发明的实施方式进行说明。在图1～图8中，对相同或类似的构成标注相同的符号，并省略重复的说明。
将参考附图解释实施例。本发明不限于所述实施例。在所述实施例中，“上方向”或“下方向”是指当垂直于其上设置半导体元件的半导体衬底表面的方向被假设为“上方向”时的相对方向。因此，术语“上方向”或“下方向”有时和基于重力加速方向的上方向或下方向不同。在本说明书和图式中，与前述图式中描述的元件相同的元件由类似的参考符号表示，并且其详细解释在适当时被省略。
本实施方式的半导体装置具备衬底。绝缘膜设置在衬底的上方。电极垫设置在绝缘膜上。金属凸块设置在电极垫的表面。侧壁膜设置在金属凸块的侧面且包含金属氧化物或金属氢氧化物。障壁金属层具有第1部分及第2部分，所述第1部分设置在金属凸块与电极垫之间且包含金属，所述第2部分在金属凸块的周边至少设置在电极垫且包含金属氧化物或金属氢氧化物。
图1是表示本实施方式的半导体装置的局部构成的剖视图。半导体装置1例如可为NAND(Not And，与非)型闪速存储器等半导体芯片或半导体封装。此外，在图1中，为方便起见，表示了未连接状态的金属凸块70及金属球80。然而，金属凸块70及金属球80通过倒装芯片接合，积层在其它半导体芯片或安装衬底。此时，金属球80连接于其它半导体芯片或安装衬底的电极垫。进而，半导体芯片被封装化，且在金属凸块70及金属球80的周围设置密封树脂。在图1中，省略了其它半导体芯片、安装衬底及密封树脂的图示。
半导体装置1具备半导体衬底10、层间绝缘膜20、配线30、障壁金属层40、60、电极垫50、金属凸块70、侧壁膜75、及金属球80。
在半导体衬底10上，设置着存储单元阵列、CMOS(Complementary Metal OxideSemiconductor，互补金属氧化物半导体)电路、二极管、电阻元件、电容器等半导体元件(未图示)。半导体衬底10例如为硅衬底等。
层间绝缘膜20设置在半导体衬底10的上方，且被覆半导体元件。层间绝缘膜20例如使用氧化硅膜或氮化硅膜等绝缘膜。多条配线30埋入至层间绝缘膜20，构成多层配线构造。配线30例如使用铜、钨等导电性金属。另外，最上层的配线30的表面从层间绝缘膜20露出，经由障壁金属层40而电连接于电极垫50。
障壁金属层40设置在最上层的配线30上，以抑制电极垫50与配线30之间的金属材料的扩散。障壁金属层40例如使用钛及钽的积层膜等。电极垫50设置在障壁金属层40上，且经由障壁金属层40而电连接于配线30。电极垫50例如主要使用铝等导电性金属。
障壁金属层60为了将金属凸块70形成在电极垫50的上方，而设置在电极垫50上。金属凸块70设置在障壁金属层60上，且经由障壁金属层60而电连接于电极垫50。
障壁金属层60包含：作为第1部分的障壁金属层60＿1，设置在金属凸块70与电极垫50之间；及作为第2部分的金属氧化膜60＿2，在金属凸块70的周边设置在电极垫50或层间绝缘膜20上。障壁金属层60＿1设置在第1区域R1，金属氧化膜60＿2设置在第2区域R2。在区域R1、R2以外的区域R20中，障壁金属层60被去除。因此，相互相邻的多个金属凸块70被电绝缘。此外，区域R1是金属凸块70的形成区域。区域R2处于金属凸块70的周边，其外缘处于电极垫50的外侧。也就是说，如果将区域R1、R2合并，那么成为包含电极垫50在内的与电极垫50大致相同或比电极垫50宽的区域。
障壁金属层60＿1例如使用钛及铜的积层膜。金属氧化膜60＿2例如是钛(或氧化钛)及氧化铜的积层膜。
金属凸块70设置在电极垫50的上方，经由障壁金属层60＿1电连接于电极垫50。在金属凸块70的侧面，设置着侧壁膜75。侧壁膜75由金属凸块70的材料的氧化物或氢氧化物(例如，氧化铜或氢氧化铜)构成。侧壁膜75被覆金属凸块70的侧面，以便在半导体装置1的制造步骤中的障壁金属层60的蚀刻步骤中抑制金属凸块70的侧蚀刻。在金属凸块70上，设置着金属球80。
此处，障壁金属层60(60＿1及60＿2)不仅残置在区域R1中的金属凸块70的下方，而且也残置在区域R2中的金属凸块70的周边的电极垫50及层间绝缘膜20上。也就是说，障壁金属层60遍及比金属凸块70的底面积更宽的范围而设置，且以被覆电极垫50的表面的方式设置。因此，被覆电极垫50及层间绝缘膜20的障壁金属层60的面积(区域R1及R2的面积)比电极垫50与金属凸块70的接触面积(R1的面积)大出相当于金属氧化膜60＿2的量。金属氧化膜60＿2被覆电极垫50的表面，以便在障壁金属层60的蚀刻步骤中抑制电极垫50的表面蚀刻。
这样，通过侧壁膜75及金属氧化膜60＿2保护金属凸块70的侧壁及电极垫50的表面，能够在障壁金属层60的蚀刻步骤中，抑制金属凸块70变细及电极垫50腐蚀。结果，本实施方式的半导体装置1能够获得高可靠性。
接下来，对本实施方式的半导体装置的制造方法进行说明。
图2(A)～图7(B)是表示本实施方式的半导体装置的制造方法的一例的剖视图。首先，在半导体衬底10上形成半导体元件(未图示)。半导体衬底例如可为硅衬底等。半导体元件例如可为存储单元阵列、晶体管、二极管、电阻元件、电容器等。
接下来，在半导体衬底10及半导体元件的上方，如图2(A)所示，形成多个层间绝缘膜20及多条配线30。层间绝缘膜20及配线30积层，构成多层配线构造。层间绝缘膜20例如使用氧化硅膜或氮化硅膜等绝缘材料。配线30例如使用铜、钨等导电性金属。另外，最上层的配线30的表面经由障壁金属层40电连接于电极垫50。
障壁金属层40在最上层的配线30上，作为电极垫50与配线30之间的防扩散层形成。障壁金属层40例如使用钛及钽的积层膜等。另外，障壁金属层40以电极垫50或配线30的材料不相互扩散的方式作为防扩散膜而发挥功能。
电极垫50是以障壁金属层40作为防扩散层而形成在配线30及障壁金属层40上。电极垫50与配线30电连接。电极垫50例如主要使用铝等导电性金属。
接下来，如图2(B)所示，在电极垫50及层间绝缘膜20的表面上，形成障壁金属层60。障壁金属层60例如使用溅镀法形成。障壁金属层60也作为图3(B)所示的金属凸块70的晶种层而发挥功能。障壁金属层60例如主要使用设置在电极垫50上的钛膜与设置在钛膜上的铜膜的积层膜。此外，障壁金属层的构成并不仅限定于钛与铜的积层膜。
接下来，如图3(A)所示，使用光刻技术，在电极垫50及层间绝缘膜20上涂布第1掩模材M1，将第1掩模材M1图案化。由此，将电极垫50的表面中处于金属凸块70的形成区域(第1区域)R1的第1掩模材M1去除。第1掩模材M1被覆区域R1以外的区域R10。区域R10包含未形成金属凸块70的电极垫50上的区域及层间绝缘膜20的区域。
接下来，如图3(B)所示，将第1掩模材M1用作掩模，在金属凸块70的形成区域R1上选择性地堆积金属凸块70的材料。金属凸块70例如主要使用铜等导电性金属。金属凸块70例如利用电解镀覆法或无电解镀覆法形成在障壁金属层60上。
接下来，如图4(A)所示，将第1掩模材M1用作掩模，在金属凸块70上堆积金属球80的材料。金属球80例如使用焊料(锡)等导电性金属。金属球80例如也利用电解镀覆法或无电解镀覆法形成在金属凸块70上。
接下来，通过将第1掩模材M1去除，获得图4(B)所示的构造。
接下来，使用光刻技术，在层间绝缘膜20及障壁金属层60上涂布第2掩模材M2，如图5(A)所示，将金属凸块70的周围中的处于电极垫50的表面区域(第2区域)R2的第2掩模材M2去除。由此，处于金属凸块70周围的电极垫50及处于层间绝缘膜20的区域R10的障壁金属层60露出。另一方面，处于区域R2以外的层间绝缘膜20的区域R20的障壁金属层60由第2掩模材M2被覆。另外，处于区域R1的障壁金属层60由金属凸块70被覆。
接下来，如图5(B)所示，将第2掩模材M2用作掩模，通过利用含氧气体的等离子体，对在金属凸块70的侧面及区域R2中露出的障壁金属层60进行表面处理。以后，也可将该处理设为灰化处理。利用灰化处理，金属凸块70的侧面及区域R2的障壁金属层60被氧化。因此，在金属凸块70的侧面形成由金属氧化膜构成的侧壁膜75。在金属凸块70为铜的情况下，侧壁膜75成为氧化铜。另外，在区域R2中露出的障壁金属层60被选择性地氧化。由此，作为第2部分的金属氧化膜60＿2形成在区域R2。在障壁金属层60为铜及钛的积层构造的情况下，在区域R2中，铜及/或钛被氧化。由此，金属氧化膜60＿2成为氧化铜与钛(或氧化钛)的积层膜。另一方面，由第2掩模材M2及金属凸块70被覆的区域R1及R20的障壁金属层60未被氧化。也就是说，通过将金属凸块70及第2掩模材M2用作掩模将障壁金属层60选择性地灰化处理，而将未由第2掩模材M2及金属凸块70被覆的区域R2的障壁金属层60选择性地氧化。此外，方便起见，将区域R1的处于金属凸块70之下的未被氧化的障壁金属层60的部分(第1部分)设为障壁金属层60＿1。方便起见，将区域R2的被氧化的障壁金属层60设为金属氧化膜60＿2。方便起见，将在区域R20中处于层间绝缘膜20上的未被氧化的障壁金属层60设为障壁金属层60＿3。
在将第2掩模材M2去除之后，如图6(A)所示，利用湿式蚀刻，对障壁金属层60进行蚀刻。蚀刻液是能将铜及钛熔解的液体，例如，是向有机酸添加了添加剂及水而成的液体、或向氢氧化物添加了添加剂及水而成的液体。此时，侧壁膜75及金属氧化膜60＿2被残置，处于区域R20的障壁金属层60＿3被选择性地去除。处于金属凸块70之下的障壁金属层60＿1当然被残置。此外，也可使用两种蚀刻液，例如在利用能将铜熔解的蚀刻液使铜熔解之后，利用能将钛熔解的其它蚀刻液使钛熔解。除了所述包含有机酸的蚀刻液、包含氢氧化物的蚀刻液以外，还存在各种蚀刻液，也可使用这些蚀刻液。
蚀刻液有使金属凸块70或电极垫50腐蚀的可能性。然而，根据本实施方式，金属凸块70的侧面由侧壁膜75被覆，且区域R2的电极垫50及层间绝缘膜20的表面由金属氧化膜60＿2被覆。像参照图8在下文所说明的一样，氧化铜及氧化钛与铜及钛相比蚀刻速率较小。因此，金属凸块70的侧面由侧壁膜75保护，电极垫50的表面由金属氧化膜60＿2保护。由此，能够抑制金属凸块70的变细，且抑制电极垫50的腐蚀，且将区域R20的障壁金属层60选择性地去除。
另外，如上所述，区域R2的外缘处于电极垫50的外侧。因此，障壁金属层60＿1及金属氧化膜60＿2被覆电极垫50的整个表面。由此，电极垫50整体被保护，能够抑制其腐蚀。
接下来，如图6(B)所示，利用热处理，将金属球80回流焊。由此，金属球80成为大致球形状。
然后，将半导体衬底10切割，将半导体衬底10单片化成半导体芯片。半导体芯片通过倒装芯片接合被积层在其它半导体芯片或安装衬底。此时，金属凸块70上的金属球80连接于其它半导体芯片或安装衬底的电极垫。由此，配线30与其它半导体芯片或安装衬底的配线电连接。
图7(A)是表示将金属球80连接于安装衬底300的电极垫370的情况的图。这样，半导体装置1能够作为半导体芯片与安装衬底300连接。安装衬底300于其内部具有配线层330。此外，在图7(A)及图7(B)中，表示了半导体装置1的概略。另外，虽然未图示，但半导体装置1也可与其它半导体芯片倒装芯片连接。
接下来，如图7(B)所示，通过在半导体装置1与安装衬底300之间埋入树脂400，来保护金属凸块70及金属球80，保护金属球80与安装衬底300的电极垫370之间的连接。由此，完成本实施方式的半导体装置。
图8是表示参照图6(A)所说明的障壁金属层60＿3的蚀刻步骤中的金属凸块70的侧蚀刻量的曲线图。纵轴表示金属凸块70的侧蚀刻量。横轴表示蚀刻的处理时间。蚀刻液是向有机酸中添加了添加剂及水而成的液体、或向氢氧化物中添加了添加剂及水而成的液体。
线L0表示在障壁金属层60＿3的蚀刻步骤之前未被灰化处理的情况下的侧蚀刻量。也就是说，线L0表示未设置侧壁膜75的情况下的金属凸块70的侧蚀刻量。线L1表示在障壁金属层60＿3的蚀刻步骤之前进行了灰化处理的情况下的侧蚀刻量。也就是说，线L1表示设置着侧壁膜75的情况下的金属凸块70的侧蚀刻量。
根据该曲线图可知，如果设置着侧壁膜75，那么金属凸块70的侧蚀刻量减少。由此，可抑制金属凸块70的变细，维持金属凸块70的宽度。同样地，金属氧化膜60＿2的蚀刻速率也比未被氧化的障壁金属层60的蚀刻速率低，也可抑制电极垫50表面的腐蚀。
此外，在所述实施方式中，侧壁膜75及金属氧化膜60＿2例如为氧化铜(CuO)等那样的金属氧化物。然而，侧壁膜75例如也可为氢氧化铜(CuOH)等那样的金属氢氧化物。另外，膜60＿2也可为金属氢氧化膜。例如，在灰化处理时，有金属凸块70的侧壁及障壁金属层60因氧及空气中的水分而被氧化及氢氧化的情况。因此，有膜75及60＿2成为金属氧化物及金属氢氧化物的混合物的情况。即便为这样的金属氧化物及金属氢氧化物的混合物，膜75及60＿2在蚀刻步骤中，也能够作为金属凸块70及电极垫50的保护膜而发挥功能。另外，在想要获得更多的氢氧化物的情况下，也可不仅导入氧气而且导入水蒸气气体来进行灰化处理。
另外，障壁金属层60在形成金属凸块70之前的工艺中，有暴露于大气或水中的情况，也有暴露于用来进行表面洗净的含氧气体的等离子体中的情况，还有暴露于酸或碱等洗净液中的情况。由于这样的暴露，也会有区域R1的障壁金属层60＿1被氧化或氢氧化而包含微量的金属氧化物及金属氢氧化物的情况。在该情况下，障壁金属层60＿1的金属氧化物及金属氢氧化物的含量比膜60＿2的金属氧化物及金属氢氧化物的含量少。
(变化例)
图9是表示所述实施方式的变化例的构成例的剖视图。在所述实施方式中，金属球80以直接接触的方式设置在金属凸块70上。另一方面，在本变化例中，防扩散膜90设置在金属球80与金属凸块70之间。防扩散膜90例如使用镍等导电性金属。防扩散膜90抑制铜或锡在金属凸块70与金属球80之间相互扩散。本变化例的其它构成可与所述实施方式的对应的构成相同。
防扩散膜90只要在图3(B)所示的步骤中，在金属凸块70的堆积后，形成在金属凸块70上即可。然后，在防扩散膜90上形成金属球80。本变化例的其它制造步骤可与所述实施方式的制造步骤相同。
这样，即便防扩散膜90设置在金属凸块70与金属球80之间，本实施方式的效果也不会消失。
(变化例2)
图10(A)及图10(B)是表示所述实施方式的变化例2的构成例的剖视图。在变化例2中，金属凸块70及金属球80仅设置在半导体装置1的两侧边，比所述实施方式的金属凸块70及金属球80少。变化例2的其它构成可与所述实施方式相同。半导体装置1也可为这样的方式。
接下来，如图10(B)所示，通过在半导体装置1与安装衬底300之间埋入树脂400，来保护金属凸块70及金属球80，保护金属球80与安装衬底300的电极垫370之间的连接。由此，完成变化例2的半导体装置。
这样，即便根据安装衬底300的方式或其它半导体芯片的方式任意地变更金属凸块70及金属球80的配置，本实施方式的效果也不会消失。
虽然已经描述了某些实施例，但是这些实施例仅以举例方式呈现，并且不打算限制本发明的范围。事实上，本文描述的新颖方法和系统可以多种其它形式体现；此外，采取本文所描述的方法和系统的形式的各种省略、替代和改变可在不偏离本发明精神的情况下作出。随附权利要求和其对等物打算涵盖这些形式或修改，就像属于本发明的范围和精神内一样。

Claims (12)

1.一种半导体装置，具备：
衬底；
绝缘膜，设置在所述衬底的上方；
电极垫，设置在所述绝缘膜上；
金属凸块，设置在所述电极垫的表面；
侧壁膜，设置在所述金属凸块的侧面且包含金属氧化物或金属氢氧化物；以及
障壁金属层，具有第1部分及第2部分，所述第1部分设置在所述金属凸块与所述电极垫之间且包含金属，所述第2部分在所述金属凸块的周边至少设置在所述电极垫且包含金属氧化物或金属氢氧化物。
2.根据权利要求1所述的半导体装置，其中所述障壁金属层的面积比所述电极垫与所述金属凸块的接触面积大。
3.根据权利要求1所述的半导体装置，其中所述电极垫包含铝，
所述金属凸块包含铜，
所述侧壁膜包含氧化铜或氢氧化铜，
所述第1部分是钛与铜的积层膜，
所述第2部分是钛与氧化铜或氢氧化铜的积层膜。
4.根据权利要求2所述的半导体装置，其中所述电极垫包含铝，
所述金属凸块包含铜，
所述侧壁膜包含氧化铜或氢氧化铜，
所述第1部分是钛与铜的积层膜，
所述第2部分是钛与氧化铜或氢氧化铜的积层膜。
5.根据权利要求1所述的半导体装置，还具备：
金属球，设置在所述金属凸块上；以及
防扩散膜，设置在所述金属球与所述金属凸块之间。
6.根据权利要求5所述的半导体装置，其中所述金属球包含锡，
所述防扩散膜包含镍。
7.一种半导体装置的制造方法，具备：
在处于衬底上方的绝缘膜形成电极垫；
在所述电极垫及所述绝缘膜的表面上形成障壁金属层；
形成将所述电极垫的表面中形成金属凸块的第1区域以外的区域及所述绝缘膜的表面被覆的第1掩模材；
在所述第1区域上堆积该金属凸块的材料；
在将所述第1掩模材去除之后，在所述绝缘膜及所述障壁金属层上形成第2掩模材；
以将所述金属凸块的周围中的处于所述电极垫上的第2区域的所述第2掩模材去除的方式形成该第2掩模材；
将所述障壁金属层的表面及所述金属凸块的侧面氧化或氢氧化；以及
在将所述第2掩模材去除之后，将所述第1及第2区域以外的未被氧化或氢氧化的所述障壁金属层选择性地去除。
8.根据权利要求7所述的半导体装置的制造方法，其中在将所述第1及第2区域以外的所述障壁金属层去除之后，所述障壁金属层的面积比所述电极垫与所述金属凸块的接触面积大。
9.根据权利要求7所述的半导体装置的制造方法，其中所述金属凸块及所述障壁金属层的氧化或氢氧化是通过利用含氧气体进行灰化处理来执行。
10.根据权利要求7所述的半导体装置的制造方法，还具备：继所述金属凸块堆积之后，在所述金属凸块上形成金属球。
11.根据权利要求7所述的半导体装置的制造方法，还具备：
继所述金属凸块堆积之后，在所述金属凸块上形成防扩散膜；
在所述防扩散膜上形成金属球。
12.根据权利要求7所述的半导体装置的制造方法，其中所述电极垫包含铝，
所述金属凸块包含铜，
形成在所述金属凸块侧面的侧壁膜包含氧化铜或氢氧化铜，
所述障壁金属层包含第1区域及第2区域，所述第1区域由钛与铜的积层膜构成，所述第2区域由钛与氧化铜或氢氧化铜的积层膜构成。
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