CN110676227A - 包括凸块结构的半导体芯片和包括半导体芯片的半导体封装 - Google Patents

包括凸块结构的半导体芯片和包括半导体芯片的半导体封装 Download PDF

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Publication number
CN110676227A
CN110676227A CN201910309072.7A CN201910309072A CN110676227A CN 110676227 A CN110676227 A CN 110676227A CN 201910309072 A CN201910309072 A CN 201910309072A CN 110676227 A CN110676227 A CN 110676227A
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Prior art keywords
layer
electrode pad
pad
semiconductor chip
protective layer
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CN201910309072.7A
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Inventor
裴镇国
郑显秀
柳翰成
李仁荣
李灿浩
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN110676227A publication Critical patent/CN110676227A/zh
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Abstract

一种半导体芯片包括半导体衬底。电极焊盘设置在半导体衬底上。电极焊盘包括低k材料层。第一保护层至少部分地围绕电极焊盘。第一保护层包括位于其上部的第一开口。缓冲焊盘电连接到电极焊盘。第二保护层至少部分地围绕缓冲焊盘。第二保护层包括位于其上部的第二开口。柱层和焊料层顺序地堆叠在缓冲焊盘上。缓冲焊盘的厚度大于电极焊盘的厚度。第一开口在平行于半导体衬底的上表面的第一方向上的宽度等于或大于第二开口在第一方向上的宽度。

Description

包括凸块结构的半导体芯片和包括半导体芯片的半导体封装
相关申请的交叉引用
本申请要求于2018年7月3日在韩国知识产权局提交的韩国专利申请No.10-2018-0077321的优先权，并在此通过引用完整地并入其公开内容。
技术领域
本公开涉及一种半导体芯片，更具体地，涉及包括凸块结构的半导体芯片和包括半导体芯片的半导体封装。
背景技术
电子设备变得更小并且能够执行更多功能。结果，电子设备中使用的半导体芯片变得更加高度集成。这种半导体芯片可以具有带有精细间距的小连接端子。为了封装这种高容量半导体芯片，可以使用凸块结构。半导体封装中包括的凸块结构的尺寸也稳定地减小，以容纳更加高度集成的半导体芯片。
发明内容
一种半导体芯片包括半导体衬底。电极焊盘设置在半导体衬底上。电极焊盘包括低k材料层。第一保护层至少部分地围绕电极焊盘。第一保护层包括位于其上部的第一开口。缓冲焊盘电连接到电极焊盘。第二保护层至少部分地围绕缓冲焊盘。第二保护层包括位于其上部的第二开口。柱层和焊料层顺序地堆叠在缓冲焊盘上。缓冲焊盘的厚度大于电极焊盘的厚度。第一开口在平行于半导体衬底的上表面的第一方向上的宽度等于或大于第二开口在第一方向上的宽度。
一种半导体芯片包括半导体衬底，所述半导体衬底具有包括低k材料的层间电介质以及布置在所述层间电介质上的电极焊盘。保护层至少部分地覆盖所述电极焊盘的侧表面和上表面。所述保护层包括内部空间，所述内部空间具有位于所述内部空间的下部的第一开口和位于所述内部空间的上部的第二开口；缓冲焊盘设置在所述保护层的所述内部空间中，并通过所述第一开口电连接到所述电极焊盘。凸块结构(不位于所述保护层的所述内部空间中)形成在所述保护层上方并通过所述第二开口电连接到所述缓冲焊盘，第一开口在平行于半导体衬底的上表面的第一方向上的宽度等于或大于第二开口在第一方向上的宽度。
一种半导体封装包括封装衬底，所述封装衬底具有衬底焊盘和安装在所述封装衬底上方的半导体芯片。所述半导体芯片包括电极焊盘，所述电极焊盘设置在所述半导体衬底上并具有低k材料层。第一保护层包括位于所述第一保护层的上部的第一开口，并至少部分地围绕所述电极焊盘。缓冲焊盘电连接到电极焊盘。第二保护层包括位于所述第二保护层的上部的第二开口，并至少部分地围绕所述缓冲焊盘。柱层和焊料层顺序地堆叠在缓冲焊盘上。缓冲焊盘的厚度大于电极焊盘的厚度。第一开口在平行于半导体衬底的上表面的第一方向上的宽度等于或大于第二开口在第一方向上的宽度。所述焊料层电连接到所述衬底焊盘。
附图说明
根据以下结合附图进行的详细描述，将更清楚地理解本发明构思的实施例，在附图中：
图1是示出了根据本发明构思的示例性实施例的半导体封装的截面图；
图2是根据本发明构思的示例性实施例的半导体芯片的截面图；
图3至图11是示出了根据本发明构思的示例性实施例的制造半导体芯片的方法的截面图；
图12是示出了根据本发明构思的示例性实施例的制造半导体封装的方法的截面图；
图13是示出了根据本发明构思的示例性实施例的半导体封装中的缓冲焊盘的厚度和凸块结构下的应力的图；以及
图14是根据本发明构思的示例性实施例的半导体封装的结构的框图。
具体实施方式
在下文中，将参照附图详细描述本发明构思的示例性实施例。
图1是根据本发明构思的示例性实施例的半导体封装1的截面图。
参照图1，半导体封装1可以包括半导体器件100、封装衬底300以及将半导体器件100连接到封装衬底300的连接结构200。半导体封装1可以是倒装芯片封装，其中以面朝下的方式通过连接结构200将半导体器件100安装在封装衬底300上方。
半导体器件100和连接结构200可以一起被认为是半导体芯片10。具体地，半导体芯片10可以包括形成在半导体衬底110上的电极焊盘210。电极焊盘210可以被配置为向外部扩展半导体器件100中包括的电路功能。可以通过半导体制造工艺在半导体芯片10中形成包括用于执行半导体器件100的电路功能的个体单元元件150的电路部分。例如，包括半导体芯片10的半导体器件100可以包括晶体管、电阻器、电容器、导电布线和/或布置在它们之间的绝缘层。
可以通过形成在半导体器件100的电路部分上的第一保护层212来部分地暴露电极焊盘210。电极焊盘210可以通过上通孔160电连接到半导体器件100的电路部分，因此半导体器件100的电路部分可以电连接到封装衬底300。
根据本发明构思的一些示例性实施例，半导体芯片10可以包括逻辑芯片和/或存储器芯片。逻辑芯片可以包括例如微处理器、模拟器件和/或数字信号处理器。此外，举例来讲，存储器芯片可以包括：易失性存储器芯片，诸如动态随机存取存储器(DRAM)或静态RAM(SRAM)；或非易失性存储器芯片，诸如相变RAM(PRAM)、铁电RAM(FeRAM)或电阻RAM(RRAM)。根据本发明构思的一些示例性实施例，半导体芯片10可以包括高带宽存储器器件。根据本发明构思的一些示例性实施例，半导体芯片10可以包括插入器和/或控制器。
半导体芯片10可以包括不包括再分布层的高带宽存储器器件。与其他存储器器件相比，高带宽存储器器件可能需要较大部分的连接结构用于信号传输。因此，再分布层的形成可能伴随着电路设计和半导体制造工艺上的困难。
封装衬底300可以包括基部310、内部连接焊盘320、绝缘层330、外部连接焊盘340和外部端子350。
基部310可包括酚醛树脂、环氧树脂和/或聚酰亚胺。内部连接焊盘320可以形成在基部310的一侧的上方，并且可以将封装衬底300电连接到连接结构200。绝缘层330可以形成在基部310的上表面上方，并且可以暴露内部连接焊盘320的上表面的一部分。外部连接焊盘340可以形成在基部310的另一侧上，并且外部端子350可以附接在外部连接焊盘340上。例如，外部端子350可以包括焊料球或焊料凸块。外部端子350可以将半导体封装1电连接到外部电子设备。
根据本公开的一些示例性实施例，当封装衬底300是印刷电路板(PCB)时，基部310可以通过将聚合物材料压缩至一定厚度而以膜状态形成，该聚合物材料例如是热固性树脂、环氧树脂或酚醛树脂，如阻燃剂4(FR-4)、双马来酰亚胺三嗪(BT)和/或味之素积层膜(ajinomoto build-up film)(ABF)。在将铜箔涂敷到基部310的两侧之后，可以通过形成布线图案来实现基部310，该布线图案是电信号的传输路径。另外，内部连接焊盘320和外部连接焊盘340可以通过穿过基部310的通孔彼此电连接。除了内部连接焊盘320和外部连接焊盘340之外，阻焊剂可以完全涂覆在基部310的下表面和上表面上，以形成下保护层和上保护层。
根据本公开的一些示例性实施例，PCB可以被划分为仅在PCB的单侧上具有布线的单层PCB和在PCB的两侧上具有布线的双层PCB。此外，通过使用被称为预浸料的绝缘体，可以形成的铜箔层的数量可以是三层或更多层。可以根据形成的铜箔层的数量通过形成三个或更多个布线层来形成具有多层布线的PCB。根据本发明构思的示例性实施例的半导体封装1的封装衬底300不限于PCB的结构或材料。
半导体芯片10的凸块结构BS可以附接到封装衬底300的内部连接焊盘320，因此半导体芯片10的电极焊盘210可以电连接到内部连接焊盘320。凸块结构BS可以包括种子层230、柱层240和焊料层250。
底部填充410可以形成在半导体芯片10和封装衬底300之间的空间中。底部填充410可以围绕连接结构200的侧壁以填充相邻连接结构200之间的空间。
模制构件420可以保护半导体芯片10免受外部影响(例如冲击)。为了执行这种作用，模制构件420可包括环氧树脂模制化合物或树脂等。另外，可以通过诸如压缩模制、层压或丝网印刷等的工艺来形成模制构件420。根据本发明构思的一些示例性实施例，模制构件420可以覆盖半导体芯片10的侧表面，使得半导体芯片10的上表面可以暴露出来。
图2是根据本发明构思的示例性实施例的半导体芯片10的截面图。
参考图2，示出了半导体芯片10，其中连接结构200布置在半导体器件100的上表面上方。
半导体器件100和连接结构200可以一起构成半导体芯片10。为了便于说明，第一方向X和第二方向Y被定义为平行于半导体衬底110的上表面的平面，并且第三方向Z垂直于半导体衬底110的上表面。
半导体芯片10可包括：布置在半导体器件100上方的电极焊盘210；至少部分地围绕电极焊盘210的第一保护层212；电连接到电极焊盘210的缓冲焊盘220；至少部分地围绕缓冲焊盘220的第二保护层222；以及布置在缓冲焊盘220上方的凸块结构BS。
缓冲焊盘220在第三方向Z上的厚度220T可以大于电极焊盘210在第三方向Z上的厚度210T。根据本发明构思的一些示例性实施例，缓冲焊盘220的厚度220T可以是电极焊盘210的厚度210T的约5倍至约10倍。
缓冲焊盘220在第一方向X上的宽度220W可以大于电极焊盘210在第一方向上的宽度210W。根据本发明构思的一些示例性实施例，缓冲焊盘220的宽度220W可以是电极焊盘210的宽度210W的约1.5倍至约3倍。
柱层240在第一方向X上的宽度240W可以大于电极焊盘210在第一方向X上的宽度210W，并且可以小于缓冲焊盘220在第一方向X上的宽度220W。
因此，当缓冲焊盘220厚于且大于电极焊盘210时，缓冲焊盘220可以减轻施加到电极焊盘210和半导体器件100的应力。
第二保护层222的第二开口在第一方向X上的宽度222W可以与第一保护层212的第一开口在第一方向X上的宽度212W基本相同。根据本发明构思的示例性实施例，第二开口的宽度222W可以小于第一开口的宽度212W。
缓冲焊盘220可以被加强，并且可以最小化当缓冲焊盘220的中心部分暴露出来时由于在形成第二保护层222的第二开口的过程中产生的氟(F)气体而引起的对缓冲焊盘220的上表面的损坏。
在半导体器件中，层间电介质可以包括低电介质材料。低电介质材料是介电常数比氧化硅低的材料。当层间电介质用于半导体器件中时，可以提供具有增大的绝缘能力的半导体器件的高集成度和高速度。
然而，与其他电介质材料相比，由于低电介质材料的多孔膜质量，低电介质材料的弹性模量和硬度相对较低，因此低电介质材料可能易受应力的损坏。
由于这些特性，可以限制在包括凸块结构的半导体封装中使用低电介质材料。特别地，包括凸块结构的材料的高弹性模量可能将应力扩散到位于凸块结构下方的层间电介质，因此可能导致诸如层间电介质的开裂和/或剥离之类的缺陷。
在制造一些半导体芯片时，可以在半导体器件上方形成再分布层，以使凸块结构与层间电介质分离。然而，与其他存储器器件相比，高带宽存储器器件可能会遇到更多的连接结构用于信号传输的情况。因此，再分布层的形成可能伴随着电路设计和半导体制造工艺上的困难。
因此，根据本发明构思的示例性实施例的半导体芯片10可以在凸块结构BS下方形成缓冲焊盘220并且减轻在凸块结构BS中产生的应力，并且因此可以减少包括低电介质材料的层间电介质130的诸如开裂和/或剥离之类的缺陷。
最终，可以增加半导体芯片10和包括半导体芯片10的半导体封装1(参见图1)的电特性和可靠性。
图3至图11是示出了根据本发明构思的示例性实施例的制造半导体芯片10的方法的截面图。
参照图3，半导体器件100包括电极焊盘210，该电极焊盘210被配置为延伸半导体衬底110上方的个体单元元件150的集成电路功能结构。
半导体衬底110可以包括半导体晶片衬底，在该半导体晶片衬底上以矩阵形式布置的多个半导体器件100通过划道(scribe lane)彼此分离。
半导体衬底110可以包括例如硅。备选地，半导体衬底110可以包括诸如锗之类的半导体元素或者诸如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)和/或磷化铟(InP)之类的化合物半导体。备选地，半导体衬底110可以具有绝缘体上硅(SOI)结构。例如，半导体衬底110可以包括掩埋氧化物层(BOX)。半导体衬底110可以包括导电区，例如掺杂有杂质的阱或掺杂有杂质的结构。此外，半导体衬底110可以具有各种器件隔离结构，例如浅沟槽隔离(STI)结构。
用于实现半导体器件100的集成电路功能的包括个体单元元件150的电路部分可以通过半导体制造工艺形成在半导体衬底110上。例如，诸如晶体管、电阻器和电容器之类的个体单元元件150、导电通孔120、导电布线140、诸如上通孔160之类的布线层、以及布置在它们之间的层间电介质130可以形成在半导体衬底110上。
根据本发明构思的一些示例性实施例，层间电介质130可以包括具有比氧化硅低的介电常数的低k材料层。例如，层间电介质130的电介质材料可以是磷硅酸盐玻璃(PSG)、未掺杂的硅酸盐玻璃(USG)、原硅酸四乙酯(TEOS)、等离子体增强的TEOS(PE-TEOS)、高密度等离子体化学气相沉积(HDP-CVD)氧化物、BEOL中使用的电介质材料、超低电介质材料等。
根据本发明构思的一些示例性实施例，层间电介质130可以具有其中顺序地堆叠了第一层间电介质、第二层间电介质、第三层间电介质和第四层间电介质的结构。然而，在本发明中，层间电介质130中的层间电介质的数量不限于此。
层间电介质130可以布置成至少部分地填充布线层的外围，诸如包括导电材料的导电通孔120和导电布线140。另外，层间电介质130可以布置成至少部分地填充电连接到电极焊盘210并且与电极焊盘210直接接触的上通孔160的外围。
电极焊盘210可以电连接到半导体器件100的电路部分，以执行将半导体器件100电连接到外部电子设备的功能。电极焊盘210可以通过半导体器件100的上通孔160电连接到半导体器件100的下部的导电通孔120和导电布线140。
多个电极焊盘210可以形成在半导体器件100上方，作为用于向/从半导体器件100输入/输出电信号的部分，并且可以包括铝(Al)、钨(W)、铜(Cu)、镍(Ni)或其组合。电极焊盘210可以在半导体器件100上方将金属(例如铝(Al))形成至预定厚度，然后可以通过执行光刻工艺和蚀刻工艺通过图案化来制造期望形状的电极焊盘210。
参照图4，具有第一开口212H的第一保护层212可以形成在电极焊盘210和半导体器件100中的每一个的上方。
在电极焊盘210和半导体器件100两者上方形成保护层之后，通过光刻工艺和蚀刻工艺来图案化保护层，以形成包括暴露出电极焊盘210的中心的第一开口212H的第一保护层212。
第一保护层212可以包括暴露出电极焊盘210的中心的第一开口212H。例如，第一保护层212可以部分地暴露电极焊盘210，该第一保护层212是半导体器件100的电路部分的最终保护层。电极焊盘210可以通过上通孔160电连接到半导体器件100的电路部分，并且可以通过电极焊盘210的被第一开口212H暴露的部分电连接到外部电子设备。第一保护层212的第一开口212H在第一方向X上的宽度212W可以基本上等于普通电极焊盘的暴露程度。
第一保护层212可以布置在半导体器件100的上部中除了形成电极焊盘210的区域之外的剩余部分上，并且半导体器件100可以在除电极焊盘210之外的区域中绝缘。另外，第一保护层212可以保护半导体器件100的上表面免受外部杂质的污染和物理冲击等。根据本发明构思的一些示例性实施例，第一保护层212可包括多个材料层。
第一保护层212的材料可包括例如氧化硅、氮化硅、聚酰亚胺、苯并环丁烯、聚苯并恶唑、双马来酰亚胺三嗪(BT)、酚醛树脂、环氧树脂和/或其等同物。
参照图5，备用缓冲焊盘220P形成为至少部分地围绕电极焊盘210和第一保护层212中的每一个，并且备用缓冲焊盘220P通过第一开口212H(参见图4)电连接到电极焊盘210。另外，在备用缓冲焊盘220P上方形成第一掩模图案M1。
在通过化学气相沉积工艺或物理气相沉积工艺在电极焊盘210和第一保护层212上方将备用缓冲焊盘220P形成至预定厚度之后，通过光刻工艺和显影工艺在备用缓冲焊盘220P上方形成第一掩模图案M1。
备用缓冲焊盘220P可包括Al、Cu、Ni或其组合。根据本发明构思的一些示例性实施例，备用缓冲焊盘220P可与电极焊盘210包括相同的材料。
第一掩模图案M1可以在第一方向X上覆盖整个电极焊盘210，并且可以具有覆盖第一保护层212的一部分的宽度M1W。形成第一掩模图案M1的工艺包括在备用缓冲焊盘220P上方沉积光刻胶材料以及通过曝光来图案化光刻胶材料。经图案化的光刻胶形成第一掩模图案M1。形成将稍后描述的缓冲焊盘220(参见图6)的区域可以由第一掩模图案M1限定。
参照图6，在通过使用第一掩模图案M1(参见图5)作为蚀刻掩模蚀刻备用缓冲焊盘220P(参见图5)来形成缓冲焊盘220之后，第一掩模图案M1(参见图5)被移除。另外，在缓冲焊盘220和第一保护层212上方形成第二预保护层222P。第二预保护层222P可以被形成为完全覆盖缓冲焊盘220。
可以执行剥离工艺和/或灰化工艺以移除第一掩模图案M1(参见图5)。此后，在缓冲焊盘220和第一保护层212上方形成第二预保护层222P。
缓冲焊盘220可以形成在第一保护层212上方，并且可以通过第一开口212H直接接触并电连接到电极焊盘210(参见图4)。缓冲焊盘220可包括Al、W、Cu、Ni或其组合。根据本发明构思的一些示例性实施例，缓冲焊盘220可与电极焊盘210包括相同的材料。
缓冲焊盘220在第三方向Z上的厚度220T可以大于电极焊盘210在第三方向Z上的厚度210T。根据本发明构思的一些示例性实施例，缓冲焊盘220的厚度220T可以是电极焊盘210的厚度210T的约5倍至约10倍。
缓冲焊盘220在第一方向X上的宽度220W可以大于电极焊盘210在第一方向上的宽度210W。根据本发明构思的一些示例性实施例，缓冲焊盘220的宽度220W可以是电极焊盘210的宽度210W的约1.5倍至约3倍。
因此，当缓冲焊盘220厚于且大于电极焊盘210时，缓冲焊盘220可以减轻施加到电极焊盘210和半导体器件100的应力。随后将参照图13对其详情进行描述。
第二预保护层222P可以形成在除了形成缓冲焊盘220的区域之外的剩余部分中，因此半导体器件100可以在除缓冲焊盘220之外的区域中绝缘。另外，第二预保护层222P可以保护缓冲焊盘220免受外部杂质的污染和物理冲击等。根据本发明构思的一些示例性实施例，第二预保护层222P可包括多个材料层。
第二预保护层222P的材料可包括例如氧化硅、氮化硅、聚酰亚胺、苯并环丁烯、聚苯并恶唑、双马来酰亚胺三嗪(BT)、酚醛树脂、环氧树脂和/或其等同物。例如，第二预保护层222P可以与第一保护层212包括相同的材料。缓冲焊盘220可以布置在由包括第二预保护层222P和第一保护层212的保护层限定的内部空间中。
参照图7，在第二预保护层222P(参见图6)上方形成第二掩模图案M2，并且通过使用第二掩模图案M2作为蚀刻掩模对第二预保护层222P(参见图6)进行蚀刻来形成第二保护层222。
通过光刻工艺和显影工艺在第二预保护层222P(参见图6)上方形成第二掩模图案M2。第二掩模图案M2可以形成为暴露第二预保护层222P(参见图6)的一部分的图案。可以移除第二预保护层222P(参见图6)的暴露部分以暴露出缓冲焊盘220的上表面的中心部分。
缓冲焊盘220的被第二掩模图案M2暴露的中心部分对应于在后续工艺中直接接触预种子层230P(参见图8)的部分。第二保护层222在第一方向X上的第二开口222H可以形成为使得缓冲焊盘220的暴露的中心部分可以最小化。在本发明构思的一些示例性实施例中，第二开口222H的宽度222W可以基本上等于第一开口212H的宽度212W。在本发明构思的示例性实施例中，第二开口222H的宽度222W可以小于第一开口212H的宽度212W。
当缓冲焊盘220的暴露的中心部分最小化时，可以进一步保护缓冲焊盘220的上表面免受在蚀刻第二预保护层222P的过程中产生的氟(F)气体的影响。
参照图8，在移除第二掩模图案M2(参见图7)之后，在缓冲焊盘220和第二保护层222上方形成预种子层230P。
可以执行剥离工艺和/或灰化工艺以移除第二掩模图案M2(参见图7)。
通过执行化学气相沉积工艺或物理气相沉积工艺，预种子层230P可以形成在缓冲焊盘220的上表面和第二保护层222的整个表面上，并且其在第三方向Z上的厚度的范围从约
Figure BDA0002030846750000111
到约0.5μm。预种子层230P可以包括铜(Cu)、镍(Ni)、钛(Ti)、钨(W)和锡(Sn)的金属或合金、或其合金，并且可以具有单层结构或多层结构。
预种子层230P用作用于形成凸块结构BS(参见图2)的种子。例如，当通过电镀方法形成凸块结构BS时，预种子层230P可以提供其中电流可以流动的路径，使得凸块结构BS可以形成在预种子层230P上方。根据本发明构思的示例性实施例，凸块结构BS可以通过无电镀覆方法形成。
预种子层230P可以共形地完全覆盖第二保护层222的第二开口222H(参见图6)。
缓冲焊盘220的被第二保护层222暴露的中心部分对应于直接接触预种子层230P的部分。
参考图9，在预种子层230P上方形成第三掩模图案M3。第三掩模图案M3可以形成为暴露预种子层230P的一部分的图案。
预种子层230P的暴露部分可以包括与缓冲焊盘220接触的部分。由于被第三掩模图案M3暴露的部分对应于在后续工艺中形成柱层240(参见图10)和预焊料层250P(参见图10)的部分，因此暴露部分可以形成为多个，以分别对应于多个缓冲焊盘220。被第三掩模图案M3暴露的部分可以称为球着陆部(land)。
参照图10，包括柱层240和预焊料层250P的双层可以形成在其上形成有第三掩模图案M3的预种子层230P上方。然而，本发明构思不限于此，备选地，可以形成单个预焊料层250P。
柱层240可以被形成为与预种子层230P的被第三掩模图案M3暴露的上表面直接接触。柱层240可以通过电镀形成。用于形成柱层240的电镀可以被称为初次电镀。
为了形成柱层240，可以将其上形成有第三掩模图案M3的半导体衬底110放置在镀液中以执行初次电镀。柱层240可以包括例如铜(Cu)、镍(Ni)或金(Au)或其合金，或者可以是包括铜(Cu)、镍(Ni)和金(Au)的双层结构。
柱层240可以形成为仅填充被第三掩模图案M3暴露的区域，但是并不完全填充被第三掩模图案M3暴露的区域。例如，柱层240在第三方向Z上的厚度可以小于第三掩模图案M3在第三方向Z上的厚度。
预焊料层250P可以形成在柱层240上方。预焊料层250P的上表面可以与第三掩模图案M3的上表面基本齐平，或者预焊料层250P的上表面可以突出到第三掩模图案M3的上表面之外。可以通过电镀形成预焊料层250P。用于形成预焊料层250P的电镀可以被称为二次电镀，以将其与用于形成柱层240的初次电镀区分开。
为了形成预焊料层250P，其上形成有柱层240的半导体衬底110可以放置在与初次电镀中使用的镀液不同的镀液中，并且可以执行二次电镀。预焊料层250P可以包括锡(Sn)和银(Ag)的合金，并且可以添加少量的铜(Cu)、钯(Pd)、铋(Bi)和/或锑(Sb)。
柱层240在第一方向X上的宽度240W可以大于电极焊盘210在第一方向X上的宽度210W，并且可以小于缓冲焊盘220在第一方向X上的宽度220W。另外，如上所述，缓冲焊盘220的宽度220W可以大于电极焊盘210的宽度210W。例如，可以设计相应的宽度，以使得缓冲焊盘220可以最有效地减轻通过柱层240传递的应力。
参照图11，在移除第三掩模图案M3(参见图10)之后，移除预种子层230P(参见图10)的一部分以形成种子层230。
可以执行剥离工艺和/或灰化工艺以移除第三掩模图案M3(参见图10)。
在移除第三掩模图案M3(参见图10)之后，可以通过将柱层240和预焊料层250P用作蚀刻掩模来对暴露在外部的预种子层230P(参见图10)进行湿法蚀刻。当通过使用湿法蚀刻(其是各向同性蚀刻)蚀刻预种子层230P(参见图10)时，可以在柱层240的下部中形成底部填充。
当预种子层230P(参见图10)的配置材料是铜(Cu)时，可以通过使用氨蚀刻移除暴露在外部的预种子层230P。例如，可以使用包括Cu(NH3)4Cl2、Cu(NH3)2Cl、NH3和NH4Cl的碱性蚀刻剂。在下文中，可以通过使用NH3和H2O来清洁作为蚀刻结果而获得的包括CuO的化学物质。
再次参考图2，根据本发明构思的示例性实施例，可以在预焊料层250P上执行回流工艺以形成半导体芯片10。
对半导体衬底110进行热处理以执行回流工艺。回流工艺可以在约220℃至约260℃的温度下进行。通过使用回流工艺熔化预焊料层250P，可以形成焊料层250。预焊料层250P在熔化后可能不会坍塌，并且可以通过表面张力在柱层240上方形成焊料层250，并且可以在焊料层250和柱层240之间的界面上形成金属间化合物。在第一方向X上从焊料层250的中心到侧部的长度可以大于在第一方向X上从柱层240的中心到侧部的长度。
凸块结构BS可以包括种子层230、柱层240和焊料层250。凸块结构BS不限于此，并且可以仅包括种子层230和焊料层250。
凸块结构BS的类型可以根据要制造的半导体封装而不同。凸块结构BS可以用作接触端子，并且可以是电连接到封装衬底300(参见图1)的触点。多个凸块结构BS可以存在于半导体芯片10中，但是为了便于说明仅示出了一个凸块结构BS。
图12是示出了根据本发明构思的实施例的制造包括半导体芯片10的半导体封装1的方法的截面图。
参考图12，首先，可以通过执行参照图3至图11描述的工艺来形成半导体芯片10。半导体芯片10可以包括多个连接结构200。
可以在凸块结构BS和/或内部连接焊盘320上方形成焊剂。焊剂可以在焊料层250的表面上形成小的厚度，以防止焊料层250的氧化或不希望的反应。在本发明构思的一些示例性实施例中，可以通过涂覆氯化物、氟化物、树脂等来形成焊剂。
在下文中，可以提供封装衬底300，在其上形成在基部310的表面上方的内部连接焊盘320和暴露出内部连接焊盘320的一部分的绝缘层330。
半导体芯片10可以通过倒装芯片接合方式安装在封装衬底300上方。半导体衬底110的下表面110B可以布置成面对封装衬底300，使得焊料层250可以接触内部连接焊盘320。在本发明构思的一些示例性实施例中，焊料层250粘附到内部连接焊盘320的工艺可以在高到足以允许使得焊料层250的一部分融化的温度下执行。
如上所述，在将半导体芯片10安装在封装衬底300上方的过程中，被施加到凸块结构BS的应力可以传递到凸块结构BS的下部。如上所述，缓冲焊盘220可以减轻应力。
再次参考图1，底部填充410可以至少部分地围绕半导体芯片10和封装衬底300之间的连接结构200的侧壁。在下文中，可以形成至少部分地围绕半导体芯片10的上表面和侧表面的模制构件420。
之后，形成封装衬底300的表面上方的外部连接焊盘340和安装到外部连接焊盘340的外部端子350。然而，可以在附接半导体芯片10的工艺之前执行形成外连接焊盘340和/或外部端子350的工艺。
图13是示出了根据本发明构思的示例性实施例的半导体封装中的缓冲垫的厚度和凸块结构下的应力的图。
参照图13，在其中未在电极焊盘上方形成缓冲焊盘的半导体芯片A(例如，控制组)中以及在其中在电极焊盘上方形成缓冲焊盘并且缓冲焊盘的厚度是电极焊盘的厚度的约5倍的半导体芯片B(例如，实验组)中，测量被施加到层间电介质(图12中上通孔160的周边部分)的应力。
此时，被施加到半导体芯片A的应力被归一化为100％并被表示成被施加到半导体B的应力的相对值。
作为测量的结果，在半导体B中被施加到邻近电极焊盘的层间电介质的应力被测量为处于与半导体A中被施加到邻近电极焊盘的层间电介质的应力的80.2％相对应的水平。
由于半导体芯片B的应力减轻水平足够显著，在该半导体芯片B中缓冲焊盘在电极焊盘上方形成的厚度约为电极焊盘的厚度的5倍，因此可以预期半导体B和包括半导体芯片B的半导体封装的应力减轻效果。
例如，可以增加根据本发明构思的示例性实施例的半导体芯片10和半导体封装1的电特性和可靠性。
图14是根据本发明构思的示例性实施例的半导体封装1000的结构的框图。
参考图14，半导体封装1000可以包括微处理器1010、存储器器件1020、接口1030、图形处理单元1040、功能块1050、以及将微处理器1010、存储器器件1020、接口1030、图形处理单元1040和功能块1050彼此连接的系统总线1060。半导体封装1000可以包括微处理器1010和图形处理单元1040两者，或者可以仅包括它们中的一个。
微处理器1010可以包括至少一个内核和L2高速缓存。例如，微处理器1010可以包括多个内核。其每个内核可以具有相同或不同的性能。另外，其每个内核可以同时被激活或者可以单独被激活。
存储器器件1020可以存储根据微处理器1010的控制在功能块1050中处理的结果。接口1030可以与外部设备交换信息和信号。接口1030可以执行图形功能。例如，图形处理单元1040可以处理视频编解码器或3D图形。功能块1050可以执行各种功能。例如，当半导体封装1000是在移动设备中使用的应用处理器时，一些功能块1050可以执行通信功能。根据本发明构思的示例性实施例，半导体封装1000可以包括上述半导体封装1。
尽管已经参考本发明构思的实施例具体示出和描述了本发明构思，但是应当理解，在不脱离本公开的精神和范围的情况下，可以在其中进行形式和细节上的各种改变。

Claims (20)

1.一种半导体芯片，包括：
半导体衬底；
电极焊盘，设置在所述半导体衬底上，所述电极焊盘包括低k材料层；
第一保护层，至少部分地围绕所述电极焊盘，所述第一保护层包括在其上部的第一开口；
缓冲焊盘，电连接到所述电极焊盘；
第二保护层，至少部分地围绕所述缓冲焊盘，所述第二保护层包括在其上部的第二开口；以及
柱层和焊料层，顺序地堆叠在所述缓冲焊盘上，
其中，所述缓冲焊盘的厚度大于所述电极焊盘的厚度，并且
其中，所述第一开口在平行于所述半导体衬底的上表面的第一方向上的宽度等于或大于所述第二开口在所述第一方向上的宽度。
2.根据权利要求1所述的半导体芯片，其中，所述电极焊盘在所述第一方向上的宽度小于所述缓冲焊盘在所述第一方向上的宽度。
3.根据权利要求1所述的半导体芯片，其中，所述柱层在所述第一方向上的宽度小于所述缓冲焊盘在所述第一方向上的宽度。
4.根据权利要求1所述的半导体芯片，其中，所述电极焊盘在所述第一方向上的宽度小于所述柱层在所述第一方向上的宽度。
5.根据权利要求1所述的半导体芯片，其中，所述电极焊盘和所述缓冲焊盘包括相同的材料。
6.根据权利要求1所述的半导体芯片，还包括：
层间电介质，设置在所述电极焊盘下方，所述层间电介质包括单元元件、布线层和所述低k材料层。
7.根据权利要求1所述的半导体芯片，其中，所述电极焊盘的中心、所述缓冲焊盘的中心、所述柱层的中心和所述焊料层的中心在垂直于所述半导体衬底的上表面的方向上对齐。
8.根据权利要求1所述的半导体芯片，其中，所述缓冲焊盘的厚度是所述电极焊盘的厚度的至少5倍。
9.根据权利要求1所述的半导体芯片，其中，所述缓冲焊盘形成在所述第一保护层上方并且至少部分地填充所述第一开口以及至少部分地围绕所述电极焊盘，其中所述第一保护层设置在所述缓冲焊盘和所述电极焊盘之间。
10.根据权利要求1所述的半导体芯片，还包括：
种子层，设置在所述柱层下方，
其中，所述种子层形成在所述第二保护层上方并且至少部分地填充所述第二开口，并且
其中，底切形成在所述种子层的侧表面上。
11.一种半导体芯片，包括：
半导体衬底，包括层间电介质和电极焊盘，所述层间电介质包括低k材料，所述电极焊盘布置在所述层间电介质上；
保护层，至少部分地覆盖所述电极焊盘的侧表面和上表面，所述保护层包括内部空间，所述内部空间具有位于所述内部空间的下部的第一开口和位于所述内部空间的上部的第二开口；
缓冲焊盘，设置在所述保护层的所述内部空间中，并通过所述第一开口电连接到所述电极焊盘；以及
凸块结构，不位于所述保护层的所述内部空间中，形成在所述保护层上方，并通过所述第二开口电连接到所述缓冲焊盘，
其中，所述第一开口在平行于所述半导体衬底的上表面的第一方向上的宽度等于或大于所述第二开口在所述第一方向上的宽度。
12.根据权利要求11所述的半导体芯片，其中，所述保护层包括绝缘材料，并且所述电极焊盘和所述缓冲焊盘包括相同的导电材料。
13.根据权利要求11所述的半导体芯片，其中，所述保护层的侧表面和所述缓冲焊盘的侧表面从所述凸块结构的侧表面突出。
14.根据权利要求11所述的半导体芯片，其中，所述半导体衬底还包括：导电通孔，被所述层间电介质围绕，其中，所述导电通孔的上表面与所述电极焊盘的下表面接触。
15.根据权利要求11所述的半导体芯片，其中，所述凸块结构包括：柱层和焊料层的层叠结构，所述电极焊盘和所述缓冲焊盘包括相同的材料，并且所述柱层的材料的弹性系数大于所述电极焊盘和所述缓冲焊盘的材料的弹性系数。
16.一种半导体封装，包括：
封装衬底，包括衬底焊盘；以及
半导体芯片，安装在所述封装衬底上方；
其中，所述半导体芯片包括：
电极焊盘，设置在半导体衬底上并且包括低k材料层；
第一保护层，包括位于所述第一保护层的上部的第一开口，并至少部分地围绕所述电极焊盘；
缓冲焊盘，电连接到所述电极焊盘；
第二保护层，包括位于所述第二保护层的上部的第二开口，并至少部分地围绕所述缓冲焊盘；以及
柱层和焊料层，顺序地堆叠在所述缓冲焊盘上，
其中，所述缓冲焊盘的厚度大于所述电极焊盘的厚度，
其中，所述第一开口在平行于所述半导体衬底的上表面的第一方向上的宽度等于或大于所述第二开口在所述第一方向上的宽度，以及
其中，所述焊料层电连接到所述衬底焊盘。
17.根据权利要求16所述的半导体封装，其中，所述电极焊盘在所述第一方向上的宽度小于所述柱层在所述第一方向上的宽度，并且所述柱层在所述第一方向上的宽度小于所述缓冲焊盘在所述第一方向上的宽度。
18.根据权利要求16所述的半导体封装，还包括：
底部填充，设置在所述半导体芯片和所述封装衬底之间的空间中，
其中，所述底部填充至少部分地围绕所述第二保护层、所述柱层和所述焊料层。
19.根据权利要求16所述的半导体封装，其中，所述柱层的材料的弹性系数大于所述缓冲焊盘的材料的弹性系数。
20.根据权利要求16所述的半导体封装，其中，所述半导体芯片包括存储器芯片，其中，所述存储器芯片是高带宽存储器器件，并且所述高带宽存储器器件不包括再分布层。
CN201910309072.7A 2018-07-03 2019-04-17 包括凸块结构的半导体芯片和包括半导体芯片的半导体封装 Pending CN110676227A (zh)

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