CN117352492A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN117352492A
CN117352492A CN202310808184.3A CN202310808184A CN117352492A CN 117352492 A CN117352492 A CN 117352492A CN 202310808184 A CN202310808184 A CN 202310808184A CN 117352492 A CN117352492 A CN 117352492A
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CN
China
Prior art keywords
dielectric layer
semiconductor chip
pad
electrode
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310808184.3A
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English (en)
Inventor
金柱贤
金一焕
徐善京
赵汊济
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN117352492A publication Critical patent/CN117352492A/zh
Pending legal-status Critical Current

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Abstract

一种半导体封装包括：第一半导体芯片，包括第一焊盘；第二半导体芯片，在第一半导体芯片下方，第二半导体芯片包括具有前表面和相对的后表面的衬底、在前表面上并与第一焊盘接触的第二焊盘、以及电连接到第二焊盘并包括从衬底的后表面突出的突出部的贯通电极；通孔结构，设置在第二半导体芯片周围并与第一焊盘接触；第一介电层，沿衬底的后表面和贯通电极的突出部的侧表面延伸；第二介电层，在第一介电层下方并在贯通电极的突出部之间以及通孔结构之间的空间中；以及凸块结构，在第二介电层下方并电连接到贯通电极和通孔结构。

Description

半导体封装
相关申请的交叉引用
本申请要求于2022年7月4日向韩国知识产权局提交的韩国专利申请No.10-2022-0081724的优先权和权益，其公开内容通过引用整体并入本文。
技术领域
本发明构思涉及一种半导体封装和制造该半导体封装的方法。
背景技术
安装在电子设备上的半导体器件需要小型化，以及具有高性能和高容量。为了实现这一点，正在开发一种用于使用贯通电极(例如，硅通孔)将沿竖直方向堆叠的半导体芯片互连的半导体封装。
发明内容
本发明构思的一个方面在于提供一种简化工艺并提高良品率的半导体封装和用于制造该半导体封装的方法。
根据本发明构思的一个方面，一种半导体封装包括：第一半导体芯片，包括第一焊盘；第二半导体芯片，在第一半导体芯片下方，第二半导体芯片包括具有彼此相对的前表面和后表面的衬底、在前表面上并与第一焊盘接触的第二焊盘、以及电连接到第二焊盘并包括从衬底的后表面突出的突出部的贯通电极；通孔结构，设置在第二半导体芯片周围并与第一焊盘接触；第一介电层，沿衬底的后表面和贯通电极的突出部的侧表面延伸；第二介电层，在第一介电层下方并在(例如，填充)贯通电极的突出部之间以及通孔结构之间的空间中；以及凸块结构，在第二介电层下方并电连接到贯通电极和通孔结构。
根据本发明构思的一个方面，一种半导体封装包括：第一半导体芯片，包括第一焊盘；第二半导体芯片，包括具有彼此相对的前表面和后表面的衬底、在前表面上并与第一焊盘接触的第二焊盘、以及电连接到第二焊盘并包括从衬底的后表面突出的突出部的贯通电极；第一介电层，包括围绕贯通电极的突出部的侧表面的第一部分、以及从第一部分的一端沿衬底的后表面延伸的第二部分；以及第二介电层，在第一介电层的第一部分和第二部分下方或覆盖第一介电层的第一部分和第二部分。
根据本发明构思的一个方面，一种半导体封装包括：第一半导体芯片，包括第一焊盘；第二半导体芯片，在第一半导体芯片下方，第二半导体芯片包括具有彼此相对的前表面和后表面的衬底、在前表面上并与第一焊盘电连接的第二焊盘、以及电连接到第二焊盘并包括从衬底的后表面突出的突出部的贯通电极；第一介电层，在第一半导体芯片的下表面、第二半导体芯片的侧表面和下表面、以及贯通电极的突出部的侧表面上，或覆盖第一半导体芯片的下表面、第二半导体芯片的侧表面和下表面、以及贯通电极的突出部的侧表面；第二介电层，在第一半导体芯片和第二半导体芯片中的每一个的至少一部分下方，或覆盖第一半导体芯片和第二半导体芯片中的每一个的至少一部分，以及在第一介电层下方，第二介电层包括与第一介电层的材料不同的材料；以及凸块结构，设置在第二介电层下方并电连接到贯通电极。
根据本发明构思的一个方面，一种制造半导体封装的方法包括：制备包括第一焊盘的半导体晶片；将第二半导体芯片附接到半导体晶片，第二半导体芯片包括初步衬底、在初步衬底的前表面上的第二焊盘、以及嵌入初步衬底中的多个初步贯通电极；蚀刻初步衬底以暴露多个初步贯通电极中的每一个的至少一部分；形成第一初步介电层，第一初步介电层在半导体晶片、第二半导体芯片和多个暴露的初步贯通电极上或覆盖半导体晶片、第二半导体芯片和多个暴露的初步贯通电极，第一初步介电层包括暴露第一焊盘中的至少一部分的第一开口；在第一初步介电层上形成初步种子层；在初步种子层上形成抗蚀剂层，抗蚀剂层具有与第一开口对齐或相对应的第二开口；在第二开口中形成初步镀覆层；去除抗蚀剂层并蚀刻初步种子层；形成第二初步介电层，第二初步介电层在第一初步介电层上或覆盖第一初步介电层；抛光第一初步介电层、初步镀覆层、第二初步介电层和多个初步贯通电极，其中，形成平坦表面，该平坦表面包括第一介电层、镀覆层、第二介电层和多个贯通电极；以及在该平坦表面上形成凸块结构。
附图说明
通过结合附图的以下详细描述，将更清楚地理解本发明构思的上述和其他方面、特征和优点，在附图中：
图1A是示出了根据本发明构思的示例实施例的半导体封装的截面图。
图1B是示出了沿图1A的线I-I’截取的截面的平面图。
图1C是示出了图1A的区域“A”的局部放大图。
图2是示出了根据本发明构思的示例实施例的半导体封装的截面图。
图3是示出了根据本发明构思的示例实施例的半导体封装的截面图。
图4是示出了根据本发明构思的示例实施例的半导体封装的截面图。
图5是示出了根据本发明构思的示例实施例的半导体封装的截面图。
图6A至图6H是根据工艺顺序示出了制造图1A中所示的半导体封装的方法的截面图。
具体实施方式
在下文中，将参考附图描述本发明构思的示例实施例。
图1A是示出了根据本发明构思的示例实施例的半导体封装10A的截面图，图1B是沿图1A的线I-I′截取的截面图，并且图1C是示出了图1A的区域“A”的局部放大图。
参考图1A至图1C，根据示例实施例的半导体封装10A可以包括第一半导体芯片100、第二半导体芯片200、第一介电层310和第二介电层330。根据示例实施例，半导体封装10A还可以包括通孔结构320和/或凸块结构412。
根据本发明构思，可以通过将第一半导体芯片100的有源表面和第二半导体芯片200的有源表面彼此接合来最小化第一半导体芯片100和第二半导体芯片200之间的信号传输路径。第一半导体芯片100和第二半导体芯片200可以是逻辑芯片，包括中央处理器(CPU)、图形处理器(GPU)、现场可编程门阵列(FPGA)、数字信号处理器(DSP)、加密处理器、微处理器、微控制器、模数转换器等；或者可以是存储器芯片，包括易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM和闪存)等。例如，第一半导体芯片100可以包括逻辑电路如专用集成电路(ASIC)，并且第二半导体芯片200可以包括向第一半导体芯片100提供高速缓存信息的高速缓存存储器。第二半导体芯片200的尺寸可以小于第一半导体芯片100的尺寸。例如，第二半导体芯片200的平面面积在尺寸上可以基本上等于或小于第一半导体芯片100的平面面积。
此外，第一半导体芯片100和第二半导体芯片200可以直接接合并耦接，而无需单独的连接构件(例如，焊料凸块、铜柱等)。该结构可以被称为混合接合或直接接合等，包括金属接合(通过彼此接合的焊盘)和电介质接合(通过彼此接合的绝缘层)。
此外，通过使用包括绝缘树脂的第二介电层330来密封第一半导体芯片100和第二半导体芯片200，可以降低平坦化工艺的难度水平并且可以提高良品率。另外，通过使用由与第二介电层330的材料不同的材料形成的第一介电层310来围绕贯通电极240，可以在平坦化工艺期间保护并支撑贯通电极240。“平坦化工艺”可以包括用于形成平坦表面的一系列工艺，例如研磨工艺、抛光工艺等，该平坦表面包括贯通电极240的最下表面、通孔结构320的最下表面、第一介电层310的最下表面和第二介电层330的最下表面。在这种情况下，贯通电极240的最下表面、通孔结构320的最下表面、第一介电层310的最下表面和第二介电层330的最下表面可以基本上在相同平面(例如，图1C中的“PS”)上。
在下文中，将详细描述根据示例实施例的半导体封装10A的部件。
第一半导体芯片100可以包括第一衬底110、第一电路层120、第一绝缘层131和第一焊盘132。例如，第一半导体芯片100可以具有由第一绝缘层131和第一焊盘132提供的平坦下表面。
第一衬底110可以是半导体晶片，包括半导体元素如硅和锗，或化合物半导体如碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)和磷化铟(InP)。第一衬底110可以具有有源表面(例如，面对第一电路层120的表面)和与之相对的无源表面，该有源表面具有掺杂有杂质的有源区。
第一电路层120设置在第一衬底110的下表面上，并且可以包括层间绝缘层121和互连结构125。层间绝缘层121可以包括可流动氧化物(FOX)、东燃(tonen)硅氮烷(TOSZ)、未掺杂硅玻璃(USG)、硼硅玻璃(BSG)、磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、等离子体增强正硅酸四乙酯(PETEOS)、氟硅玻璃(FSG)、高密度等离子体(HDP)氧化物、等离子增强氧化物(PEOX)、可流动CVD(FCVD)氧化物或其组合。围绕互连结构125的层间绝缘层121的至少一部分可以被配置为低κ层。层间绝缘层121可以使用化学气相沉积(CVD)工艺、可流动CVD工艺或旋涂工艺形成。
互连结构125可以由包括互连图案和过孔的多层结构形成，互连图案和过孔包括例如铝(Al)、金(Au)、钴(Co)、铜(Cu)、镍(Ni)、铅(Pb)、钽(Ta)、碲(Te)、钛(Ti)、钨(W)或其组合。可以在互连图案和/或过孔与层间绝缘层121之间设置包括钛(Ti)、氮化钛(TiN)、钽(Ta)或氮化钽(TaN)的阻挡膜。构成集成电路的单独器件115可以设置在第一衬底110的下表面(或有源表面)上。在这种情况下，互连结构125可以通过互连部分或互连构件113(例如，接触插塞)电连接到单独器件115。单独器件115可以包括FET如平面FET、FinFET等，存储器件如闪存、DRAM、SRAM、EEPROM、PRAM、MRAM、FeRAM、RRAM等，逻辑器件如“与”、“或”、“非”等，以及各种有源和/或无源部件如系统LSI、CIS、MEMS等。
第一绝缘层131可以设置在第一电路层120下方以围绕第一焊盘132。第一绝缘层131可以包括能够与第二半导体芯片200的第二绝缘层231接合并耦接的材料例如氧化硅(SiO)、氮化硅(SiN)和碳氮化硅(SiCN)中的至少一种。即，第一绝缘层131的至少一部分可以接合到第二绝缘层231以形成第一半导体芯片100和第二半导体芯片200之间的接合表面。
第一焊盘132可以是与第一电路层120的互连结构125电连接的连接端子。第一焊盘132中的至少一部分可以是与互连结构125绝缘的虚设焊盘。第一焊盘132可以包括设置在第一半导体芯片100的下表面上的第一组的第一焊盘132a和第二组的第一焊盘132b。第一组的第一焊盘132a可以连接到第二半导体芯片200的第二焊盘232。第二组的第一焊盘132b可以连接到通孔结构320。第一组的第一焊盘132a可以设置为在与第一半导体芯片100的下表面垂直的方向(Z轴方向)上与第二半导体芯片200重叠或对齐。第一焊盘132可以包括铜(Cu)、镍(Ni)、钛(Ti)、铝(Al)、金(Au)和银(Ag)中的任一种或其合金。第一焊盘132可以与第一绝缘层131一起形成第一半导体芯片100和第二半导体芯片200之间的接合表面。可以在第一绝缘层131和第一焊盘132之间设置包括钛(Ti)、氮化钛(TiN)、钽(Ta)和氮化钽(TaN)中的至少一种的阻挡层。
第二半导体芯片200可以设置在第一半导体芯片100下方，并且可以包括具有彼此相对的前表面S1和后表面S2的第二衬底210、第二电路层220、第二绝缘层231、第二焊盘232和贯通电极240。第二半导体芯片200可以具有由第二绝缘层231和第二焊盘232提供的、与第一半导体芯片100的下表面接触的平坦上表面。根据示例实施例，第二半导体芯片200可以设置的层数小于附图中所示的层数。例如，第二半导体芯片200可以设置为在第一半导体芯片100下方水平设置的两个或更多个半导体芯片。第二半导体芯片200可以设置为在第一半导体芯片100下方在竖直方向(Z轴方向)上堆叠的多个半导体芯片。
第二半导体芯片200可以具有与第一半导体芯片100的结构基本相同或相似的结构，相同或相似的部件可以由相同或相似的附图标记表示，并且为了简洁起见，在下文中可以省略对相同部件的重复描述。第二电路层220设置在第二衬底210的前表面S1上，并且可以包括层间绝缘层221和互连结构225。构成集成电路的单独器件215可以设置在第二衬底210的前表面(或有源表面)上。在这种情况下，互连结构225可以电连接到单独器件215。例如，由于第二衬底210和第二电路层220与如上所述的第一衬底110和第一电路层120具有相同或相似的特性，因此彼此相对应的部件由相似的附图标记来表示，并且可以省略重复描述。
第二绝缘层231可以设置在第二电路层220上并形成为围绕第二焊盘232。第二绝缘层231可以包括能够与第一绝缘层131接合并耦接的材料，例如氧化硅(SiO)、氮化硅(SiN)和碳氮化硅(SiCN)中的至少一种。
第二焊盘232可以设置在第二衬底210的前表面S1上，并且可以是与第二电路层220的互连结构225电连接的连接端子。第二焊盘232可以与第二绝缘层231一起形成第一半导体芯片100和第二半导体芯片200之间的接合表面。第二焊盘232可以包括铜(Cu)、镍(Ni)、钛(Ti)、铝(A1)、金(Au)和银(Ag)中的任一种或其合金。例如，第二焊盘232可以接合并耦接到第一焊盘132。
贯通电极240可以电连接到第二电路层220的互连结构225和第二焊盘232。贯通电极240可以贯穿第二衬底210，并突出到或突出穿过第二衬底210的后表面S2。例如，贯通电极240可以具有从第二衬底210的后表面S2突出的突出部240P。贯通电极240可以通过突出部240P连接到凸块结构412。
贯通电极240可以包括过孔插塞和围绕过孔插塞的侧表面的侧阻挡膜。过孔插塞可以包括例如钨(W)、钛(Ti)、铝(Al)或铜(Cu)，并且可以通过镀覆工艺、PVD工艺或CVD工艺来形成。侧阻挡膜可以包括钛(Ti)、氮化钛(TiN)、钽(Ta)或氮化钽(TaN)，并且可以通过镀覆工艺、PVD工艺或CVD工艺来形成。可以在贯通电极240和第二衬底210之间形成包括绝缘材料如氧化硅、氮化硅、氮氧化硅等(例如，高纵横比工艺(HARP)氧化物)的侧绝缘膜241。
第一介电层310可以形成为覆盖第一半导体芯片100和第二半导体芯片200的表面。例如，第一介电层310可以覆盖第一半导体芯片100的下表面、第二半导体芯片200的侧表面和下表面、以及贯通电极240的突出部240P的侧表面。第一介电层310可以包括具有比构成第二介电层330的绝缘树脂高的平坦度和耐加工性的材料，例如，氧化硅(SiO)、氮化硅(SiN)和碳氮化硅(SiCN)中的至少一种。
第一介电层310可以沿第二衬底210的后表面S2和突出部240P的侧表面延伸，以在平坦化工艺中保护并支撑贯通电极240。例如，第一介电层310可以包括围绕突出部240P的侧表面的第一部分310a、以及从第一部分310a的一端延伸以覆盖第二衬底210的后表面S2的第二部分310b。第一部分310a可以沿突出部240P的侧表面(例如，在垂直于后表面S2的第一方向(Z方向)上)延伸，并且第二部分310b可以从第一部分310a的一端沿第二衬底210的后表面S2(例如，在平行于后表面S2的第二方向(X或Y方向)上)延伸。
第一介电层310的第一部分310a可以与贯通电极240的突出部240P一起形成从第二介电层330暴露的电极结构ELS。第一介电层310可以增加突出部240P的纵横比以确保平坦化工艺中突出部240P的稳定性。因此，电极结构ELS在第二方向(X或Y方向)上的宽度W1可以等于或大于突出部240P的高度h。例如，突出部240P的高度h可以在约1μm至约5μm的范围内，并且电极结构ELS的宽度W1可以在约4vm至约13μm的范围内。第一介电层310的厚度可以在约1μm至约3μm的范围内，但不限于此，并且可以根据突出部240P的高度h和宽度W3而不同地改变。
通孔结构320可以设置在第二半导体芯片200周围，并且可以与第一焊盘132接触。通孔结构320可以电连接到第一电路层120的互连结构125。根据示例实施例，通孔结构320中的至少一部分可以是与互连结构125或单独器件115电绝缘的虚设过孔。通孔结构320可以设置在第一介电层310的暴露第一焊盘132中至少一部分的开口(图6C的“OP1”)中。每一个通孔结构320可以包括沿开口OP1的内壁延伸的种子层321和从种子层321向下延伸的镀覆层322。种子层321可以包括铜(Cu)、钛(Ti)、铜(Cu)合金或钛(Ti)合金，并且镀覆层322可以包括铜(Cu)或铜(Cu)合金。贯通电极240可以具有比通孔结构320的宽度W2窄的宽度W3。例如，贯通电极240的宽度W3可以在约1μm至约10μm的范围内，并且通孔结构320的宽度W2可以在约4vm至约40vm的范围内。
第二介电层330可以设置在第一介电层310下方，并覆盖或围绕第一半导体芯片100和第二半导体芯片200中的每一个的至少一部分。第二介电层330可以填充贯通电极240的突出部240P之间的空间以及通孔结构320之间的空间。例如，第二介电层330可以与第一介电层310的第一部分310a和第二部分310b以及通孔结构320(或镀覆层322)的侧表面接触。为了简化工艺，第二介电层330可以包括与第一介电层310的材料不同的材料。第二介电层330可以包括绝缘树脂，例如，热固性树脂如环氧树脂，热塑性树脂如聚酰亚胺，或者浸渍有无机填料或/和玻璃纤维(玻璃纤维、玻璃布、玻璃织物)的材料(例如，预浸料、味之素积层膜(ABF)、FR-4、双马来酰亚胺三嗪(BT)、环氧模塑料(EMC)等)。
凸块结构412可设置在第二介电层330下方，并且可以电连接到贯通电极240和通孔结构320。半导体封装10A可以通过凸块结构412连接到外部装置如模块衬底、系统板等。作为示例，凸块结构412可以包括柱状部分412P和焊料部分412S。柱状部分412P可以包括铜(Cu)或铜(Cu)合金，并且焊料部分412S可以包括低熔点金属，例如锡(Sn)或包括锡(Sn)的合金(Sn-Ag-Cu)。根据示例实施例，凸块结构412可以仅包括柱状部分412P或仅包括焊料部分412S。可以在第二介电层330下方形成围绕凸块结构412的保护层411。保护层411可以保护凸块结构412免受外部物理/化学损坏。保护层411可以使用预浸料、ABF、FR-4、BT、可光成像电介质(PID)、光阻焊剂等来形成。根据示例实施例，保护层411可以形成为覆盖柱状部分412P的下表面或侧表面，或者可以被省略。
图2是示出了根据本发明构思的示例实施例的半导体封装10B的截面图。
参考图2，除了不包括图1A的通孔结构320之外，根据示例实施例的半导体封装10B可以具有与参考图1A至图1C描述的特性相同或相似的特性。本示例实施例的半导体封装10B可以具有其中第一半导体芯片100和第二半导体芯片200彼此竖直重叠或对齐的重叠区域OR、以及位于重叠区域OR之外的外围区域PR。例如，第二半导体芯片200在水平方向(X或Y方向)上的宽度可以等于或窄于第一半导体芯片100的宽度。第一半导体芯片100的第一焊盘132可以设置在重叠区域OR中，并且可以不设置在外围区域PR中。然而，根据示例实施例，与第一电路层120电绝缘的虚设焊盘可以设置在外围区域PR中。如上所述，取决于第一半导体芯片100和第二半导体芯片200的尺寸和类型，可以省略图1A的通孔结构320。
图3是示出了根据本发明构思的示例实施例的半导体封装10C的截面图。
参考图3，除了还包括对贯通电极240和/或通孔结构320进行重分布的重分布结构510之外，根据示例实施例的半导体封装10C可以具有与参考图1A至图2描述的特性相同或相似的特性。重分布结构510设置在第二介电层330下方，并且可以包括绝缘材料层511、重分布图案层512和重分布过孔513。
根据本示例实施例的重分布图案层512可以直接设置在第二介电层330的表面上。例如，重分布图案层512可以包括：上图案层，与第二介电层330和第一介电层310直接接触并被掩埋在绝缘材料层511中；以及下图案层，设置在绝缘材料层511下方。在这种情况下，重分布过孔513可以贯穿绝缘材料层511以连接下图案层和上图案层。如上所述，通过引入重分布结构510，可以设计凸块结构412的布局。
绝缘材料层511可以使用介电材料如氧化硅、氮化硅或氮氧化硅，或者光敏树脂如可光成像电介质(PID)形成。根据重分布图案层512的层数，绝缘材料层511可以形成为多层。取决于工艺，多个绝缘材料层511中的至少一部分之间的边界可以不清晰。
重分布图案层512可以电连接到第一半导体芯片100和第二半导体芯片200，并且可以包括金属材料例如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金。重分布图案层512可以包括例如接地图案、电源图案和信号图案。信号图案可以将从第一半导体芯片100和第二半导体芯片200发送的数据信号发送到外部，或者将从外部发送的数据信号发送到第一半导体芯片100和第二半导体芯片200。根据示例实施例，电源图案和/或接地图案中的至少一部分可以通过通孔结构320连接到第一半导体芯片100。重分布图案层512可以形成为比附图中所示的层数(两层)多或少的层数。例如，重分布图案层512可以在凸块结构412和第二介电层330之间沿水平方向(例如，沿X和Y方向)延伸，使得重分布图案层512可以设置为用于对贯通电极240和通孔结构320进行重分布的三个或更多个图案层。
重分布过孔513可以贯穿绝缘材料层511以连接到重分布图案层512。重分布过孔513可以具有其中金属材料填充在过孔内部的填充过孔、或其中金属材料沿过孔内壁而形成的共形过孔的形式。重分布过孔513可以与重分布图案层512集成，但本发明构思的示例实施例不限于此。重分布过孔513可以对应于重分布图案层512，从而重分布过孔513可以形成为比附图中所示的层数(一层)多的层数。
在附图中，凸块结构412可以仅包括焊料部分412S，但根据示例实施例，凸块结构412可以包括柱状部分(图1A中的“412P”)，并且可以形成围绕凸块结构412的保护层(图1A中的“411”)。
图4是示出了根据本发明构思的示例实施例的半导体封装10D的截面图。
参考图4，除了重分布图案层512与第一介电层310和第二介电层330间隔开之外，根据示例实施例的半导体封装10D可以具有与参考图3描述的特性相同或相似的特性。本示例实施例的重分布结构510可以包括：绝缘材料层511，直接设置在第一介电层310和第二介电层330的下表面上；重分布图案层512，设置在绝缘材料层511下方；以及重分布过孔513，贯穿绝缘材料层511以将重分布图案层512连接到贯通电极240和/或通孔结构320。如上所述，通过在绝缘材料层511上形成重分布图案层512，可以确保重分布图案层512的粘合性，并且可以实现具有精细间距的重分布图案层512。在附图中，凸块结构412可以包括柱状部分412P和焊料部分412S两者，但根据示例实施例，可以省略其中任何一个。
图5是示出了根据本发明构思的示例实施例的半导体封装10E的截面图。
参考图5，根据示例实施例的半导体封装10E可以包括接合结构BS、互连衬底600和散热结构630。接合结构BS可以包括第一半导体芯片100、第二半导体芯片200、第一介电层310、第二介电层330等，并且可以具有与参考图1A至图4描述的特性相同或相似的特性。
互连衬底600是其上安装有接合结构BS的支撑衬底，并且可以是用于半导体封装的衬底如印刷电路板(PCB)、陶瓷衬底、带式互连衬底等。互连衬底600可以包括主体、设置在主体的下表面上的下焊盘612、设置在主体的上表面上的上焊盘611、以及电连接下焊盘612和上焊盘611的互连电路613。取决于衬底的类型，互连衬底600的主体可以包括不同的材料。例如，当互连衬底600是印刷电路板时，互连衬底可以具有其中互连层被附加地层压在主体覆铜层压板或覆铜层压板的一侧或两侧上的形式。上焊盘611、下焊盘612和互连电路613可以形成连接互连衬底600的下表面和上表面的电路径。可以在互连衬底600的下表面上设置与下焊盘612连接的外部连接凸块620。外部连接凸块620可以包括锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)和/或其合金。
散热结构630可以设置在互连衬底600的上表面上，并且可以形成为覆盖接合结构BS的上部。散热结构630可以通过粘合剂附接到互连衬底600。作为粘合剂，可以使用导热粘合带、导热脂、导热粘合剂等。散热结构630可以通过接合结构BS上的接合构件631附接到接合结构BS的上表面。散热结构630可以包括具有优异导热性的导电材料。例如，散热结构630可以包括：金属或金属合金，包括金(Au)、银(Ag)、铜(Cu)、铁(Fe)等；或导电材料，诸如石墨、石墨烯等。散热结构630可以具有与附图中所示的形状不同的形状。例如，散热结构630可以具有仅覆盖接合结构的上表面的形状。
图6A至图6H是根据工艺顺序示出了制造图1A中所示的半导体封装10A的方法的截面图。
参考图6A，可以制备用于第一半导体芯片100的半导体晶片100W。
半导体晶片100W可以包括由划线SL分离的多个第一半导体芯片100。半导体晶片100W可以处于其中用于第一半导体芯片100的第一电路层120和第一接合层130形成在第一衬底110上的状态。第一接合层130可以包括第一绝缘层131和第一焊盘132。半导体晶片100W可以设置在载体CR上，使得其上设置有第一焊盘132的第一有源表面AS1面朝上。
接下来，可以将第二半导体芯片200p附接到半导体晶片100W。
第二半导体芯片200p可以包括在通过背磨工艺调整其厚度之前的初步衬底210p、设置在初步衬底210p的前表面上的第二电路层220和第二接合层230、以及掩埋在初步衬底210p中的多个初步贯通电极240p。第二半导体芯片200p可以设置在半导体晶片100W上，使得其上设置有第二焊盘232的第二有源表面AS2面朝下。第二半导体芯片200p可以设置为使得第二有源表面AS2与第一有源表面AS1接触。
此后，第一半导体芯片100和第二半导体芯片200p可以通过执行热压工艺来耦接。热压工艺可以在从约100℃至约300℃范围内的热氛围中执行。然而，热氛围的温度不限于上述范围并且可以不同地改变。
参考图6B，可以蚀刻初步衬底210p以暴露多个初步贯通电极240p中的每一个的至少一部分。
可以通过对初步衬底210p应用抛光工艺来形成具有期望厚度的衬底210。抛光工艺可以通过化学机械抛光(CMP)工艺、回蚀工艺或其组合来执行。例如，可以通过执行抛光工艺将初步衬底210p减小到预定厚度，并且可以通过在适当条件下应用回蚀条件来充分暴露多个初步贯通电极240p。
参考图6C，可以形成覆盖半导体晶片100W、第二半导体芯片200p和多个暴露的初步贯通电极240p的第一初步介电层310p。
第一初步介电层310p可以具有暴露第一焊盘132中的至少一部分的第一开口OP1。第一初步介电层310p可以沿多个暴露的初步贯通电极240p的表面共形地延伸。第一初步介电层310p可以包括例如氧化硅(SiO)，并且可以使用PVD或CVD工艺来形成。
参考图6D，可以在第一初步介电层310p上形成初步种子层321p。
初步种子层321p可以沿第一初步介电层310p的表面共形地延伸。初步种子层321p可以包括例如钛(Ti)、铜(Cu)等，并且可以使用镀覆工艺、PVD工艺或CVD工艺来形成。初步种子层321p的厚度可以在约0.1μm至约0.3μm的范围内，但其示例实施例不受具体限制。
参考图6E，可以在初步种子层321p上形成具有第二开口OP2的抗蚀剂层PR，并且可以在第二开口OP2中形成初步镀覆层322p。
第二开口OP2可以形成在对应于第一开口OP1的位置(例如，水平位置)处。第二开口OP2的宽度可以等于或大于第一开口OP1的宽度，但其示例实施例不限于此。抗蚀剂层PR可以通过在初步种子层321p上涂覆并固化光敏材料(例如，光刻胶)并执行光刻工艺来形成。初步镀覆层322p可以包括例如铜(Cu)，并且可以使用镀覆工艺来形成。
参考图6F，可以去除抗蚀剂层(图6E中的“PR”)，并且可以蚀刻初步种子层321p。例如，可以使用干法蚀刻工艺来去除初步种子层321p的从初步镀覆层322p暴露的部分，使得可以在初步镀覆层322p下方形成种子层321。
参考图6G，可以形成覆盖第一初步介电层310p的第二初步介电层330p。此后，通过对第二初步介电层330p应用抛光工艺，可以形成包括第二介电层330、镀覆层322、第一介电层310和多个贯通电极240的平坦表面PS。第二初步介电层330p可以通过涂覆并固化模塑材料(例如，EMC)来形成。第二初步介电层330p可以覆盖初步镀覆层322p和初步贯通电极240p，并且可以填充由第一初步介电层310p围绕的多个初步贯通电极240p之间的空间。第一介电层310(从其去除了第一初步介电层310p的一部分)、镀覆层322(从其去除了初步镀覆层322p的一部分)和贯通电极(从其去除了初步贯通电极240p的一部分)可以通过蚀刻工艺来形成。第一初步介电层310p可以在抛光工艺期间通过围绕从衬底210突出的初步贯通电极240p来支撑并保护初步贯通电极240p。
参考图6H，可以在通过抛光工艺形成的平坦表面上顺序地形成保护层411和凸块结构412。保护层411可以使用例如光敏性树脂如PID来形成。凸块结构412可以包括柱状部分和焊料部分。此后，可以通过沿划线SL执行切割工艺来形成图1A的半导体封装。
如上所述，根据本发明构思的示例实施例，通过引入围绕贯通电极的第一介电层和第二介电层，可以提供具有简化工艺并提高了良品率的半导体封装和制造该半导体封装的方法。
在本文中，下侧、下部、下表面等用于指代相对于附图的截面朝向扇出型半导体封装的安装表面的方向，而上侧、上部、上表面等用于指代与该方向相反的方向。然而，这些方向是为了便于说明而定义的，并且权利要求不具体受限于如上所述定义的方向。
虽然以上已经示出并描述了示例实施例，但本领域技术人员应清楚，在不脱离由所附权利要求限定的本发明构思的范围的情况下，可以进行修改和改变。

Claims (20)

1.一种半导体封装，包括：
第一半导体芯片，包括第一焊盘；
第二半导体芯片，在所述第一半导体芯片下方，所述第二半导体芯片包括具有彼此相对的前表面和后表面的衬底、在所述前表面上并与所述第一焊盘接触的第二焊盘、以及电连接到所述第二焊盘并包括从所述衬底的后表面突出的突出部的贯通电极；
通孔结构，设置在所述第二半导体芯片周围并与所述第一焊盘接触；
第一介电层，沿所述衬底的后表面和所述贯通电极的突出部的侧表面延伸；
第二介电层，在所述第一介电层下方并在所述贯通电极的突出部之间以及所述通孔结构之间的空间中；以及
凸块结构，在所述第二介电层下方并电连接到所述贯通电极和所述通孔结构。
2.根据权利要求1所述的半导体封装，其中，所述第一介电层具有沿所述贯通电极的突出部的侧表面在第一方向上延伸的第一部分、以及从所述第一部分沿所述衬底的后表面在第二方向上延伸的第二部分。
3.根据权利要求2所述的半导体封装，其中，所述第二介电层与所述第一介电层的第一部分和第二部分接触。
4.根据权利要求1所述的半导体封装，其中，所述第一介电层沿所述第一半导体芯片的下表面和所述第二半导体芯片的侧表面延伸，并且包括暴露所述第一焊盘中的至少一部分的开口。
5.根据权利要求4所述的半导体封装，其中，所述通孔结构中的每一个包括位于所述开口中的种子层以及从所述种子层向下延伸的镀覆层。
6.根据权利要求5所述的半导体封装，其中，所述镀覆层的侧表面与所述第二介电层接触。
7.根据权利要求1所述的半导体封装，其中，所述第一介电层包括氧化硅SiO、氮化硅SiN和碳氮化硅SiCN中的至少一种。
8.根据权利要求1所述的半导体封装，其中，所述第二介电层包括绝缘树脂。
9.根据权利要求1所述的半导体封装，其中，所述贯通电极在与所述衬底的后表面平行的方向上具有比所述通孔结构的宽度窄的宽度。
10.根据权利要求9所述的半导体封装，其中，所述贯通电极的宽度在约1μm至约10μm的范围内，以及
所述通孔结构的宽度在约4μm至约40μm的范围内。
11.根据权利要求1所述的半导体封装，其中，所述第一半导体芯片还包括围绕所述第一焊盘的侧表面的第一绝缘层，
其中，所述第二半导体芯片还包括第二绝缘层，所述第二绝缘层围绕所述第二焊盘的侧表面并与所述第一绝缘层接触。
12.根据权利要求11所述的半导体封装，其中，所述第一绝缘层和所述第二绝缘层各自包括氧化硅SiO、氮化硅SiN和碳氮化硅SiCN中的至少一种。
13.根据权利要求1所述的半导体封装，其中，所述贯通电极的最下表面、所述通孔结构的最下表面、所述第一介电层的最下表面和所述第二介电层的最下表面基本上共面。
14.一种半导体封装，包括：
第一半导体芯片，包括第一焊盘；
第二半导体芯片，包括具有彼此相对的前表面和后表面的衬底、在所述前表面上并与所述第一焊盘接触的第二焊盘、以及电连接到所述第二焊盘并包括从所述衬底的后表面突出的突出部的贯通电极；
第一介电层，包括围绕所述贯通电极的突出部的侧表面的第一部分、以及从所述第一部分的一端沿所述衬底的后表面延伸的第二部分；以及
第二介电层，覆盖所述第一介电层的第一部分和第二部分。
15.根据权利要求14所述的半导体封装，其中，所述第一介电层的第一部分与所述贯通电极的突出部形成延伸穿过所述第二介电层的电极结构，
其中，所述电极结构的宽度等于或大于所述突出部的高度。
16.根据权利要求14所述的半导体封装，其中，所述第一介电层的厚度在约1μm至约3μm的范围内，
其中，所述贯通电极的突出部的宽度在约1μm至约10μm的范围内。
17.根据权利要求14所述的半导体封装，其中，所述第一介电层的第一部分沿与所述衬底的后表面垂直的第一方向延伸，并且
所述第一介电层的第二部分沿与所述衬底的后表面平行的第二方向延伸。
18.一种半导体封装，包括：
第一半导体芯片，包括第一焊盘；
第二半导体芯片，在所述第一半导体芯片下方，所述第二半导体芯片包括具有彼此相对的前表面和后表面的衬底、在所述前表面上并与所述第一焊盘电连接的第二焊盘、以及电连接到所述第二焊盘并包括从所述衬底的后表面突出的突出部的贯通电极；
第一介电层，在所述第一半导体芯片的下表面、所述第二半导体芯片的侧表面和下表面、以及所述贯通电极的突出部的侧表面上；
第二介电层，在所述第一半导体芯片和所述第二半导体芯片中的每一个的至少一部分下方并且在所述第一介电层下方，所述第二介电层包括与所述第一介电层的材料不同的材料；以及
凸块结构，在所述第二介电层下方并电连接到所述贯通电极。
19.根据权利要求18所述的半导体封装，其中，所述第一介电层包括氧化硅SiO、氮化硅SiN和碳氮化硅SiCN中的至少一种。
20.根据权利要求18所述的半导体封装，其中，所述第二介电层包括预浸料、味之素积层膜ABF和环氧模塑料EMC中的至少一种。
CN202310808184.3A 2022-07-04 2023-07-03 半导体封装 Pending CN117352492A (zh)

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