TW202403982A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TW202403982A TW202403982A TW112118395A TW112118395A TW202403982A TW 202403982 A TW202403982 A TW 202403982A TW 112118395 A TW112118395 A TW 112118395A TW 112118395 A TW112118395 A TW 112118395A TW 202403982 A TW202403982 A TW 202403982A
- Authority
- TW
- Taiwan
- Prior art keywords
- chip
- redistribution
- pillar
- layer
- interconnect
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000005538 encapsulation Methods 0.000 claims description 35
- 230000007423 decrease Effects 0.000 claims description 4
- 239000008393 encapsulating agent Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 138
- 235000012431 wafers Nutrition 0.000 description 63
- 239000010949 copper Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 230000015654 memory Effects 0.000 description 17
- 229910052802 copper Inorganic materials 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 239000010931 gold Substances 0.000 description 14
- 229920005989 resin Polymers 0.000 description 14
- 239000011347 resin Substances 0.000 description 14
- 229910045601 alloy Inorganic materials 0.000 description 10
- 239000000956 alloy Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 8
- 230000017525 heat dissipation Effects 0.000 description 8
- 229910052709 silver Inorganic materials 0.000 description 8
- 239000004332 silver Substances 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000007769 metal material Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000000227 grinding Methods 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 229920006336 epoxy molding compound Polymers 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- -1 for example Substances 0.000 description 3
- 239000011256 inorganic filler Substances 0.000 description 3
- 229910003475 inorganic filler Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229920005992 thermoplastic resin Polymers 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5381—Crossover interconnections, e.g. bridge stepovers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
一種半導體封裝包括基板以及第一晶片結構及第二晶片結構,基板包括:第一重佈線構件,包括第一表面及第二表面且包括第一重佈線層;內連晶片,位於第二表面下方且包括電性連接至第一重佈線層的內連電路;通孔結構,圍繞內連晶片且電性連接至第一重佈線層;包封體,位於第二表面與內連晶片及通孔結構之間;第一柱,延伸穿過包封體以將第一重佈線層與內連電路電性連接;第二柱,延伸穿過包封體以將第一重佈線層與通孔結構電性連接;以及連接凸塊,位於內連晶片及通孔結構下方;第一晶片結構及第二晶片結構位於第一重佈線構件的第一表面上且電性連接至第一重佈線層。第一柱與第二柱具有不同的形狀。
Description
[相關申請案的交叉參考]
本申請案基於35 USC § 119(a)主張於2022年7月14日在韓國智慧財產局提出申請的韓國專利申請案第10-2022-0086802號的優先權,所述韓國專利申請案的揭露內容全部併入本案供參考。
本發明概念是有關於一種半導體封裝。
安裝於電子裝置上的半導體裝置需要小型化,並且需要具有高效能及高容量。為此,正在開發一種用於使用貫穿電極(through-electrode)(例如矽穿孔)對在垂直方向上堆疊的半導體晶片進行內連的半導體封裝。
實例性實施例提供一種製程得到簡化的半導體封裝。
根據實例性實施例,一種半導體封裝包括基板以及第一晶片結構及第二晶片結構,基板包括:第一重佈線構件,包括彼此相對的第一表面與第二表面且包括第一重佈線層;內連晶片,位於第二表面下方且包括電性連接至第一重佈線層的內連電路;通孔結構,圍繞內連晶片設置且電性連接至第一重佈線層;包封體,對第二表面與內連晶片及通孔結構之間的空間進行填充;第一柱,延伸穿過包封體以將第一重佈線層與內連電路電性連接;第二柱,延伸穿過包封體以將第一重佈線層與通孔結構電性連接;以及連接凸塊,位於內連晶片及通孔結構下方;第一晶片結構及第二晶片結構位於第一重佈線構件的第一表面上且電性連接至第一重佈線層。第一柱與第二柱具有不同的形狀。
根據實例性實施例,一種半導體封裝包括基板以及第一晶片結構及第二晶片結構,基板包括:第一重佈線構件,包括第一表面及第二相對表面且包括第一重佈線層;內連晶片,位於第二表面下方且包括電性連接至第一重佈線層的內連電路;通孔結構,圍繞內連晶片設置且電性連接至第一重佈線層;包封體,位於第一重佈線構件的第二表面與內連晶片及通孔結構之間;第一柱,穿過包封體以將第一重佈線層與內連電路電性連接;第二柱,穿過包封體以將第一重佈線層與通孔結構電性連接;以及連接凸塊,位於內連晶片及通孔結構下方;第一晶片結構及第二晶片結構位於第一重佈線構件的第一表面上且電性連接至第一重佈線層。第一柱與第二柱具有不同的高度。
根據實例性實施例,一種半導體封裝包括:第一重佈線構件,包括第一表面與相對的第二表面且包括第一重佈線層;內連晶片,位於第一重佈線構件的第二表面下方且包括電性連接至第一重佈線層的內連電路;通孔結構,圍繞內連晶片設置且電性連接至第一重佈線層;包封體,包括設置於第一重佈線構件的第二表面與內連晶片及通孔結構之間的第一部分、以及設置於內連晶片的側表面上的第二部分;第一柱,延伸穿過包封體的第一部分並將第一重佈線層與內連電路電性連接;第二柱,延伸穿過包封體的第一部分並將第一重佈線層與通孔結構電性連接,且包括寬度在自第一重佈線構件的第二表面朝向通孔結構的方向上減小的錐形形狀;第二重佈線構件,位於內連晶片及通孔結構下方且包括電性連接至通孔結構的第二重佈線層;連接凸塊,位於第二重佈線構件下方且電性連接至第二重佈線層;以及第一晶片結構及第二晶片結構,位於第一重佈線構件的第一表面上且電性連接至第一重佈線層。
在下文中,將參照附圖對實例性實施例進行闡述。
圖1A是示出根據實例性實施例的半導體封裝的平面圖,圖1B是沿著圖1A所示的線I-I’截取的剖視圖,且圖2是示出圖1B所示的區域「A」及區域「B」的局部放大圖。
參照圖1A及圖1B,根據實例性實施例的半導體封裝1a可包括基板20(或「中介基板」)及晶片結構30。根據實例性實施例,藉由在內連晶片220之間以及在重佈線構件210與通孔結構235之間引入柱結構PL1及PL2,半導體封裝1a的製造製程可得到簡化且良率可得到提高。
基板20可包括第一重佈線構件210、內連晶片220、連接構件230、包封體240以及連接凸塊250。在一些實施例中,基板20可更包括第二重佈線構件260。
第一重佈線構件210具有彼此相對的第一表面S1與第二表面S2,且可包括第一介電層211、第一重佈線層212以及第一重佈線通孔213。此外,重佈線構件210(或第一重佈線層212)可包括設置於第一表面S1上的接墊結構212P。
第一介電層211可包含熱固性樹脂(例如環氧樹脂)、熱塑性樹脂(例如聚醯亞胺)或者在該些樹脂中浸漬有無機填料的樹脂(例如,預浸體、味之素堆積膜(Ajinomoto build-up film,ABF)、FR-4、雙馬來醯亞胺三嗪(Bismaleimide Triazine,BT))或感光性樹脂(例如光可成像介電質(Photo Imageable Dielectric,PID)樹脂)。第一介電層211可由多個層形成且可清晰地區分出各層之間的邊界。然而,端視製程而定,各別層之間的邊界可能不清晰。
第一重佈線層212可將內連晶片220、通孔結構235及晶片結構30電性連接。第一重佈線層212可實質上重新分佈晶片結構30的接墊32。舉例而言,接墊32可藉由焊料凸塊34連接至接墊結構212P。第一重佈線層212可包含金屬材料,金屬材料包括例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。第一重佈線層212可根據設計包括接地(GrouND:GND)圖案、電源(PoWeR:PWR)圖案及訊號(S)圖案。訊號(S)圖案可提供除接地(GND)圖案、電源(PWR)圖案及類似圖案之外的各種訊號的傳輸路徑。
接墊結構212P可設置於第一表面S1上,且可將晶片結構30與第一重佈線層212電性連接。接墊結構212P可包括設置於第一介電層211上的接墊部分以及延伸至第一介電層211中以將接墊部分連接至第一重佈線層212的通孔部分。另外,接墊結構212P可包括設置於接墊部分上的表面層。表面層可包含鎳(Ni)、金(Au)或其合金。
接墊結構212P可包括第一接墊結構212P1及第二接墊結構212P2,第一接墊結構212P1經由第一重佈線層212電性連接至內連電路222,第二接墊結構212P2電性連接至通孔結構235。第一接墊結構212P1與第二接墊結構212P2可在同一製造製程中形成,且因此可具有實質上相同的大小。舉例而言,第一接墊結構212P1在平行於第一表面S1的方向(X方向)上的寬度w1可實質上等於第二接墊結構212P2的寬度w2。
各晶片結構30可藉由第一接墊結構212P1及內連電路222彼此電性連接,且可藉由第二接墊結構212P2及通孔結構235電性連接至連接凸塊250。因此,第一接墊結構212P1可以與用於晶片結構30的內連的接墊32的節距對應的精細節距進行佈置。舉例而言,彼此相鄰的第一接墊結構212P1之間的第一距離或間距d1可小於彼此相鄰的第二接墊結構212P2之間的第二距離或間距d2。第一距離d1可為約60微米或小於60微米(例如介於約10微米至約60微米、約20微米至約60微米、約20微米至約50微米、或約20微米至約40微米的範圍內),且第二距離d2可為約60微米或大於60微米(例如介於約60微米至約100微米、或約70微米至約100微米的範圍內)。
第一重佈線通孔213可將第一重佈線層212電性連接至第一柱PL1及第二柱PL2。第一重佈線通孔213可包含金屬材料,金屬材料包括例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。第一重佈線通孔213可為其中填充有金屬材料的填充通孔或者其中金屬材料沿著通孔孔的內壁形成的共形的通孔。
內連晶片220可設置於第一重佈線構件210的第二表面S2上,且可包括晶片主體221、內連電路222及內連接墊223。內連晶片220可具有其中晶片主體221的部分區可在垂直方向(Z方向)上與晶片結構30交疊或對準的大小或水平區域,以用於連接晶片結構30。
晶片主體221可基於陶瓷、玻璃、半導體或類似材料而形成。舉例而言,晶片主體221可基於主動晶圓形成,且可包含矽(Si)、鍺(Ge)、砷化鎵(GaAs)或類似元素。在晶片主體221的一個表面上可形成有鈍化層以保護晶片主體221免受外部物理損壞及化學損壞。鈍化層可由氧化膜或氮化膜形成,或者可由氧化膜及氮化膜構成的雙層形成。舉例而言,鈍化層可由氧化矽(SiO)膜、氮化矽(SiN)膜或其組合形成。
內連電路222可形成於在晶片主體221的一個表面上形成的層間絕緣層中。內連電路222可經由第一柱PL1及第一重佈線層212電性連接至第一接墊結構212P1,且可將晶片結構30彼此電性連接。內連電路222可具有較第一重佈線層212的節距更精細的節距。內連接墊223可設置於在晶片主體221的一個表面上形成的層間絕緣層上或所述層間絕緣層內部,且可與第一柱PL1接觸。
連接構件230可包括絕緣層231及通孔結構235。絕緣層231可環繞通孔結構235或位於通孔結構235的側表面上,且使多個通孔結構235彼此絕緣。連接構件230可具有穿透絕緣層231且容納或接納內連晶片220的貫通孔210H。貫通孔210H可具有在平面(X-Y平面)上連續環繞內連晶片220的形狀,但本發明概念不限於此。根據絕緣層231的材料,連接構件230可提高封裝的剛性並確保包封體240的厚度均勻性。
絕緣層231可包含熱固性樹脂(例如環氧樹脂)、熱塑性樹脂(例如聚醯亞胺)、或者在該些樹脂中浸漬有無機填料的樹脂(例如,預浸體、ABF、FR-4、BT)或PID。絕緣層231可由多個層形成,且可清晰地區分出各別層之間的邊界。然而,端視製程而定,各個層之間的邊界可能不清晰。
通孔結構235可圍繞內連晶片220設置且可電性連接至第一重佈線層212。通孔結構235可具有其中多個導電元件(例如配線層232及通孔233)在垂直方向上堆疊的形式。舉例而言,在絕緣層231中可埋置有第一配線層232a且第一配線層232a可包括與內連晶片220的底表面共面的底表面。與第一配線層232a相對的第二配線層232b可自絕緣層231突出。配線層232及通孔233可包含銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)及鈦(Ti)或其合金。通孔233可為填充有金屬材料的填充型通孔或者其中金屬材料沿著通孔孔的壁表面形成的共形型通孔。
包封體240可對第二表面S2與內連晶片220及通孔結構235之間的空間進行填充,且可將內連晶片220及通孔結構235中的每一者的至少一部分密封。舉例而言,包封體240可具有第一部分及第二部分,第一部分填充於第一重佈線構件210、內連晶片220及通孔結構235之間,第二部分覆蓋內連晶片220的側表面。包封體240可例如包含熱固性樹脂(例如環氧樹脂)、熱塑性樹脂(例如聚醯亞胺)、或者在該些樹脂中浸漬有無機填料的樹脂(例如,預浸體、ABF、FR-4、BT、環氧樹脂模製化合物(Epoxy Molding Compound,EMC)或類似樹脂)。
柱結構PL1及PL2可穿過包封體240的填充於內連晶片220與通孔結構235之間的部分。柱結構PL1及PL2可包含銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。
在本發明概念的實例性實施例中,柱結構PL1及PL2是藉由將在內連晶片220及通孔結構235上形成的初步柱結構與初步包封體(參見圖9C)一起磨製形成的。因此,第一柱PL1的上表面可實質上位於與第二柱PL2的上表面相同的表面上或與第二柱PL2的上表面共面。如本文中所述,可形成暴露於磨製表面的柱結構PL1及PL2,而無需在磨製製程之後額外對包封體240進行處理的雷射製程(通孔孔形成製程)。在下文中,將參照圖2詳細地對柱結構PL1及PL2進行闡述。
參照圖2,柱結構PL1及PL2可包括第一柱PL1及第二柱PL2,第一柱PL1將第一重佈線層212與內連電路222進行電性連接,第二柱PL2將第一重佈線層212與通孔結構235進行電性連接。
由於不同的引入方法,第一柱PL1與第二柱PL2可具有不同的形狀。第一柱PL1可設置於與內連晶片220交疊或對準的位置(例如在扇入(fan-in)區域中)。在第一柱PL1中,相鄰於第一重佈線構件210的第二表面S2的上部寬度W1a與相鄰於內連晶片220的下部寬度W1b可具有實質上相同的形狀或大小。第二柱PL2可設置於不與內連晶片220交疊或對準的位置(例如在扇出(fan-out)區域中)。第二柱PL2可具有寬度朝向通孔結構235減小的錐形形狀。舉例而言,在第二柱PL2中,相鄰於第一重佈線構件210的第二表面S2的上部寬度W2a可大於相鄰於通孔結構235的下部寬度W2b。
此外,第二柱PL2的與第一重佈線構件210的第二表面S2接觸的上表面的寬度可大於第一柱PL1的與第一重佈線構件210的第二表面S2接觸的上表面的寬度。
此外,第二柱PL2可在平行於第一重佈線構件210的第二表面S2的方向(X方向)上具有大於第一重佈線通孔213的寬度的寬度。舉例而言,第二柱PL2的與通孔結構235接觸的下表面的寬度可大於第一重佈線通孔213的與第二柱PL2接觸的下表面的寬度。
此外,第一柱PL1與第二柱PL2可具有不同的高度。舉例而言,在垂直於第一重佈線構件210的第二表面S2的方向(Z方向)上,第二柱PL2可具有小於第一柱PL1的第一高度H1的第二高度H2。
再次參照圖1A及圖1B,連接凸塊250可設置於內連晶片220及通孔結構235下方。連接凸塊250可經由通孔結構235連接至晶片結構30,且可將所述晶片結構30電性連接至外部裝置(例如模組基板或系統板(system board))。連接凸塊250可形成於鈍化層或保護層251上。保護層251可由絕緣樹脂(例如ABF)形成。根據實例性實施例,保護層251可覆蓋連接凸塊250的側表面及/或下表面的至少一部分。在連接凸塊250下方,可設置有由例如錫(Sn)、銦(In)、鉍(Bi)、銻(Sb)、銅(Cu)、銀(Ag)、鋅(Zn)、鉛(Pb)、或其合金(例如Sn-Ag-Cu)形成的焊料凸塊SB。
第二重佈線構件260可包括第二介電層261及第二重佈線層262,第二介電層261設置於內連晶片220及通孔結構235下方,第二重佈線層262電性連接至通孔結構235。連接凸塊250可設置於第二重佈線構件260下方。第二介電層261可包含感光性樹脂(例如PID)。第二介電層261可形成為大於圖中所示的數目,且端視製程而定,各別層之間的邊界可為清晰的或不清晰的。
第二重佈線層262可將通孔結構235與連接凸塊250電性連接。第二重佈線層262可包含金屬材料,所述金屬材料包括例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。第二重佈線層262可藉由穿透第二介電層261的第二重佈線通孔連接至通孔結構235。
晶片結構30可被設置成在基板20上在水平方向(X方向或Y方向)上彼此間隔開。晶片結構30可經由內連電路222彼此電性連接。晶片結構30中的每一者可在垂直於基板20的垂直方向(Z方向)上與內連晶片220至少部分交疊或對準。舉例而言,晶片結構30可包括第一晶片結構30A及第二晶片結構30B,第一晶片結構30A及第二晶片結構30B分別設置於第一重佈線構件210的第一表面S1上且與內連晶片220的至少一部分交疊。
第一晶片結構30A及第二晶片結構30B可包括邏輯晶片(或處理器晶片)(例如中央處理器(中央處理單元(central processor unit,CPU))、圖形處理器(圖形處理單元(graphic processing unit,GPU))、現場可程式化閘陣列(field programmable gate array,FPGA)、應用處理器(application processor,AP)、數位訊號處理器、密碼處理器(cryptographic processor)、微處理器、微控制器、類比數位轉換器、應用專用積體電路(application-specific IC,ASIC)、應用處理器(AP))以及記憶體晶片,所述記憶體晶片包括揮發性記憶體(例如動態隨機存取記憶體(dynamic random access memory,DRAM)、靜態隨機存取記憶體(static RAM,SRAM)及類似記憶體)以及非揮發性記憶體(例如相變隨機存取記憶體(phase change RAM,PRAM)、磁性隨機存取記憶體(magnetic RAM,MRAM)、電阻式隨機存取記憶體(resistive RAM,RRAM)、快閃記憶體或類似記憶體)。
根據實例性實施例,第一晶片結構30A與第二晶片結構30B可包括不同類型的半導體晶片。舉例而言,第一晶片結構30A可包括邏輯晶片(例如CPU、GPU或ASIC),而第二晶片結構30B可包括記憶體晶片(例如DRAM或快閃記憶體)。
圖3是示出根據實例性實施例的半導體封裝1b的平面圖。
參照圖3,除了半導體封裝1b包括多個內連晶片220-1及220-2之外,根據實例性實施例的所述半導體封裝1b可具有與參照圖1A至圖2闡述的特性相同或相似的特性。
本實施例的半導體封裝1b包括多個內連晶片220-1及220-2,所述多個內連晶片220-1及220-2分別與第一晶片結構30A及第二晶片結構30B至少部分交疊,基板20可具有分別容納所述多個內連晶片220-1及220-2的多個貫通孔210H1及210H2。可根據設計對第一晶片結構30A、第二晶片結構30B以及所述多個內連晶片220-1及220-2的形狀、相對大小及佈置不同地進行修改。
舉例而言,基板20可包括設置於第一貫通孔210H1中的第一內連晶片220-1及設置於第二貫通孔210H2中的第二內連晶片220-2。第一晶片結構30A及第二晶片結構30B可安裝於基板20上以分別與第一內連晶片220-1及第二內連晶片220-2在垂直方向上至少部分交疊或對準。第一晶片結構30A及第二晶片結構30B可藉由第一內連晶片220-1及第二內連晶片220-2進行電性連接。
圖4A是示出根據實例性實施例的半導體封裝1c的平面圖,且圖4B是示出沿著圖4A所示線II-II’截取的橫截面的剖視圖。
參照圖4A及圖4B,根據實例性實施例的半導體封裝1c可具有與參照圖1A至圖3闡述的特性相同或相似的特性。
除了半導體封裝1c包括設置於第一晶片結構30A的周邊上的多個第二晶片結構30B1及30B2之外,根據實例性實施例的所述半導體封裝1c可具有與參照圖1A至圖3闡述的特性相同或相似的特性。
本實施例的半導體封裝1c可包括圍繞第一晶片結構30A設置的所述多個第二晶片結構30B1及30B2,且基板20可包括將所述多個第二晶片結構30B1及30B2分別電性連接至第一晶片結構30A的所述多個內連晶片220-1及220-2。
第一晶片結構30A可藉由柱PL1-1連接至第一內連晶片220-1,且可藉由柱PL2-1連接至通孔結構235。第二晶片結構30B1可藉由柱PL1-1連接至第一內連晶片220-1,且可藉由柱PL2-2連接至通孔結構235。第二晶片結構30B2可藉由柱PL1-2連接至第二內連晶片220-2,且可藉由柱PL2-2連接至通孔結構235。
基板20可具有分別容納所述多個內連晶片220-1及220-2的多個貫通孔210H1及210H2。舉例而言,基板20可包括設置於第一貫通孔210H1中的第一內連晶片220-1及設置於第二貫通孔210H2中的第二內連晶片220-2。第一晶片結構30A、第二晶片結構30B1及第二晶片結構30B2可安裝於基板20上以分別與第一內連晶片220-1及第二內連晶片220-2至少部分交疊。
所述多個第二晶片結構30B1及30B2可在水平方向(例如X方向)上彼此間隔開。第一晶片結構30A可設置於彼此間隔開的所述多個第二晶片結構30B1及30B2之間,但第一晶片結構30A與所述多個第二晶片結構30B1及30B2的佈置關係不限於此。在平面圖中,所述多個第二晶片結構30B1及30B2可相鄰於第一晶片結構30A的左表面及右表面以及第一晶片結構30A的上表面及下表面進行設置。第一晶片結構30A以及所述多個第二晶片結構30B1及30B2可被提供為大於圖中所示的數目,且內連晶片的數目可相應地增加。
圖5是示出根據實例性實施例的半導體封裝1d的剖視圖。
參照圖5,除了半導體封裝1d包括穿透內連晶片220的穿孔224之外,實例性實施例的所述半導體封裝1d可具有與參照圖1A至圖4闡述的特徵相同或相似的特徵。
本實施例的內連晶片220可包括穿孔224及背面接墊225。穿孔224可將內連接墊223與背面接墊225電性連接。穿孔224可為穿過晶片主體221的矽穿孔(through-silicon via,TSV)。根據實例性實施例,內連電路222或第一晶片結構30A及第二晶片結構30B可藉由穿孔224電性連接至第二重佈線層262。
圖6是示出根據實例性實施例的半導體封裝1e的剖視圖。
參照圖6,除了半導體封裝1e更包括嵌入基板20中的被動組件215之外,根據實例性實施例的半導體封裝1e可具有與參照圖1A至圖5闡述的特性相同或相似的特性。
本實施例的基板20可包括圍繞內連晶片220設置且電性連接至第二重佈線層262的至少一個被動組件215。被動組件215可經由第二重佈線層262及通孔結構235電性連接至第一晶片結構30A及第二晶片結構30B。舉例而言,連接構件230可具有用於接納被動組件215的第二貫通孔210H2。第二貫通孔210H2可與容納內連晶片220的第一貫通孔210H1間隔開。被動組件215可包括電容器(例如多層陶瓷電容器(Multi Layer Ceramic Capacitor,MLCC)或低電感晶片電容器(Low Inductance Chip Capacitor,LICC))、電感器(例如晶片電感器、功率電感器、焊珠(bead)及類似電感器)。被動組件215的數目不受特別限制,且可被提供為大於圖中所示的數目。
圖7是示出根據實例性實施例的半導體封裝1f的剖視圖。
參照圖7,除了第二晶片結構30B被設置成高容量記憶體裝置300之外,根據實例性實施例的半導體封裝1f可具有與參照圖1A至圖6闡述的特性相同或相似的特性。在一些實施例中,在第一晶片結構30A及第二晶片結構30B下方可形成有底部填充層UF。底部填充層UF可形成為毛細管底部填充(capillary underfill,CUF)或模製底部填充(molded underfill,MUF)的形式。
在本實施例中,第一晶片結構30A可為包括ASIC或類似晶片的邏輯晶片,且第二晶片結構30B可為包括多個記憶體晶片320(例如包括高頻寬記憶體(High Bandwidth Memory,HBM)或電子資料處理(Electro Data Processing,EDP)裝置)的高容量記憶體裝置300。舉例而言,記憶體裝置300可包括基礎晶片310、記憶體晶片320及模製層330。
基礎晶片310可為包括多個邏輯裝置及/或記憶體裝置的控制晶片或緩衝晶片。基礎晶片310可在外部傳輸來自記憶體晶片320的訊號,且亦可將來自外部的訊號及電力傳輸至記憶體晶片320。
記憶體晶片320可為包括揮發性記憶體裝置(例如DRAM及SRAM)或非揮發性記憶體裝置(例如PRAM、MRAM、鐵電隨機存取記憶體(ferroelectric random access memory,FeRAM)、RRAM及快閃記憶體)的記憶體晶片。記憶體晶片320可藉由貫穿電極320TV彼此電性連接。然而,最上部記憶體晶片320可不包括貫穿電極320TV,且可具有相對更大的厚度。
模製層330可設置於基礎晶片310上且可包封記憶體晶片320中的每一者的至少一部分。模製層330可被形成為暴露出最上部記憶體晶片320的上表面。模製層330可使用例如EMC來形成,但是模製層33的材料不受特別限制。
圖8是示出根據實例性實施例的半導體封裝1g的剖視圖。
參照圖8,除了半導體封裝1g更包括基礎基板10及散熱結構130之外,根據實例性實施例的所述半導體封裝1g可具有與參照圖1A至圖7闡述的特性相同或相似的特性。
本實施例的半導體封裝1g可包括基礎基板10、基板(或中介基板)20及晶片結構30A及30B。
基礎基板10可為其上安裝有中介基板20的支撐基板,且可為半導體封裝(例如印刷電路板(printed circuit board,PCB)、陶瓷基板或膠帶配線板(tape wiring board))的基板。基礎基板10可包括下部接墊112、上部接墊111及配線電路113,下部接墊112設置於下表面上,上部接墊111設置於上表面上,配線電路113將下部接墊112與上部接墊111電性連接。端視基板的類型而定,基礎基板10的主體可包含不同的材料。舉例而言,當基礎基板10為印刷電路板時,所述主體可為覆銅積層板(copper clad laminate)的形式或其中將配線層額外疊層於覆銅積層板的一個表面或兩個表面上的形式。在基礎基板10的下表面上可設置有連接至下部接墊112的外部連接凸塊120。外部連接凸塊120可包含錫(Sn)、銦(In)、鉍(Bi)、銻(Sb)、銅(Cu)、銀(Ag)、鋅(Zn)、鉛(Pb)、及/或其合金。
散熱結構130可設置於基礎基板10的上表面上且可被形成為覆蓋晶片結構30A及30B的上部部分。散熱結構130可藉由黏合劑貼合至基礎基板10。黏合劑可為導熱膠帶、導熱脂、導熱黏合劑或類似黏合劑。在散熱結構130與晶片結構30A及30B之間可設置有熱介面材料層。散熱結構130可包含具有優異的導熱性的材料(例如包括金(Au)、銀(Ag)、銅(Cu)、鐵(Fe)或類似金屬的金屬或金屬合金)或例如石墨、石墨烯或類似材料的材料。散熱結構130可具有與圖中所示的形狀不同的形狀。舉例而言,散熱結構130可具有僅覆蓋晶片結構30A及30B的上部層或上表面的板形狀。
圖9A至圖9E是示出圖1B所示的半導體封裝1a的製造製程的剖視圖。
參照圖9A,首先,可將其中形成有通孔結構235及第二初步柱PL2’的連接構件230貼合至第一載體C1。
第一載體C1可包括例如由於紫外(ultraviolet,UV)照射而失去黏性的膠帶。通孔結構235可具有其中配線層232與通孔233進行堆疊的形式。連接構件230可具有其中容納有內連晶片220的貫通孔210H。貫通孔210H可藉由使用雷射鑽孔移除絕緣層231的一部分來形成。連接構件230可被設置成使得埋置於絕緣層231中的第一配線層232a面朝下。
第二初步柱PL2’可穿透覆蓋通孔結構235的上部部分的第一初步包封體層240p1以接觸通孔結構235。第二初步柱PL2’可包括通孔部分及接墊部分,通孔部分穿透第一初步包封體層240p1,接墊部分突出至第一初步包封體層240p1上。第一初步包封體層240p1可由絕緣樹脂(例如ABF)形成。第二初步柱PL2’可藉由鍍覆製程形成且可包含銅(Cu)或銅(Cu)合金。
接著,可將其上形成有第一初步柱PL1’的內連晶片220貼合至第一載體C1。內連晶片220可設置於連接構件230的貫通孔210H中。內連晶片220可被設置成使得內連接墊223及第一初步柱PL1’面朝上。第一初步柱PL1’可在內連接墊223上形成為支柱(post)形狀。第一初步柱PL1’可包含銅(Cu)或銅(Cu)合金。
參照圖9B,可使用其上形成有第二初步包封體層240p2的第二載體C2形成初步包封體240’。
第二載體C2可包括例如覆銅積層板(copper clad laminate,CCL)。第二初步包封體層240p2可包含與第一初步包封體層240p1相同的材料(例如ABF)。第二初步包封體層240p2可覆蓋第一初步柱PL1’及第二初步柱PL2’,且可被填充於內連晶片220與連接構件230之間。端視製程而定,可能無法清晰地區分出第一初步包封體層240p1與第二初步包封體層240p2之間的邊界。
之後,可移除第一載體C1,且可形成第二重佈線構件260及連接凸塊250。可在內連晶片220及藉由移除第一載體C1而暴露出的通孔結構235上形成第二重佈線構件260。第二重佈線構件260可包括第二介電層261及第二重佈線層262。可藉由塗佈感光性樹脂(例如PID)並使其硬化來形成第二介電層261。可使用光微影製程、鍍覆製程或類似製程來形成第二重佈線層262。
參照圖9C,移除第二載體C2,且可對初步包封體240’的上部部分施加平坦化製程。在平坦化製程及後續製程中,可將第二重佈線構件260貼合至第三載體C3以支撐並固定內連晶片220、連接構件230及類似元件。平坦化製程可包括磨製製程、化學機械研磨(chemical mechanical polishing,CMP)製程及類似製程。藉由平坦化製程移除第一初步柱PL1’及第二初步柱PL2’中的每一者的一部分,且可形成暴露於包封體240的平整表面FS的第一柱PL1及第二柱PL2。因此,第一柱PL1的上表面、第二柱PL2的上表面及包封體240的上表面可實質上共面。
參照圖9D,可在被施加磨製製程的包封體240的平整表面上形成第一重佈線構件210。第一重佈線構件210可包括第一介電層211、第一重佈線層212、第一重佈線通孔213以及第一接墊結構212P1及第二接墊結構212P2。可藉由塗佈感光性樹脂(例如PID)並使其硬化來形成第一介電層211。可使用光微影製程、鍍覆製程或類似製程形成第一重佈線層212、第一重佈線通孔213以及第一接墊結構212P1及第二接墊結構212P2。第一重佈線通孔213可接觸第一柱PL1及第二柱PL2。
參照圖9E,可在第一重佈線構件210上安裝第一晶片結構30A及第二晶片結構30B。第一晶片結構30A及第二晶片結構30B可藉由焊料凸塊34連接至接墊結構212P。之後,可形成用於將第一晶片結構30A及第二晶片結構30B密封的模製層,且在移除第三載體C3之後,暴露出連接凸塊250,藉此製成圖1A及圖1B中的半導體封裝1a。
如上所述,根據實例性實施例,可藉由在連接構件及內連晶片上引入柱結構而提供具有簡化的製程的半導體封裝。
儘管上面已示出並闡述了示例性實施例,然而對於此項技術中具有通常知識者而言將顯而易見,在不背離由隨附申請專利範圍定義的本發明概念的範圍的條件下,可作出各種潤飾及變化。
1a、1b、1c、1d、1e、1f、1g:半導體封裝
10:基礎基板
20:基板/中介基板
30:晶片結構
30A:第一晶片結構/晶片結構
30B:第二晶片結構/晶片結構
30B1、30B2:第二晶片結構
32:接墊
34:焊料凸塊
111:上部接墊
112:下部接墊
113:配線電路
120:外部連接凸塊
130:散熱結構
210:重佈線構件/第一重佈線構件
210H:貫通孔
210H1:貫通孔/第一貫通孔
210H2:貫通孔/第二貫通孔
211:第一介電層
212:第一重佈線層
212P:接墊結構
212P1:第一接墊結構
212P2:第二接墊結構
213:第一重佈線通孔
215:被動組件
220:內連晶片
220-1:內連晶片/第一內連晶片
220-2:內連晶片/第二內連晶片
221:晶片主體
222:內連電路
223:內連接墊
224:穿孔
225:背面接墊
230:連接構件
231:絕緣層
232:配線層
232a:第一配線層
232b:第二配線層
233:通孔
235:通孔結構
240:包封體
240’:初步包封體
240p1:第一初步包封體層
240p2:第二初步包封體層
250:連接凸塊
251:保護層
260:第二重佈線構件
261:第二介電層
262:第二重佈線層
300:高電容記憶體裝置/記憶體裝置
310:基礎晶片
320:記憶體晶片
320TV:貫穿電極
330:模製層
A、B:區域
C1:第一載體
C2:第二載體
C3:第三載體
d1:第一距離或間距/第一距離
d2:第二距離或間距/第二距離
FS:平整表面
H1:第一高度
H2:第二高度
I-I’、II-II’:線
PL1:第一柱/柱結構
PL1’:第一初步柱
PL1-1、PL1-2、PL2-1、PL2-2:柱
PL2:第二柱/柱結構
PL2’:第二初步柱
S1:第一表面
S2:第二表面
SB:焊料凸塊
UF:底部填充層
w1、w2:寬度
W1a、W2a:上部寬度
W1b、W2b:下部寬度
X、Y、Z:方向
結合附圖閱讀以下詳細說明,將更清楚地理解本發明概念的上述及其他態樣、特徵及其他優點,附圖中:
圖1A是示出根據實例性實施例的半導體封裝的平面圖。
圖1B是沿著圖1A所示的線I-I’截取的剖視圖。
圖2是示出圖1B所示的區域「A」及區域「B」的局部放大圖。
圖3是示出根據實例性實施例的半導體封裝的平面圖。
圖4A是示出根據實例性實施例的半導體封裝的平面圖。
圖4B是示出圖4A所示的橫截面II-II’的剖視圖。
圖5是示出根據實例性實施例的半導體封裝的剖視圖。
圖6是示出根據實例性實施例的半導體封裝的剖視圖。
圖7是示出根據實例性實施例的半導體封裝的剖視圖。
圖8是示出根據實例性實施例的半導體封裝的剖視圖。
圖9A至圖9E是示出圖1B所示半導體封裝的製造製程的剖視圖。
1a:半導體封裝
20:基板/中介基板
30A:第一晶片結構/晶片結構
30B:第二晶片結構/晶片結構
32:接墊
34:焊料凸塊
210:重佈線構件/第一重佈線構件
210H:貫通孔
211:第一介電層
212:第一重佈線層
212P:接墊結構
212P1:第一接墊結構
212P2:第二接墊結構
213:第一重佈線通孔
220:內連晶片
221:晶片主體
222:內連電路
223:內連接墊
230:連接構件
231:絕緣層
232:配線層
232a:第一配線層
232b:第二配線層
233:通孔
235:通孔結構
240:包封體
250:連接凸塊
251:保護層
260:第二重佈線構件
261:第二介電層
262:第二重佈線層
A、B:區域
I-I’:線
PL1:第一柱/柱結構
PL2:第二柱/柱結構
S1:第一表面
S2:第二表面
SB:焊料凸塊
X、Y、Z:方向
Claims (10)
- 一種半導體封裝,包括: 基板,包括:第一重佈線構件,包括第一重佈線層且包括彼此相對的第一表面與第二表面;內連晶片,位於所述第二表面下方且包括電性連接至所述第一重佈線層的內連電路;通孔結構,圍繞所述內連晶片設置且電性連接至所述第一重佈線層;包封體,位於所述第二表面與所述內連晶片及所述通孔結構之間;第一柱,延伸穿過所述包封體以將所述第一重佈線層與所述內連電路電性連接;第二柱,延伸穿過所述包封體以將所述第一重佈線層與所述通孔結構電性連接;以及連接凸塊,位於所述內連晶片及所述通孔結構下方;以及 第一晶片結構及第二晶片結構,位於所述第一重佈線構件的所述第一表面上且電性連接至所述第一重佈線層, 其中所述第一柱與所述第二柱具有不同的形狀。
- 如請求項1所述的半導體封裝,其中所述第一柱具有其中相鄰於所述第一重佈線構件的所述第二表面的上部寬度與相鄰於所述內連晶片的下部寬度實質上相同的形狀。
- 如請求項1所述的半導體封裝,其中所述第二柱具有其中寬度在自所述第一重佈線構件的所述第二表面朝向所述通孔結構的方向上減小的錐形形狀。
- 如請求項1所述的半導體封裝,其中所述第一重佈線構件包括:多個第一接墊結構,位於所述第一重佈線構件的所述第一表面上且經由所述第一重佈線層電性連接至所述內連電路;以及多個第二接墊結構,位於所述第一重佈線構件的所述第一表面上且經由所述第一重佈線層電性連接至所述通孔結構, 其中所述第一晶片結構及所述第二晶片結構經由所述多個第一接墊結構電性連接至所述內連電路。
- 如請求項4所述的半導體封裝,其中所述多個第一接墊結構中的相鄰的第一接墊結構之間的第一間距小於所述多個第二接墊結構中的相鄰的第二接墊結構之間的第二間距。
- 一種半導體封裝,包括: 基板,包括:第一重佈線構件,包括彼此相對的第一表面與第二表面且包括第一重佈線層;內連晶片,位於所述第二表面下方且包括電性連接至所述第一重佈線層的內連電路;通孔結構,圍繞所述內連晶片設置且電性連接至所述第一重佈線層;包封體,填充至所述第一重佈線構件的所述第二表面與所述內連晶片及所述通孔結構之間的空間;第一柱,穿過所述包封體以將所述第一重佈線層與所述內連電路電性連接;第二柱,穿過所述包封體以將所述第一重佈線層與所述通孔結構電性連接;以及連接凸塊,位於所述內連晶片及所述通孔結構下方;以及 第一晶片結構及第二晶片結構,位於所述第一重佈線構件的所述第一表面上且電性連接至所述第一重佈線層, 其中所述第一柱與所述第二柱具有不同的高度。
- 如請求項6所述的半導體封裝,其中所述第一柱的上表面與所述第二柱的上表面實質上共面。
- 如請求項6所述的半導體封裝,其中所述第二柱的上表面的寬度大於所述第一柱的上表面的寬度。
- 一種半導體封裝,包括: 第一重佈線構件,包括彼此相對的第一表面與第二表面且包括第一重佈線層; 內連晶片,位於所述第一重佈線構件的所述第二表面下方且包括電性連接至所述第一重佈線層的內連電路; 通孔結構,圍繞所述內連晶片設置且電性連接至所述第一重佈線層; 包封體,包括設置於所述第一重佈線構件的所述第二表面與所述內連晶片及所述通孔結構之間的第一部分、以及設置於所述內連晶片的側表面上的第二部分; 第一柱,延伸穿過所述包封體的所述第一部分並將所述第一重佈線層與所述內連電路電性連接; 第二柱,延伸穿過所述包封體的所述第一部分並將所述第一重佈線層與所述通孔結構電性連接,且包括寬度在自所述第一重佈線構件的所述第二表面朝向所述通孔結構的方向上減小的錐形形狀; 第二重佈線構件,位於所述內連晶片及所述通孔結構下方且包括電性連接至所述通孔結構的第二重佈線層; 連接凸塊,位於所述第二重佈線構件下方且電性連接至所述第二重佈線層;以及 第一晶片結構及第二晶片結構,位於所述第一重佈線構件的所述第一表面上且電性連接至所述第一重佈線層。
- 如請求項9所述的半導體封裝,其中所述第一重佈線構件更包括將所述第一重佈線層連接至所述第一柱及所述第二柱的重佈線通孔,且 所述第二柱的與所述通孔結構接觸的下表面的寬度大於所述重佈線通孔的與所述第二柱接觸的下表面的寬度。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020220086802A KR20240010602A (ko) | 2022-07-14 | 2022-07-14 | 반도체 패키지 |
KR10-2022-0086802 | 2022-07-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202403982A true TW202403982A (zh) | 2024-01-16 |
Family
ID=89485977
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW112118395A TW202403982A (zh) | 2022-07-14 | 2023-05-17 | 半導體封裝 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20240021531A1 (zh) |
KR (1) | KR20240010602A (zh) |
CN (1) | CN117410272A (zh) |
TW (1) | TW202403982A (zh) |
-
2022
- 2022-07-14 KR KR1020220086802A patent/KR20240010602A/ko unknown
-
2023
- 2023-03-28 US US18/191,212 patent/US20240021531A1/en active Pending
- 2023-05-17 TW TW112118395A patent/TW202403982A/zh unknown
- 2023-07-06 CN CN202310826770.0A patent/CN117410272A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US20240021531A1 (en) | 2024-01-18 |
KR20240010602A (ko) | 2024-01-24 |
CN117410272A (zh) | 2024-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI649845B (zh) | 半導體封裝結構及其製造方法 | |
TW202203410A (zh) | 半導體封裝 | |
US20140210080A1 (en) | PoP Device | |
KR102505853B1 (ko) | 반도체 패키지 | |
CN112864109A (zh) | 半导体封装件 | |
TW202123394A (zh) | 半導體封裝 | |
US20230071812A1 (en) | Semiconductor package | |
US20230178492A1 (en) | Semiconductor package | |
TW202125754A (zh) | 半導體封裝 | |
KR20210042212A (ko) | 반도체 패키지 | |
TW202127602A (zh) | 半導體封裝 | |
US20230133322A1 (en) | Semiconductor package and method of manufacturing the same | |
US20220302002A1 (en) | Semiconductor package | |
TW202306093A (zh) | 半導體封裝 | |
TWI802726B (zh) | 電子封裝件及其承載基板與製法 | |
TW202403982A (zh) | 半導體封裝 | |
CN111710672A (zh) | 一种半导体封装件及其制备方法 | |
US20240014197A1 (en) | Semiconductor package and method of manufacturing the same | |
TW202416462A (zh) | 半導體封裝 | |
US20240006272A1 (en) | Semiconductor package and method of manufacturing the same | |
US20240047419A1 (en) | Semiconductor package | |
US20230420415A1 (en) | Semiconductor package | |
US20240162188A1 (en) | Semiconductor package | |
TWI757864B (zh) | 封裝結構及其形成方法 | |
US20230402424A1 (en) | Semiconductor package |