CN117410272A - 半导体封装 - Google Patents
半导体封装 Download PDFInfo
- Publication number
- CN117410272A CN117410272A CN202310826770.0A CN202310826770A CN117410272A CN 117410272 A CN117410272 A CN 117410272A CN 202310826770 A CN202310826770 A CN 202310826770A CN 117410272 A CN117410272 A CN 117410272A
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- Prior art keywords
- redistribution
- chip
- interconnect
- semiconductor package
- redistribution layer
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Abstract
一种半导体封装,包括:衬底,包括:第一再分布构件,包括第一表面和第二表面,并且包括第一再分布层;互连芯片,在第二表面下方,并且包括电连接到第一再分布层的互连电路;过孔结构,在互连芯片周围,并且电连接到第一再分布层;密封物,在第二表面与互连芯片和过孔结构之间;第一柱,延伸穿过密封物,以将第一再分布层和互连电路电连接;第二柱,延伸穿过密封物,以将第一再分布层和过孔结构电连接;以及连接凸块,在互连芯片和过孔结构下方;以及第一芯片结构和第二芯片结构,在第一再分布构件的第一表面上,并且电连接到第一再分布层。第一柱和第二柱具有不同的形状。
Description
相关申请的交叉引用
本申请要求于2022年7月14日在韩国知识产权局递交的韩国专利申请No.10-2022-0086802的优先权,其公开内容通过引用整体合并于此。
技术领域
本发明构思涉及一种半导体封装。
背景技术
安装在电子设备上的半导体器件需要小型化,并且需要具有高性能和大容量。为了其实现,正在开发用于使用贯通电极(例如,硅通孔)将在竖直方向上堆叠的半导体芯片互连的半导体封装。
发明内容
示例实施例提供了一种简化了工艺的半导体封装。
根据示例实施例,一种半导体封装包括:衬底,包括:第一再分布构件,包括彼此相对的第一表面和第二表面,并且包括第一再分布层;互连芯片,在第二表面下方,并且包括电连接到第一再分布层的互连电路;过孔结构,设置在互连芯片周围,并且电连接到第一再分布层;密封物,填充第二表面与互连芯片和过孔结构之间的空间;第一柱,延伸穿过密封物,以将第一再分布层和互连电路电连接;第二柱,延伸穿过密封物,以将第一再分布层和过孔结构电连接;以及连接凸块,在互连芯片和过孔结构下方;以及第一芯片结构和第二芯片结构,在第一再分布构件的第一表面上,并且电连接到第一再分布层。第一柱和第二柱具有不同的形状。
根据示例实施例,一种半导体封装包括:衬底,包括:第一再分布构件,包括彼此相对的第一表面和第二表面,并且包括第一再分布层;互连芯片,在第二表面下方,并且包括电连接到第一再分布层的互连电路;过孔结构,设置在互连芯片周围,并且电连接到第一再分布层;密封物,在第一再分布构件的第二表面与互连芯片和过孔结构之间;第一柱,穿过密封物,以将第一再分布层和互连电路电连接;第二柱,穿过密封物,以将第一再分布层和过孔结构电连接;以及连接凸块,在互连芯片和过孔结构下方;以及第一芯片结构和第二芯片结构,在第一再分布构件的第一表面上,并且电连接到第一再分布层。第一柱和第二柱具有不同的高度。
根据示例实施例,一种半导体封装包括:第一再分布构件,包括彼此相对的第一表面和第二表面,并且包括第一再分布层;互连芯片,在第一再分布构件的第二表面下方,并且包括电连接到第一再分布层的互连电路;过孔结构,设置在互连芯片周围,并且电连接到第一再分布层;密封物,包括设置在第一再分布构件的第二表面与互连芯片和过孔结构之间的第一部分、以及设置在互连芯片的侧表面上的第二部分;第一柱,延伸穿过密封物的第一部分,并且将第一再分布层和互连电路电连接;第二柱,延伸穿过密封物的第一部分,并将第一再分布层和过孔结构电连接,并且具有宽度在从第一再分布构件的第二表面朝向过孔结构的方向上减小的锥形形状;第二再分布构件,在互连芯片和过孔结构下方,并且包括电连接到过孔结构的第二再分布层;连接凸块,在第二再分布构件下方,并且电连接到第二再分布层;以及第一芯片结构和第二芯片结构,在第一再分布构件的第一表面上,并且电连接到第一再分布层。
附图说明
根据结合附图给出的以下详细描述,将更清楚地理解本发明构思的以上和其他方面、特征和优点,在附图中:
图1A是示出了根据示例实施例的半导体封装的平面图;
图1B是沿着图1A的线I-I′截取的截面图;
图2是示出了图1B的区域“A”和区域“B”的局部放大图;
图3是示出了根据示例实施例的半导体封装的平面图;
图4A是示出了根据示例实施例的半导体封装的平面图;
图4B是示出了图4A的截面II-II′的截面图;
图5是示出了根据示例实施例的半导体封装的截面图;
图6是示出了根据示例实施例的半导体封装的截面图;
图7是示出了根据示例实施例的半导体封装的截面图;
图8是示出了根据示例实施例的半导体封装的截面图;以及
图9A至图9E是示出了图1B的半导体封装的制造过程的截面图。
具体实施方式
在下文中,将参考附图来描述示例实施例。
图1A是示出了根据示例实施例的半导体封装的平面图;图1B是沿着图1A的线I-I′截取的截面图;并且图2是示出了图1B的区域“A”和区域“B”的局部放大图。
参考图1A和图1B,根据示例实施例的半导体封装1a可以包括衬底20(或“中介衬底”)和芯片结构30。根据示例实施例,通过在第一再分布构件210与互连芯片220之间以及第一再分布构件210与过孔结构235之间分别引入柱结构PL1和PL2,可以简化半导体封装1a的制造工艺,并且可以提高产量。
衬底20可以包括第一再分布构件210、互连芯片220、连接构件230、密封物240和连接凸块250。在一些实施例中,衬底20还可以包括第二再分布构件260。
第一再分布构件210具有彼此相对的第一表面S1和第二表面S2,并且可以包括第一介电层211、第一再分布层212和第一再分布过孔213。此外,第一再分布构件210(或第一再分布层212)可以包括设置在第一表面S1上的焊盘结构212P。
第一介电层211可以包括热固性树脂(例如,环氧树脂)、热塑性树脂(例如,聚酰亚胺)、或在这些树脂中浸渍有无机填料的树脂(例如,预浸料(prepreg))、味之素积层膜(ABF)、FR-4、双马来酰亚胺三嗪(BT)、或光敏树脂(例如,可光成像电介质(PID)树脂)。第一介电层211可以由多个层形成,并且每个层之间的边界可以清晰地区分。然而,根据工艺,各个层之间的边界可以不清晰。
第一再分布层212可以将互连芯片220、过孔结构235和芯片结构30电连接。第一再分布层212可以基本上再分布芯片结构30的焊盘32。例如,焊盘32可以通过焊料凸块34连接到焊盘结构212P。第一再分布层212可以包括金属材料,该金属材料包括例如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金。根据设计,第一再分布层212可以包括接地(GrouND:GND)图案、电力(PoWeR:PWR)图案和信号(S)图案。除了接地(GND)图案、电力(PWR)图案等之外,信号(S)图案可以提供各种信号的传输路径。
焊盘结构212P可以设置在第一表面S1上,并且可以将芯片结构30和第一再分布层212电连接。焊盘结构212P可以包括设置在第一介电层211上的焊盘部、以及延伸到第一介电层211中以将焊盘部连接到第一再分布层212的过孔部。此外,焊盘结构212P可以包括设置在焊盘部上的表面层。表面层可以包括镍(Ni)、金(Au)或其合金。
焊盘结构212P可以包括通过第一再分布层212电连接到互连电路222的第一焊盘结构212P1、以及通过第一再分布层212电连接到过孔结构235的第二焊盘结构212P2。第一焊盘结构212P1和第二焊盘结构212P2可以在相同的制造过程中形成,因此可以具有基本上相同的尺寸。例如,第一焊盘结构212P1在平行于第一表面S1的方向(X方向)上的宽度w1可以基本上等于第二焊盘结构212P2的宽度w2。
芯片结构30可以通过第一焊盘结构212P1和互连电路222彼此电连接,并且可以通过第二焊盘结构212P2和过孔结构235电连接到连接凸块250。因此,第一焊盘结构212P1可以以精细间距布置,该精细间距与用于芯片结构30的互连的焊盘32的间距相对应。例如,彼此相邻的第一焊盘结构212P1之间的第一距离或间隔d1可以小于彼此相邻的第二焊盘结构212P2之间的第二距离或间隔d2。第一距离d1可以为约60μm或更小,例如,在约10μm至约60μm、约20μm至约60μm、约20μm至约50μm或约20μm至约40μm的范围内,并且第二距离d2可以为约60μm或更大,例如,在约60μm至约100μm或约70μm至约100μm的范围内。
第一再分布过孔213可以将第一再分布层212电连接到第一柱PL1和第二柱PL2。第一再分布过孔213可以包括金属材料,该金属材料包括例如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金。第一再分布过孔213可以是填充有金属材料的填充过孔、或金属材料沿着过孔的内壁形成的共形过孔。
互连芯片220可以设置在第一再分布构件210的第二表面S2上,并且可以包括芯片主体221、互连电路222和互连焊盘223。互连芯片220可以具有芯片主体221的部分区域可以在竖直方向(Z方向)上与芯片结构30重叠或对齐的尺寸或水平面积,以用于芯片结构30的连接。
芯片主体221可以基于陶瓷、玻璃、半导体等来形成。例如,芯片主体221可以基于有源晶片来形成,并且可以包括硅(Si)、锗(Ge)、砷化镓(GaAs)等。钝化层可以形成在芯片主体221的一个表面上,以保护芯片主体221免受外部物理和化学损坏。钝化层可以由氧化膜或氮化膜形成,或者可以由氧化膜和氮化膜的双层形成。例如,钝化层可以由氧化硅膜(SiO)、氮化硅膜(SiN)或其组合形成。
互连电路222可以形成在层间绝缘层中,该层间绝缘层形成在芯片主体221的一个表面上。互连电路222可以通过第一柱PL1和第一再分布层212电连接到第一焊盘结构212P1,并且可以将芯片结构30彼此电连接。互连电路222可以具有比第一再分布层212的间距更精细的间距。互连焊盘223可以设置在层间绝缘层上或其内部,并且可以与第一柱PL1接触,该层间绝缘层形成在芯片主体221的一个表面上。
连接构件230可以包括绝缘层231和过孔结构235。绝缘层231可以围绕过孔结构235的侧表面或在过孔结构235的侧表面上,并且将多个过孔结构235彼此绝缘。连接构件230可以具有穿透绝缘层231并容纳或接纳互连芯片220的通孔210H。通孔210H可以在平面(X-Y平面)上具有连续地围绕互连芯片220的形状,但本发明构思不限于此。根据绝缘层231的材料,连接构件230可以提高封装的刚度,并确保密封物240的厚度均匀性。
绝缘层231可以包括热固性树脂(例如,环氧树脂)、热塑性树脂(例如,聚酰亚胺)、或在这些树脂中浸渍有无机填料的树脂(例如,预浸料)、ABF、FR-4、BT或PID。绝缘层231可以由多个层形成,并且各个层之间的边界可以清晰地区分。然而,根据工艺,层之间的边界可以不清晰。
过孔结构235可以设置在互连芯片220周围,并且可以电连接到第一再分布层212。过孔结构235可以具有多个导电元件(例如,布线层232和过孔233)竖直堆叠的形式。例如,第一布线层232a可以埋入绝缘层231中,并且可以包括与互连芯片220的底表面共面的底表面。与第一布线层232a相对的第二布线层232b可以从绝缘层231突出。布线层232和过孔233可以包括铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金。过孔233可以是填充有金属材料的填充型过孔,或金属材料沿着过孔的壁表面形成的共形型过孔。
密封物240可以填充第二表面S2与互连芯片220和过孔结构235之间的空间,并且可以将互连芯片220和过孔结构235中的每一个的至少一部分密封。例如,密封物240可以具有填充在第一再分布构件210、互连芯片220和过孔结构235之间的第一部分、以及覆盖互连芯片220的侧表面的第二部分。密封物240可以包括例如热固性树脂(例如,环氧树脂)、热塑性树脂(例如,聚酰亚胺)、或在这些树脂中浸渍有无机填料的树脂(例如,预浸料)、ABF、FR-4、BT、环氧模制化合物(EMC)等。
柱结构PL1和PL2可以穿过密封物240的填充在互连芯片220和过孔结构235之间的一部分。柱结构PL1和PL2可以包括铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金。
在本发明构思的示例实施例中,通过将形成在互连芯片220和过孔结构235上的初步柱结构与初步密封物一起研磨来形成柱结构PL1和PL2(参见图9C)。因此,第一柱PL1的上表面可以与第二柱PL2的上表面基本上在相同的表面上,或与第二柱PL2的上表面基本上共面。如本文中所描述的,可以形成暴露于研磨表面的柱结构PL1和PL2,而无需在研磨工艺之后附加地处理密封物240的激光工艺(过孔形成工艺)。在下文中,将参考图2详细地描述柱结构PL1和PL2。
参考图2,柱结构PL1和PL2可以包括将第一再分布层212和互连电路222电连接的第一柱PL1、以及将第一再分布层212和过孔结构235电连接的第二柱PL2。
由于不同的引入方法,第一柱PL1和第二柱PL2可以具有不同的形状。第一柱PL1可以设置在与互连芯片220重叠或对齐的位置中,例如,在扇入(fan-in)区域中。在第一柱PL1中,与第一再分布构件210的第二表面S2相邻的上部宽度W1 a和与互连芯片220相邻的下部宽度W1b可以具有基本上相同的形状或尺寸。第二柱PL2可以设置在不与互连芯片220重叠或对齐的位置中,例如,在扇出(fan-out)区域中。第二柱PL2可以具有宽度朝向过孔结构235减小的锥形形状。例如,在第二柱PL2中,与第一再分布构件210的第二表面S2相邻的上部宽度W2a可以大于与过孔结构235相邻的下部宽度W2b。
此外,第二柱PL2的与第一再分布构件210的第二表面S2接触的上表面的宽度可以大于第一柱PL1的与第一再分布构件210的第二表面S2接触的上表面的宽度。
此外,在平行于第一再分布构件210的第二表面S2的方向(X方向)上,第二柱PL2的宽度可以大于第一再分布过孔213的宽度。例如,第二柱PL2的与过孔结构235接触的下表面的宽度可以大于第一再分布过孔213的与第二柱PL2接触的下表面的宽度。
此外,第一柱PL1和第二柱PL2可以具有不同的高度。例如,在与第一再分布构件210的第二表面S2垂直的方向(Z方向)上,第二柱PL2可以具有小于第一柱PL1的第一高度H1的第二高度H2。
再次参考图1A和图1B,连接凸块250可以设置在互连芯片220和过孔结构235下方。连接凸块250可以通过过孔结构235连接到芯片结构30,并且可以将芯片结构30电连接到诸如模块衬底或系统板之类的外部设备。连接凸块250可以形成在钝化或保护层251上。保护层251可以由诸如ABF之类的绝缘树脂形成。根据示例实施例,保护层251可以覆盖连接凸块250的侧表面和/或下表面的至少一部分。在连接凸块250下方,可以设置由例如锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)或其合金(例如,Sn-Ag-Cu)形成的焊料凸块SB。
第二再分布构件260可以包括设置在互连芯片220和过孔结构235下方的第二介电层261、以及电连接到过孔结构235的第二再分布层262。连接凸块250可以设置在第二再分布构件260下方。第二介电层261可以包括诸如PID之类的光敏树脂。第二介电层261可以以比附图中所示的数量更大的数量来形成,并且各个层之间的边界可以根据工艺而清晰或不清晰。
第二再分布层262可以将过孔结构235和连接凸块250电连接。第二再分布层262可以包括金属材料,该金属材料包括例如铜(Cu)、铝(A1)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金。第二再分布层262可以通过穿透第二介电层261的第二再分布过孔连接到过孔结构235。
芯片结构30可以设置为在衬底20上沿水平方向(X方向或Y方向)彼此间隔开。芯片结构30可以经由互连电路222彼此电连接。每个芯片结构30可以在垂直于衬底20的竖直方向(Z方向)上至少部分地与互连芯片220重叠或对齐。例如,芯片结构30可以包括第一芯片结构30A和第二芯片结构30B,该第一芯片结构30A和第二芯片结构30B设置在第一再分布构件210的第一表面S1上,并且分别与互连芯片220的至少一部分重叠。
第一芯片结构30A和第二芯片结构30B可以包括逻辑芯片(或处理器芯片)(例如,中央处理器(CPU)、图形处理器(GPU)、现场可编程门阵列(FPGA)、应用处理器(AP)、数字信号处理器、加密处理器、微处理器、微控制器、模数转换器、专用IC(ASIC))和存储芯片,该存储芯片包括易失性存储器(例如,动态RAM、(DRAM)、静态RAM(SRAM)等)和非易失性存储器(例如,相变RAM(PRAM)、磁性RAM(MRAM)、电阻式RAM(RRAM)、闪存等)。
根据示例实施例,第一芯片结构30A和第二芯片结构30B可以包括不同类型的半导体芯片。例如,第一芯片结构30A可以包括诸如CPU、GPU或ASIC之类的逻辑芯片,并且第二芯片结构30B可以包括诸如DRAM或闪存之类的存储芯片。
图3是示出了根据示例实施例的半导体封装1b的平面图。
参考图3,除了包括多个互连芯片220-1和220-2之外,根据示例实施例的半导体封装1b可以具有与参考图1A至图2描述的那些特性相同或相似的特性。
本实施例的半导体封装1b包括分别与第一芯片结构30A和第二芯片结构30B至少部分地重叠的多个互连芯片220-1和220-2,并且衬底20可以具有分别容纳多个互连芯片220-1和220-2的多个通孔210H1和210H2。第一芯片结构30A、第二芯片结构30B以及多个互连芯片220-1和220-2的形状、相对尺寸和布置可以根据设计进行各种修改。
例如,衬底20可以包括设置在第一通孔210H1中的第一互连芯片220-1和设置在第二通孔210H2中的第二互连芯片220-2。第一芯片结构30A和第二芯片结构30B可以安装在衬底20上,以分别与第一互连芯片220-1和第二互连芯片220-2至少部分地竖直重叠或对齐。第一芯片结构30A和第二芯片结构30B可以通过第一互连芯片220-1和第二互连芯片220-2电连接。
图4A是示出了根据示例实施例的半导体封装1c的平面图,并且图4B是示出了沿着图4A的线II-II′截取的截面的截面图。
参考图4A和图4B,根据示例实施例的半导体封装1c可以具有与参考图1A至图3描述的那些特性相同或相似的特性。
除了包括设置在第一芯片结构30A的外围上的多个第二芯片结构30B1和30B2之外,根据示例实施例的半导体封装1c可以具有与参考图1A至图3描述的那些特性相同或相似的特性。
本实施例的半导体封装1c可以包括设置在第一芯片结构30A周围的多个第二芯片结构30B1和30B2,并且衬底20可以包括分别将多个第二芯片结构30B1和30B2电连接到第一芯片结构30A的多个互连芯片220-1和220-2。
第一芯片结构30A可以通过柱PL1-1连接到第一互连芯片220-1,并且可以通过柱PL2-1连接到过孔结构235。第二芯片结构30B1可以通过柱PL1-1连接到第一互连芯片220-1,并且可以通过柱PL2-2连接到过孔结构235。第二芯片结构30B2可以通过柱PL1-2连接到第二互连芯片220-2,并且可以通过柱PL2-2连接到过孔结构235。
衬底20可以具有分别容纳多个互连芯片220-1和220-2的多个通孔210H1和210H2。例如,衬底20可以包括设置在第一通孔210H1中的第一互连芯片220-1和设置在第二通孔210H2中的第二互连芯片220-2。第一芯片结构30A、以及第二芯片结构30B1和第二芯片结构30B2可以安装在衬底20上,以分别与第一互连芯片220-1和第二互连芯片220-2至少部分地重叠。
多个第二芯片结构30B1和30B2可以在水平方向(例如,X方向)上彼此间隔开。第一芯片结构30A可以设置在彼此间隔开的多个第二芯片结构30B1和30B2之间,但是第一芯片结构30A和多个第二芯片结构30B1和30B2的布置关系不限于此。在平面图中,多个第二芯片结构30B1和30B2可以设置为与第一芯片结构30A的左表面和右表面以及第一芯片结构30A的上表面和下表面相邻。第一芯片结构30A和多个第二芯片结构30B1和30B2可以以比附图中所示的数量更大的数量设置,并且互连芯片的数量可以相应地增加。
图5是示出了根据示例实施例的半导体封装1d的截面图。
参考图5,除了包括穿透互连芯片220的通孔224之外,示例实施例的半导体封装1d可以具有与参考图1A至图4B描述的那些特征相同或相似的特征。
本实施例的互连芯片220可以包括通孔224和背焊盘225。通孔224可以将互连焊盘223和背焊盘225电连接。通孔224可以是穿过芯片主体221的硅通孔(TSV)。根据示例实施例,互连电路222或第一芯片结构30A和第二芯片结构30B可以通过通孔224电连接到第二再分布层262。
图6是示出了根据示例实施例的半导体封装1e的截面图。
参考图6,除了根据示例实施例的半导体封装1e还包括嵌入在衬底20中的无源组件215之外,半导体封装1e可以具有与参考图1A至图5描述的那些特性相同或相似的特性。
本实施例的衬底20可以包括至少一个无源组件215,其设置在互连芯片220周围,并且电连接到第二再分布层262。无源组件215可以通过第二再分布层262和过孔结构235电连接到第一芯片结构30A和第二芯片结构30B。例如,连接构件230可以具有用于接纳无源组件215的第二通孔210H2。第二通孔210H2可以与容纳互连芯片220的第一通孔210H1间隔开。无源组件215可以包括电容器(例如多层陶瓷电容器(MLCC)或低电感芯片电容器(LICC))、电感器(例如芯片电感器、功率电感器)、磁珠等。无源组件215的数量不受特别限制,并且可以以比附图所示的数量大的数量设置。
图7是示出了根据示例实施例的半导体封装1f的截面图。
参考图7,除了第二芯片结构30B设置为大容量存储器件300之外,根据示例实施例的半导体封装1f可以具有与参考图1A至图6描述的那些特性相同或相似的特性。在一些实施例中,底部填充层UF可以形成在第一芯片结构30A和第二芯片结构30B下方。底部填充层UF可以以毛细底部填充(CUF)或模制底部填充(MUF)的形式形成。
在本实施例中,第一芯片结构30A可以是包括ASIC等的逻辑芯片,并且第二芯片结构30B可以是包括多个存储芯片320(例如,包括高带宽存储器(HBM)或电子数据处理(EDP)器件)的大容量存储器件300。例如,存储器件300可以包括基底芯片310、存储芯片320和模制层330。
基底芯片310可以是包括多个逻辑器件和/或存储器件的控制芯片或缓冲芯片。基底芯片310可以从存储芯片320向外部传输信号,并且也可以从外部向存储芯片320传输信号和电力。
存储芯片320可以是包括诸如DRAM和SRAM之类的易失性存储器件或诸如PRAM、MRAM、FeRAM、RRAM和闪存之类的非易失性存储器件的存储芯片。存储芯片320可以通过贯通电极320TV彼此电连接。然而,最上面的存储芯片320可以不包括贯通电极320TV,并且可以具有相对更大的厚度。
模制层330可以设置在基底芯片310上,并且可以将每个存储芯片320的至少一部分密封。模制层330可以形成为暴露最上面的存储芯片320的上表面。模制层330可以使用例如EMC来形成,但是模制层33的材料不受特别限制。
图8是示出了根据示例实施例的半导体封装1g的截面图。
参考图8,除了还包括基底衬底10和散热结构130之外,根据示例实施例的半导体封装1g可以具有与参考图1A至图7所描述的那些特性相同或相似的特性。
本实施例的半导体封装1g可以包括基底衬底10、衬底(或中介衬底)20以及芯片结构30A和30B。
基底衬底10可以是安装有中介衬底20的支撑衬底,并且可以是用于半导体封装的衬底(例如,印刷电路板(PCB)、陶瓷衬底或带式布线板)。基底衬底10可以包括设置在下表面上的下焊盘112、设置在上表面上的上焊盘111、以及将下焊盘112和上焊盘111电连接的布线电路113。基底衬底10的主体可以根据衬底的类型而包括不同的材料。例如,当基底衬底10为印刷电路板时,该主体可以为覆铜层压板的形式,或者为在覆铜层压板的一个表面或两个表面上附加地层压布线层的形式。连接到下焊盘112的外部连接凸块120可以设置在基底衬底10的下表面上。外部连接凸块120可以包括锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)和/或其合金。
散热结构130可以设置在基底衬底10的上表面上,并且可以形成为覆盖芯片结构30A和30B的上部。散热结构130可以通过粘合剂附接到基底衬底10。粘合剂可以为导热胶带、导热油脂、导热粘合剂等。热界面材料层可以设置在散热结构130与芯片结构30A和30B之间。散热结构130可以包括具有良好的导热性的材料,例如,包括金(Au)、银(Ag)、铜(Cu)、铁(Fe)等的金属或金属合金,或诸如石墨、石墨烯等的材料。散热结构130可以具有与附图中所示的形状不同的形状。例如,散热结构130可以具有仅覆盖芯片结构30A和30B的上层或上表面的板状形状。
图9A至图9E是示出了图1B的半导体封装1a的制造过程的截面图。
参考图9A,首先,可以将其中形成有过孔结构235和第二初步柱PL2′的连接构件230附接到第一载体C1。
第一载体C1可以包括例如由于紫外线(UV)照射而失去粘合性的胶带。过孔结构235可以具有布线层232和过孔233堆叠的形式。连接构件230可以具有容纳互连芯片220的通孔210H。可以通过使用激光钻孔去除绝缘层231的一部分来形成通孔210H。连接构件230可以设置为使得埋入绝缘层231中的第一布线层232a面向下。
第二初步柱PL2′可以穿透覆盖过孔结构235的上部的第一初步密封物层240p1,以接触过孔结构235。第二初步柱PL2′可以包括穿透第一初步密封物层240p1的过孔部分和突出到第一初步密封物层240p1上的焊盘部分。第一初步密封物层240p1可以由诸如ABF之类的绝缘树脂形成。可以通过电镀工艺形成第二初步柱PL2′,并且第二初步柱PL2′可以包括铜(Cu)或铜(Cu)合金。
接下来,其上形成有第一初步柱PL1′的互连芯片220可以附接到第一载体C1。互连芯片220可以设置在连接构件230的通孔210H中。互连芯片220可以设置为使得互连焊盘223和第一初步柱PL1′面向上。第一初步柱PL1′可以以圆柱形状形成在互连焊盘223上。第一初步柱PL1′可以包括铜(Cu)或铜(Cu)合金。
参考图9B,可以使用其上形成有第二初步密封物层240p2的第二载体C2来形成初步密封物240′。
第二载体C2可以包括例如覆铜层压板(CCL)。第二初步密封物层240p2可以包括与第一初步密封物层240p1相同的材料,例如,ABF。第二初步密封物层240p2可以覆盖第一初步柱PL1′和第二初步柱PL2′,并且可以填充在互连芯片220和连接构件230之间。根据工艺,可能不能清晰地区分第一初步密封物层240p1和第二初步密封物层240p2之间的边界。
此后,可以去除第一载体C1,并且可以形成第二再分布构件260和连接凸块250。可以在通过去除第一载体C1而暴露的互连芯片220和过孔结构235上形成第二再分布构件260。第二再分布构件260可以包括第二介电层261和第二再分布层262。可以通过涂覆和固化诸如PID之类的光敏树脂来形成第二介电层261。可以使用光刻工艺、电镀工艺等来形成第二再分布层262。
参考图9C,去除第二载体C2,并且可以对初步密封物240′的上部施加平坦化工艺。在平坦化工艺和后续工艺中,第二再分布构件260可以附接到第三载体C3,以支撑和固定互连芯片220、连接构件230等。平坦化工艺可以包括研磨工艺、化学机械抛光(CMP)工艺等。通过平坦化工艺来去除第一初步柱PL1′和第二初步柱PL2′中的每一个的一部分,并且可以形成暴露于密封物240的平坦表面FS的第一柱PL1和第二柱PL2。因此,第一柱PL1的上表面、第二柱PL2的上表面和密封物240的上表面可以基本上共面。
参考图9D,可以在密封物240的施加了研磨工艺的平坦表面上形成第一再分布构件210。第一再分布构件210可以包括第一介电层211、第一再分布层212、第一再分布过孔213以及第一焊盘结构212P1和第二焊盘结构212P2。可以通过涂覆和固化诸如PID之类的光敏树脂来形成第一介电层211。可以使用光刻工艺、电镀工艺等来形成第一再分布层212、第一再分布过孔213以及第一焊盘结构212P1和第二焊盘结构212P2。第一再分布过孔213可以接触第一柱PL1和第二柱PL2。
参考图9E,可以在第一再分布构件210上安装第一芯片结构30A和第二芯片结构30B。可以通过焊料凸块34将第一芯片结构30A和第二芯片结构30B连接到焊盘结构212P。此后,可以形成用于将第一芯片结构30A和第二芯片结构30B密封的模制层,并且在去除第三载体C3之后,暴露连接凸块250,从而制造图1A和图1B中的半导体封装1a。
如上所述,根据示例实施例,可以通过在连接构件和互连芯片上引入柱结构来提供具有简化工艺的半导体封装。
虽然以上已经示出并描述了示例实施例,但是本领域技术人员应清楚,在不脱离由所附权利要求限定的本发明构思的范围的情况下,可以进行修改和改变。
Claims (20)
1.一种半导体封装,包括:
衬底,包括:第一再分布构件,包括第一再分布层,并且包括彼此相对的第一表面和第二表面;互连芯片,在所述第二表面下方,并且包括电连接到所述第一再分布层的互连电路;过孔结构,设置在所述互连芯片周围,并且电连接到所述第一再分布层;密封物,在所述第二表面与所述互连芯片和所述过孔结构之间;第一柱,延伸穿过所述密封物,以将所述第一再分布层和所述互连电路电连接;第二柱,延伸穿过所述密封物,以将所述第一再分布层和所述过孔结构电连接;以及连接凸块,在所述互连芯片和所述过孔结构下方;以及
第一芯片结构和第二芯片结构,在所述第一再分布构件的所述第一表面上,并且电连接到所述第一再分布层,
其中,所述第一柱和所述第二柱具有不同的形状。
2.根据权利要求1所述的半导体封装,其中,所述第一柱具有邻近所述第一再分布构件的所述第二表面的上部宽度和邻近所述互连芯片的下部宽度基本上相同的形状。
3.根据权利要求1所述的半导体封装,其中,所述第二柱具有宽度在从所述第一再分布构件的所述第二表面朝向所述过孔结构的方向上减小的锥形形状。
4.根据权利要求1所述的半导体封装,其中,所述第二柱的与所述第一再分布构件的所述第二表面接触的上表面的宽度大于所述第一柱的与所述第一再分布构件的所述第二表面接触的上表面的宽度。
5.根据权利要求1所述的半导体封装,其中,所述第一再分布构件还包括介电层和再分布过孔,所述再分布过孔延伸穿过所述介电层,并且将所述第一再分布层连接到所述第一柱和所述第二柱。
6.根据权利要求5所述的半导体封装,其中,所述第二柱的宽度大于所述再分布过孔的宽度。
7.根据权利要求5所述的半导体封装,其中,所述介电层包括光敏树脂。
8.根据权利要求1所述的半导体封装,其中,所述第一芯片结构和所述第二芯片结构通过所述互连电路彼此电连接。
9.根据权利要求1所述的半导体封装,其中,所述第一再分布构件包括第一焊盘结构和第二焊盘结构,所述第一焊盘结构在所述第一再分布构件的所述第一表面上,并且通过所述第一再分布层电连接到所述互连电路,所述第二焊盘结构在所述第一再分布构件的所述第一表面上,并且通过所述第一再分布层电连接到所述过孔结构,
其中,所述第一芯片结构和所述第二芯片结构通过所述第一焊盘结构电连接到所述互连电路。
10.根据权利要求9所述的半导体封装,其中,所述第一焊盘结构中的相邻的第一焊盘结构之间的第一间隔小于所述第二焊盘结构中的相邻的第二焊盘结构之间的第二间隔。
11.根据权利要求10所述的半导体封装,其中,所述第一间隔在10μm至60μm的范围内,并且
所述第二间隔在60μm至100μm的范围内。
12.根据权利要求9所述的半导体封装,其中,所述第一焊盘结构的宽度与所述第二焊盘结构的宽度基本上相同。
13.根据权利要求1所述的半导体封装,其中,所述衬底还包括第二再分布构件,所述第二再分布构件设置在所述连接凸块、所述互连芯片和所述过孔结构之间,并且所述第二再分布构件包括将所述过孔结构电连接到所述连接凸块的第二再分布层。
14.根据权利要求1所述的半导体封装,其中,所述衬底还包括连接构件,所述连接构件包括所述过孔结构和在所述过孔结构的侧表面上的绝缘层,并且所述连接构件包括接纳所述互连芯片的通孔。
15.一种半导体封装,包括:
衬底,包括:第一再分布构件,包括彼此相对的第一表面和第二表面,并且包括第一再分布层;互连芯片,在所述第二表面下方,并且包括电连接到所述第一再分布层的互连电路;过孔结构,设置在所述互连芯片周围,并且电连接到所述第一再分布层;密封物,填充所述第一再分布构件的所述第二表面与所述互连芯片和所述过孔结构之间的空间;第一柱,穿过所述密封物,以将所述第一再分布层和所述互连电路电连接;第二柱,穿过所述密封物,以将所述第一再分布层和所述过孔结构电连接;以及连接凸块,在所述互连芯片和所述过孔结构下方;以及
第一芯片结构和第二芯片结构,在所述第一再分布构件的所述第一表面上,并且电连接到所述第一再分布层,
其中,所述第一柱和所述第二柱具有不同的高度。
16.根据权利要求15所述的半导体封装,其中,在与所述第一再分布构件的所述第二表面垂直的方向上,所述第二柱的高度小于所述第一柱的高度。
17.根据权利要求15所述的半导体封装,其中,所述第一柱的上表面与所述第二柱的上表面基本上共面。
18.根据权利要求15所述的半导体封装,其中,所述第二柱的上表面的宽度大于所述第一柱的上表面的宽度。
19.一种半导体封装,包括:
第一再分布构件,包括彼此相对的第一表面和第二表面,并且包括第一再分布层;
互连芯片,在所述第一再分布构件的所述第二表面下方,并且包括电连接到所述第一再分布层的互连电路;
过孔结构,设置在所述互连芯片周围,并且电连接到所述第一再分布层;
密封物,包括设置在所述第一再分布构件的所述第二表面与所述互连芯片和所述过孔结构之间的第一部分、以及设置在所述互连芯片的侧表面上的第二部分;
第一柱,延伸穿过所述密封物的所述第一部分,并且将所述第一再分布层和所述互连电路电连接;
第二柱,延伸穿过所述密封物的所述第一部分,并将所述第一再分布层和所述过孔结构电连接,并且具有宽度在从所述第一再分布构件的所述第二表面朝向所述过孔结构的方向上减小的锥形形状;
第二再分布构件,在所述互连芯片和所述过孔结构下方,并且包括电连接到所述过孔结构的第二再分布层;
连接凸块,在所述第二再分布构件下方,并且电连接到所述第二再分布层;以及
第一芯片结构和第二芯片结构,在所述第一再分布构件的所述第一表面上,并且电连接到所述第一再分布层。
20.根据权利要求19所述的半导体封装,其中,所述第一再分布构件还包括将所述第一再分布层连接到所述第一柱和所述第二柱的再分布过孔,并且
所述第二柱的与所述过孔结构接触的下表面的宽度大于所述再分布过孔的与所述第二柱接触的下表面的宽度。
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