CN109216310B - 半导体封装装置及其制造方法 - Google Patents

半导体封装装置及其制造方法 Download PDF

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CN109216310B
CN109216310B CN201810184022.6A CN201810184022A CN109216310B CN 109216310 B CN109216310 B CN 109216310B CN 201810184022 A CN201810184022 A CN 201810184022A CN 109216310 B CN109216310 B CN 109216310B
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conductive
electronic component
conductive pad
layer
semiconductor package
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CN109216310A (zh
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方仁广
吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体封装装置包括第一介电层、第一导电垫及第一导电元件。所述第一介电层具有第一表面及与所述第一表面相对的第二表面。所述第一介电层界定从所述第一表面朝向所述第二表面渐缩的第一开口。所述第一导电垫在所述第一开口内且邻近于所述第一介电层的所述第二表面。所述第一导电元件的至少一部分在所述第一开口内。所述第一导电元件与所述第一开口的侧壁接合(例如，邻接)，所述第一导电元件具有面向所述第一导电垫的第一表面，其中所述第一导电元件的所述第一表面与所述第一导电垫隔开。

Description

半导体封装装置及其制造方法
技术领域
本公开大体上涉及一种半导体封装装置及其制造方法。更特定来说，本公开涉及一种包含倒装芯片结合结构的半导体封装装置及其制造方法。
背景技术
在半导体封装装置中，可通过倒装芯片结合技术将裸片或芯片附接到衬底。举例来说，在用于将裸片安装到衬底(例如，电路板或另一芯片)的倒装芯片结合工艺期间，将裸片翻转，使得裸片的导电柱与衬底的对应导电垫对准。然而，衬底的导电垫的相对粗糙表面或结合器或结合设备的不准确度可引起衬底的导电垫与裸片的导电柱之间的移位或未对准。移位或未对准可不利地影响安置在导电垫与导电柱之间的连接结构(例如焊料材料或焊料球)且导致例如裸片与衬底之间的开路的可靠性问题。
发明内容
在一或多个实施例中，一种半导体封装装置包括第一介电层、第一导电垫及第一导电元件。所述第一介电层具有第一表面及与所述第一表面相对的第二表面。所述第一介电层界定从所述第一表面面向所述第二表面渐缩的第一开口。所述第一导电垫在所述第一开口内且邻近于所述第一介电层的所述第二表面。所述第一导电元件的至少一部分在所述第一开口内。所述第一导电元件与所述第一开口的侧壁接合(例如，邻接)，所述第一导电元件具有面向所述第一导电垫的第一表面，其中所述第一导电元件的所述第一表面与所述第一导电垫隔开。
在一或多个实施例中，一种半导体封装装置包括介电层、导电垫、导电柱及第一金属间化合物(IMC)层。所述介电层具有第一表面及与所述第一表面相对的第二表面。所述介电层界定从所述表面面向所述第二表面渐缩的开口。所述导电垫在所述开口内且邻近于所述介电层的所述第二表面。所述导电柱的至少一部分在所述开口内，且所述导电柱具有面向所述导电垫的第一表面。所述第一IMC层在所述导电柱的所述第一表面上且从所述导电柱的所述第一表面延伸到所述导电柱中。所述第一IMC层与所述开口的侧壁接合(例如，邻接)。
在一或多个实施例中，一种半导体封装装置包括介电层、导电垫、导电柱及第一IMC 层。所述介电层具有第一表面及与所述第一表面相对的第二表面。所述介电层界定从所述第一表面面向所述第二表面渐缩的开口。所述导电垫在所述开口内且邻近于所述介电层的所述第二表面。所述导电柱的至少一部分在所述开口内。所述导电柱具有第一部分及在所述第一部分上的第二部分。所述导电柱的所述第一部分的宽度小于所述导电柱的所述第二部分的宽度。所述第一IMC层覆盖所述导电柱的所述第一部分。
附图说明
在与附图一起阅读时可从以下详述描述最佳地理解本公开的方面。应注意，各种特征可能未按比例绘制，且各种特征的尺寸可出于论述清楚起见而任意地增大或减小。
图1A说明根据本公开的一些实施例的半导体封装装置的横截面图；
图1B说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1C说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1D说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1E说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1F说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1G说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1H说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1I说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1J说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1K说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1L说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1M说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图1N说明根据本公开的一些实施例的图1A中的半导体封装装置的连接结构的放大图；
图2说明根据本公开的一些实施例的半导体封装装置的横截面图；
图3说明根据本公开的一些实施例的半导体封装装置的横截面图；
图4A说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图4B说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图4C说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图4D说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图4E说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图4F说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图4G说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图5A说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图5B说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图5C说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图5D说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图6A说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图6B说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图6C说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图6D说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图6E说明根据本公开的一些实施例的制造半导体封装装置的方法的一或多个阶段；
图7A说明根据本公开的一些实施例的各种类型的半导体封装装置；及
图7B说明根据本公开的一些实施例的各种类型的半导体封装装置。
贯穿图式及详细描述使用共同参考数字来指示相同或相似元件。本公开从结合附图进行的以下详细描述将更显而易见。
具体实施方式
图1A说明根据本公开的一些实施例的半导体封装装置1的横截面图。半导体封装装置1包含：载体10；电子组件11a、11b；封装体12；底部填充料12u；及连接结构 13、14及15。
载体10可为例如印刷电路板，例如纸基铜箔层压板、复合铜箔层压板、聚合物浸渍玻璃纤维基铜箔层压板，或其中的两者或多于两者的组合。载体10可包含互连结构，例如重布层(RDL)。在一些实施例中，载体10的表面101被称作顶部表面或第一表面，且载体10的表面102被称作底部表面或第二表面。载体10可包含在其底部表面102上的一或多个导电垫16p。一或多个电触点16安置在载体10的导电垫16p上。在一些实施例中，导电垫16p的厚度小于如图1B到1F所展示的导电垫10p的厚度。在一些实施例中，电触点16为可控塌陷芯片连接(Controlled Collapse Chip Connection；C4)凸块、球栅格阵列(Ball Grid Array；BGA)或焊盘栅格阵列(Land Grid Array；LGA)。
电子组件11a安置在载体10的顶部表面101上且通过连接结构13电连接到载体10。电子组件11a可为例如包含半导体衬底的芯片或裸片、一或多个集成电路装置，及其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及/或例如电阻器、电容器、电感器或其中的两者或三者的组合的无源装置。在一些实施例中，电子组件11a为双面电子组件。电子组件11a的表面11a1通过例如倒装芯片技术(例如，通过连接结构13及/或15)电连接到载体10，而电子组件11a的表面11a2通过例如导线结合技术电连接到载体10。
电子组件11b安置在电子组件11a的表面11a2上且通过连接结构14电连接到电子组件11a。电子组件11b可为例如包含半导体衬底的芯片或裸片、一或多个集成电路装置，及其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及 /或例如电阻器、电容器、电感器或其中的两者或多于两者的组合的无源装置。在一些实施例中，取决于设计规范，电子组件11b的面积可大于、基本上等于或小于电子组件11a 的面积。在一些实施例中，电子组件11b为单面电子组件。替代地，取决于设计规范，电子组件11b可为双面电子组件。在一些实施例中，取决于设计规范，不需要电子组件 11b。举例来说，半导体封装装置1可包含一个电子组件11a。在一些实施例中，至少一个电子组件可堆叠在电子组件11b上。堆叠式电子组件的数目可取决于不同实施例而变化。
底部填充料12u可安置在载体10的顶部表面101上以覆盖电子组件11a及11b的有源表面(例如，邻近于连接结构13或14的表面)及连接结构13及14。在一些实施例中，底部填充料12u包含环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、包含分散于其中的硅酮的材料，或其中的两者或多于两者的组合。在一些实施例中，取决于不同实施例，底部填充料12u可为毛细底部填充料(CUF) 或成型底部填充料(MUF)。
封装体12安置在载体10的顶部表面101上且覆盖电子组件11b及底部填充料12u的至少一部分。在一些实施例中，封装体12包含例如有机材料(例如，封装材料、双马来酰亚胺三嗪(BT)、聚酰亚胺(PI)、聚苯并恶唑(PBO)、阻焊剂、味之素(Ajinomoto)累积膜(ABF)、聚丙烯(PP)、环氧基材料，或其中的两者或多于两者的组合)、无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两者或多于两者的组合)、液体、干膜材料，或其中的两者或多于两者的组合。
图1B说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构13的放大图。连接结构13包含介电层13d、焊料层13s及导电柱13p(也被称作导电元件)。
介电层13d安置在如图1A所展示的载体10的顶部表面101上。介电层13d具有第一表面13d1及面向载体10的顶部表面101的第二表面13d2。介电层13d界定从第一表面13d1面向第二表面13d2渐缩以暴露载体10的顶部表面101上的导电垫10p的开口。在一些实施例中，介电层13d可包含有机物、防焊剂、PI、环氧树脂、ABF、封装材料，或其中的两者或多于两者的组合。
导电柱13p的至少一部分安置在介电层13d的开口内且与开口的侧壁13d3接合(例如，邻接)。举例来说，导电柱13p的拐角或边缘接触开口的侧壁13d3。导电柱13p具有面向导电垫10p的表面13p1。导电柱13p的表面13p1与导电垫10p隔开距离D1。在一些实施例中，导电柱13p包含金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钛(Ti)、钨(Wu)、镍 (Ni)、其它合适金属，或其中的两者或多于两者的合金或组合。在一些实施例中，导电柱13p的表面13p1可为圆形、正方形、矩形、三角形或不等边三角形。
根据本公开的至少一些实施例，通过将导电柱13p安置到渐缩的开口中以接合到介电层13d的开口的侧壁13d3，可改进导电垫10p与导电柱13p之间的对准的准确度。另外，还可增大导电垫10p与导电柱13p之间的连接强度。
焊料层13s安置在开口内且填充由导电柱13p、导电垫10p及开口的侧壁围封的空间。举例来说，焊料层13s覆盖导电垫10p、导电柱13p的表面13p1，及导电柱13p的侧表面的在开口内的部分。在一些实施例中，焊料层13a的熔点大于电触点16的熔点。
在一些实施例中，为了确保导电柱13p可与开口的侧壁适当地接合，可满足以下不等式：
Figure BDA0001589710670000061
其中R1为导电柱13p的半径，r1为开口的底部部分(例如，邻近于介电层13d的第二表面13d2)的半径，H1为由焊料层13s覆盖的导电柱13p的厚度，且h1为导电柱13p 的表面13p1与开口的底部部分之间的距离，如图1B所展示。另外，h1可小于介电层的厚度T1，且因此可满足以下不等式：
0≤0.5×(R1-r1)tanθ1≤T1 方程式(2)，
其中θ1为由介电层13d的第二表面13d2与开口的侧壁13d3界定的锐角。因此，可通过方程式(1)及方程式(2)的组合而导出H1的条件：
Figure BDA0001589710670000062
在一些实施例中，θ1在从0度到约90度、从0度到约100度、从0度到约120度的范围内；r1在从约5微米(μm)到约50μm、从约2μm到约70μm、从约1μm到约100 μm的范围内；R1在从约10μm到约100μm、从约5μm到约200μm、从约1μm到约 500μm的范围内；T1在从约2μm到约50μm、从约1μm到约100μm、从约0.5μm到约200μm的范围内。因此，可从以上条件导出，H1可在例如从约1μm到约100μm、从约0.5μm到约200μm、从约0.1μm到约500μm的范围内。
图1C说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构13的放大图。图1C中的连接结构13'相似于图1B中的连接结构13，但图1C中的连接结构 13'进一步包含金属间化合物(IMC)层10pb、13sb、13sa及13pb除外。
IMC层10pb形成在图1B所展示的导电垫10p与焊料层13s之间的界面处且延伸到焊料层13s及导电垫10p中。举例来说，导电垫10p包含第一部分10pa及第二部分10pb。导电垫10p的第一部分10pa包含与导电垫10p相同的成分，而导电垫10p的第二部分 10pb为IMC层。在一些实施例中，导电垫10p的第二部分10pb覆盖导电垫10p的第一部分10pa。
相似地，焊料层13s包含第一部分13sa、第二部分13sb及第三部分13sc。焊料层13s的第三部分13sc包含与焊料层13s相同的成分，而焊料层13s的第一部分13sa及第二部分13sb为IMC层。
IMC层13pb形成在图1B所展示的导电柱13p与焊料层13s之间的界面处且延伸到焊料层13s及导电柱13p中。举例来说，导电柱13p包含第一部分13pa及第二部分13pb。导电柱13p的第一部分13pa包含与导电柱13p相同的成分，而导电柱13p的第二部分 13pb为IMC层。在一些实施例中，导电柱13p的第二部分13pb覆盖导电柱13p的第一部分13pa。导电柱13p的第二部分13pb与介电层13d的侧壁13d3接合。
在一些实施例中，导电柱13p与导电垫10p之间的距离D1大于厚度TH1与厚度TH2的和的一半。如图1C所展示，TH1表示形成在导电柱13p与焊料层13s之间的界面处的IMC层13pb、13sa的厚度，而TH2表示形成在导电垫10p与焊料层13s之间的界面处的IMC层10pb、13sb的厚度。举例来说，距离D1大于1/2(TH1+TH2)。
图1D说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构13的放大图。图1D中的连接结构13”相似于图1C中的连接结构13'，但图1C所展示的焊料层13s被替换为一或多个IMC层除外。
在一些实施例中，导电柱13p与导电垫10p之间的距离D1基本上等于厚度TH1'与厚度TH2'的和的一半。如图1D所展示，TH1'表示形成在导电柱13p与焊料层13s之间的界面处的IMC层的厚度，而TH2'表示形成在导电垫10p与焊料层13s之间的界面处的IMC层的厚度。换句话说，举例来说，形成在导电柱13p与焊料层13s之间的界面处的IMC层直接接触形成在导电垫10p与焊料层13s之间的界面处的IMC层。
图1E说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构13的放大图。图1E中的连接结构13”'相似于图1C中的连接结构13'，且其间的差异为：在图1C中，焊料层13s的部分在导电柱13p与介电层13d的侧壁13d3之间，而在图1E 中，导电柱13p与介电层13d的侧壁13d3之间的焊料层被替换为一或多个IMC层。
图1F说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构13的放大图。图1F中的连接结构13””相似于图1C中的连接结构13'，且其间的差异为：在图1C中，焊料层13s的部分在导电柱13p与导电垫10p之间，而在图1F中，导电柱13p 与导电垫10p之间的焊料层被替换为一或多个IMC层。
在回流工艺期间，如图1B所展示的焊料层13s可与底部裸片或衬底的导电垫10反应以形成金属间化合物(IMC)层或多个IMC层(例如IMC层10pb、13sb、13sa及13pb)。焊料层13s可包含但不限于例如SnAg。导电垫10p可包含但不限于例如Cu。IMC层可包含但不限于例如(Cu,Ni)6Sn5、(Cu,Ni)3Sn4或其组合。导电柱13p与导电垫10p之间的结合力可取决于IMC层(或多个IMC层)的数量。如果导电垫10p的厚度太小，那么整个导电垫10p可形成易遭受应力或张力的IMC层，且可在导电垫10p中发生破裂。导电柱13p与导电垫10p之间的相对厚的IMC层可由于其性质(IMC相对易碎)而减小剪切强度。此外，如果焊料层13s相对薄(例如，小于30um)，那么IMC层对焊料层13s的体积比可达到超过80％的临界条件，这也可引起接头破裂。导电柱13p与焊料层13s之间的IMC层(或多个IMC层)被控制为具有适当的厚度。导电垫10p与焊料层13s之间的 IMC层(或多个IMC层)被控制为具有适当的厚度。相对薄的IMC层可能不会提供足够的结合力。相对厚的IMC层可能易遭受破裂问题。
根据如图1C到1F所展示的实施例，导电柱13p与导电垫10p之间的距离D1可经设计以规定导电柱13p与导电垫10p之间的空间足够大以形成相对厚的IMC层(或多个 IMC层)以加强导电垫10p与导电柱13p之间的连接结构。
图1G说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构14的放大图。连接结构14包含介电层14d、焊料层14s及导电柱14p。
介电层14d安置在如图1A所展示的电子组件11a上。介电层14d具有第一表面14d1及面向电子组件11a的第二表面14d2。介电层14d界定从第一表面14d1面向第二表面 14d2渐缩以暴露电子组件11a上的导电垫11p的开口。在一些实施例中，介电层14d可包含有机物、防焊剂、PI、环氧树脂、ABF、封装材料，或其中的两者或多于两者的组合。在一些实施例中，导电垫11p的厚度小于图1B到1F所展示的导电垫10p的厚度，且大于如图1A所展示的导电垫16p的厚度。在一些实施例中，取决于导电垫的厚度而选择焊料层的熔点。
导电柱14p的至少一部分安置在介电层14d的开口内且与开口的侧壁14d3接合(例如，邻接)。举例来说，导电柱14p的拐角或边缘接触开口的侧壁14d3。导电柱14p具有面向导电垫11p的表面14p1。导电柱14p的表面14p1与导电垫11p隔开距离D2。在一些实施例中，距离D2大于如图1B到1F所展示的距离D2。在一些实施例中，导电柱 14p包含Au、Ag、Cu、Pt、Ti、Wu、Ni、其它合适金属，或其中的两者或多于两者的合金或组合。在一些实施例中，导电柱14p的表面14p1可为圆形、正方形、矩形、三角形或不等边三角形。
根据本公开的至少一些实施例，通过将导电柱14p安置到渐缩的开口中以接合到介电层14d的开口的侧壁14d3，可改进导电垫11p与导电柱14p之间的对准的准确度。另外，还可增大导电垫11p与导电柱14p之间的连接强度。
焊料层14s安置在开口内且填充由导电柱14p、导电垫11p及开口的侧壁围封的空间。举例来说，焊料层14s覆盖导电垫11p、导电柱14p的表面14p1，及导电柱14p的侧表面的在开口内的部分。在一些实施例中，焊料层14s的熔点小于图1B到1F所展示的焊料层13s的熔点且大于图1A所展示的电触点16的熔点。
图1H说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构14的放大图。图1H中的连接结构14'相似于图1G中的连接结构14，但图1H中的连接结构 14'进一步包含IMC层11pb、14sb、14sa及14pb除外。
IMC层11pb形成在图1G所展示的导电垫11p与焊料层14s之间的界面处且延伸到焊料层14s及导电垫11p中。举例来说，导电垫11p包含第一部分11pa及第二部分11pb。导电垫11p的第一部分11pa包含与导电垫11p相同的成分，而导电垫11p的第二部分 11pb为IMC层。在一些实施例中，导电垫11p的第二部分11pb覆盖导电垫11p的第一部分11pa。
相似地，焊料层14s包含第一部分14sa、第二部分14sb及第三部分14sc。焊料层14s的第三部分14sc包含与焊料层14s相同的成分，而焊料层14s的第一部分14sa及第二部分14sc为IMC层。
IMC层14pb形成在图1B所展示的导电柱14p与焊料层14s之间界面处且延伸到焊料层14s及导电柱14p中。举例来说，导电柱14p包含第一部分14pa及第二部分14pb。导电柱14p的第一部分14pa包含与导电柱14p相同的成分，而导电柱14p的第二部分 14pb为IMC层。在一些实施例中，导电柱14p的第二部分14pb覆盖导电柱14p的第一部分14pa。导电柱14p的第二部分14pb与介电层14d的侧壁14d3接合。
在一些实施例中，导电柱14p与导电垫11p之间的距离D2大于厚度TH3与厚度TH4的和的一半。如图1H所展示，TH3表示形成在导电柱14p与焊料层14s之间的界面处的IMC层14pb、14sa的厚度，而TH4表示形成在导电垫11p与焊料层14s之间的界面处的IMC层11pb、14sb的厚度。举例来说，D2大于1/2(TH3+TH4)。
图1I说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构14的放大图。图1I中的连接结构14”相似于图1H中的连接结构14'，但图1H所展示的焊料层14s被替换为一或多个IMC层除外。
在一些实施例中，导电柱14p与导电垫11p之间的距离D2基本上等于厚度TH3'与厚度TH4'的和的一半。如图1I所展示，TH3'表示形成在导电柱14p与焊料层14s之间的界面处的IMC层的厚度，而TH4'表示形成在导电垫11p与焊料层14s之间的界面处的IMC层的厚度。换句话说，举例来说，形成在导电柱14p与焊料层14s之间的界面处的IMC层直接接触形成在导电垫11p与焊料层14s之间的界面处的IMC层。
图1J说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构14的放大图。图1J中的连接结构14”'相似于图1H中的连接结构14'，且其间的差异为：在图 1H中，焊料层14s的部分在导电柱14p与介电层14d的侧壁14d3之间，而在图1J中，导电柱14p与介电层14d的侧壁14d3之间的焊料层被替换为一或多个IMC层。
图1K说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构14的放大图。图1K中的连接结构14””相似于图1H中的连接结构14'，且其间的差异为：在图1H中，焊料层14s的部分在导电柱14p与导电垫11p之间，而在图1K中，导电柱 14p与导电垫11p之间的焊料层被替换为一或多个IMC层。
根据如图1H到1K所展示的实施例，导电柱14p与导电垫11p之间的距离D2可经设计以规定导电柱14p与导电垫11p之间的空间足够大以形成相对厚的IMC层(或多个 IMC层)以加强导电垫11p与导电柱14p之间的连接结构。
图1L说明根据本公开的一些实施例的图1A的半导体封装装置1的连接结构15的放大图。连接结构15包含在载体10的顶部表面101上的导电垫10p1与电子组件11a 的导电垫11p1之间的短柱凸块15s及焊料层15b。
在一些实施例中，连接结构15安置在如图1A所展示的电子组件11a的一或多个边缘周围。返回参看图1L，短柱凸块15s的部分插入到导电垫10p1中以改进导电垫10p1 与导电垫11p1之间的对准且防止电子组件11a的侧向移动。如图1L所展示，短柱凸块 15s的宽度小于导电垫10p1的宽度。替代地，短柱凸块15s的宽度可基本上等于导电垫 10p1'的宽度(如图1M所展示)或大于导电垫10p1”的宽度(如图1N所展示)。如图1L、1M 及1N所展示，焊料层的形状可取决于短柱凸块的宽度与导电垫的宽度之间的相对差而变化。
图2说明根据本公开的一些实施例的半导体封装装置2的横截面图。半导体封装装置2相似于图1A所展示的半导体封装装置1，但电子组件21b为双面芯片或裸片且电子组件11a的表面11a1及11a2由通孔21v电连接除外。
图3说明根据本公开的一些实施例的半导体封装装置3的横截面图。半导体封装装置3包含：载体30；电子组件31a、31b；封装体32a、32b；底部填充料32u；及连接结构33、35。
载体30可为例如印刷电路板，例如纸基铜箔层压板、复合铜箔层压板、聚合物浸渍玻璃纤维基铜箔层压板，或其中的两者或多于两者的组合。载体30可包含互连结构，例如RDL。载体30界定穿透载体30的开口30h。在一些实施例中，载体30的表面301 被称作顶部表面或第一表面，且载体30的表面302被称作底部表面或第二表面。载体 30可包含在第一表面301上的多个导电垫36p1、36p3，及在第二表面302上的导电垫 36p2、36p4。电触点36安置在载体30的导电垫36p1上。在一些实施例中，电触点36 为C4凸块、BGA或LGA。
电子组件31a安置在载体30的第二表面302上且跨越载体30的开口30h。电子组件31a可为例如包含半导体衬底的芯片或裸片、一或多个集成电路装置，及其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及/或例如电阻器、电容器、电感器或其中的两者或多于两者的组合的无源装置。在一些实施例中，电子组件 31a为双面电子组件。电子组件31a的表面31a1通过例如倒装芯片技术电连接到载体30 的第二表面302且通过例如导线结合技术电连接到载体30的第一表面301。电子组件 31a的表面31a2通过例如导线结合技术电连接到载体30的第二表面302。
电子组件31b安置在载体30的第一表面301上且跨越载体30的开口30h。电子组件31b具有表面31b1及面向电子组件31a的表面31a1的表面31b2。在一些实施例中，电子组件31b为双面电子组件。电子组件31b的表面31b2通过例如倒装芯片技术(例如，通过连接结构35)电连接到载体30的第一表面301，而电子组件31b的表面31b1通过例如导线结合技术电连接到载体30的第一表面301。在一些实施例中，连接结构35与图 1L所展示的连接结构15相同或相似。在一些实施例中，电子组件31b的表面31b2通过导电柱33p(其穿过载体30的开口30h)及连接结构33电连接到电子组件31a的表面 31a1。在一些实施例中，连接结构33与图1B到1F所展示的连接结构13、13'、13”、 13”'及13””中的任一者相同或相似。替代地，连接结构33可为任何合适连接结构。
电子组件31b可为例如包含半导体衬底的芯片或裸片、一或多个集成电路装置，及其中的一或多个上覆互连结构。集成电路装置可包含例如晶体管的有源装置，及/或例如电阻器、电容器、电感器或其中的两者或多于两者的组合的无源装置。
底部填充料32u可安置在电子组件31a及31b之间以覆盖电子组件31a的表面31a1、电子组件31b的表面31b2，及载体30的第一表面301及第二表面302的至少一部分。在一些实施例中，底部填充料32u包含环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、包含分散于其中的硅酮的材料，或其中的两者或多于两者的组合。在一些实施例中，取决于不同实施例，底部填充料32u可为CUF 或MUF。
封装体32a覆盖电子组件31b的表面31b1、载体30的第一表面301的部分，及底部填充料32u的部分。封装体32b覆盖电子组件31a的表面31a2、载体30的第二表面 302的部分，及底部填充料32u的部分。在一些实施例中，封装体32a、32b包含例如有机材料(例如，封装材料、BT、PI、PBO、ABF、PP、环氧基材料，或其中的两者或多于两者的组合)、无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两者或多于两者的组合)、液体及/或干膜材料，或其中的两者或多于两者的组合。
图4A、4B、4C、4D、4E、4F及4G为根据本公开的一些实施例的在各种阶段制作的半导体结构的横截面图。各种图已被简化以更佳地理解本公开的方面。
参看图4A，提供电子组件41a(例如，芯片、裸片或晶片)。电子组件41a为双面的，且具有表面41a1及与表面41a1相对的表面41a2。电子组件41a具有在其表面41a1上的多个导电垫41p1及在其表面41a2上的导电垫41p2。
在电子组件41a的表面41a1上形成钝化层49a(或介电层)以覆盖电子组件41a的表面41a1上的导电垫41p1。
参看图4B，将图4A所展示的结构翻转，且在电子组件41a的表面41a2上的导电垫41p2的部分上形成短柱凸块45s。在一些实施例中，短柱凸块45s为熔融结合线。
参看图4C，在电子组件41a的表面41a2上形成光阻49b(或掩模)以覆盖导电垫41p2及短柱凸块45s。将结构翻转，且在钝化层49a上形成多个开口49ah以暴露电子组件41a 的表面41a1上的导电垫41p1的部分。在一些实施例中，开口49ah可通过例如光刻技术而形成。
参看图4D，将图4C所展示的结构翻转，且在光阻49b上形成开口以暴露短柱凸块45s。通过例如电镀或无电镀将焊料层45b形成在开口内以接触短柱凸块45s。
参看图4E，在光阻49b上形成光阻49c以覆盖短柱凸块45s及焊料层45b。在光阻49b上形成多个开口49ch以暴露电子组件41a的表面41a2上的导电垫41p2的部分。通过例如电镀、无电镀、溅射、膏印刷、凸块化或结合工艺而在开口49ch内形成导电材料来形成导电柱43p。在一些实施例中，开口49ch可能未被导电材料完全地填充。举例来说，导电柱43p的顶部表面可低于钝化层49c的表面49c1。
参看图4F，在开口49ch的剩余部分内形成焊料层43s以接触导电柱43p。在一些实施例中，焊料层43s是通过例如电镀或无电镀而形成。
参看图4G，从电子组件41a的表面41a2移除光阻49b及49c以暴露导电垫41p1、短柱凸块45s、导电柱43及焊料层43s的部分。
图5A、5B、5C及5D为根据本公开的一些实施例的在各种阶段制作的半导体结构的横截面图。各种图已被简化以更佳地理解本公开的方面。
参看图5A，提供载体50。载体50具有第一表面501及与第一表面501相对的第二表面502。载体50具有在其第一表面501上的导电垫50p1及在其第二表面502上的导电垫50p2。
在载体50的第一表面501上形成钝化层50d以覆盖载体50的第一表面501上的导电垫50p1。形成多个开口以暴露载体50的第一表面501上的导电垫50p1的部分。在一些实施例中，开口可通过例如光刻技术而形成。
参看图5B，将电子组件51a(裸片或芯片)放置在载体50的第一表面501上。电子组件51a为双面的，且具有第一表面51a1及面向载体50的第二表面51a2。在一些实施例中，电子组件51a及其连接结构可通过图4A到4G所展示的操作而形成，且因此电子组件51a的第二表面51a2上的导电柱电连接到载体50的第一表面501上的导电垫50p1。电子组件51a的第一表面51a1通过导线结合技术电连接到载体50。
在一些实施例中，可将底部填充料51u1形成在电子组件51a与载体50之间以覆盖电子组件51a的第二表面51a2。在一些实施例中，底部填充料51u1包含环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、包含分散于其中的硅酮的材料，或其中的两者或多于两者的组合。在一些实施例中，取决于不同实施例，底部填充料51u1可为CUF或MUF。
参看图5C，将电子组件51b(裸片或芯片)放置在电子组件51a的第一表面51a1上。电子组件51b为双面的，且具有第一表面51b1及面向电子组件51a的第二表面51b2。在一些实施例中，电子组件51b及其连接结构可通过图4A到4G所展示的操作而形成，且因此电子组件51b的第二表面51b2上的导电柱电连接到电子组件51a的第一表面51a1 上的导电垫。电子组件51b的第一表面51b1通过导线结合技术电连接到载体50。
在一些实施例中，可将底部填充料51u2形成在电子组件51a及51b之间以覆盖电子组件51a的第一表面51a1及电子组件51b的第二表面51b2。在一些实施例中，底部填充料51u2包含环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、包含分散于其中的硅酮的材料，或其中的两者或多于两者的组合。在一些实施例中，取决于不同实施例，底部填充料51u2可为CUF或MUF。
参看图5D，将封装体52形成在载体50的第一表面501上以覆盖电子组件51a、51b及底部填充料51u1、51u2。在一些实施例中，封装体52包含例如有机材料(例如，封装材料、BT、PI、PBO、阻焊剂、ABF、PP、环氧基材料，或其中的两者或多于两者的组合)、无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两者或多于两者的组合)、液体及/或干膜材料，或其中的两者或多于两者的组合。封装体52可通过例如转送成型或压缩成型的成型技术而形成。
在形成封装体52之后，将装置翻转，且在载体50的第二表面502上的导电垫50p2上形成电触点56。在一些实施例中，电触点56为C4凸块、BGA或LGA。在一些实施例中，电触点56可通过电镀、无电镀、溅射、膏印刷、凸块化或结合工艺而形成。在一些实施例中，图5D所展示的半导体封装装置5相似于图1A所展示的半导体封装装置1，但半导体封装装置1的电子组件11b为单面的，而半导体封装装置5的电子组件 51b为双面的除外。
在一些实施例中，如图5B及5C所展示，电子组件51a连接到载体50且电子组件 51b连接到电子组件51a。在电子组件51a连接到载体50时，执行回流工艺。在电子组件51b连接到电子组件51a时，执行另一回流工艺。换句话说，电子组件51a与载体50 之间的连接结构(相似于图1B到1F所展示的连接结构13)的焊料层可经受回流工艺达两次。为了避免载体50的翘曲及电子组件51a的导电柱与载体50上的导电垫之间的未对准，电子组件51a与载体50之间的焊料层的熔点可高于电子组件51b与电子组件51a 之间的焊料层(相似于图1G到1K所展示的连接结构14)的熔点或电触点56的熔点。因此，电子组件51a的导电柱与载体50的导电垫之间的距离(例如，图1B到1F所展示的 D1)大于电子组件51b的导电柱与电子组件51a的导电垫之间的距离(例如，图1G到1K 所展示的D2)。
另外，由于电子组件51a与载体50之间的连接结构(相似于图1B到1F所展示的连接结构13)的焊料层可经受回流工艺达两次，故载体50上的导电垫的厚度可大于电子组件51a上的导电垫的厚度或被安置电触点56的导电垫的厚度，以避免载体50上的导电垫完全地转化成IMC。
在一些实施例中，电子组件51b可首先连接到电子组件51a，且电子组件51a连同电子组件51b一起连接到载体50。在电子组件51b连接到电子组件51a时，执行回流工艺。在电子组件51a、51b连接到载体50时，执行另一回流工艺。换句话说，电子组件 51a与电子组件51b之间的连接结构(相似于图1G到1K所展示的连接结构14)的焊料层可经受回流工艺达两次。为了避免电子组件51a或51b的翘曲及电子组件51b的导电柱与电子组件51a上的导电垫之间的未对准，电子组件51a与电子组件51b之间的焊料层的熔点可高于电子组件51a与载体50之间的焊料层(相似于图1B到1F所展示的连接结构13)的熔点或电触点56的熔点。因此，电子组件51b的导电柱与电子组件51a的导电垫之间的距离(例如，图1G到1K所展示的D2)大于电子组件51b的导电柱与载体50上的导电垫之间的距离(例如，图1B到1F所展示的D1)。
另外，由于电子组件51a与电子组件51b之间的连接结构(相似于图1G到1K所展示的连接结构14)的焊料层可经受回流工艺达两次，故电子组件51a上的导电垫的厚度可大于载体50上的导电垫的厚度或被安置电触点56的导电垫的厚度，以避免电子组件 51a上的导电垫完全地转化成IMC。
图6A、6B、6C、6D及6E为根据本公开的一些实施例的在各种阶段制作的半导体结构的横截面图。各种图已被简化以更佳地理解本公开的方面。
参看图6A，提供衬底60。载体60界定穿透载体60的开口60h。在一些实施例中，开口60h可通过机械钻孔、激光钻孔或其它合适工艺而形成。载体60具有第一表面601 及与第一表面601相对的第二表面602。载体60可包含在其第一表面601及第二表面 602上的多个导电垫。
将电子组件61a(裸片或芯片)放置在载体60的第二表面02上且跨越开口60h。在一些实施例中，电子组件61a为双面电子组件。电子组件61a具有面向载体60的第一表面60a1及与第一表面60a1相对的第二表面60a2。电子组件61a的第一表面61a1通过例如倒装芯片技术电连接到载体60的第二表面602，而电子组件61a的第二表面61a2 通过例如导线结合技术电连接到载体60的第二表面602。
参看图6B，在载体60的第二表面602上形成封装体62b以覆盖电子组件61a的第二表面61a2且暴露电子组件61a的第一表面61a1。在一些实施例中，封装体62b包含例如有机材料(例如，封装材料、BT、PI、PBO、阻焊剂、ABF、PP、环氧基材料，或其中的两者或多于两者的组合)、无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两者或多于两者的组合)、液体及/或干膜材料，或其中的两者或多于两者的组合。封装体 62b可通过例如转送成型或压缩成型的成型技术而形成。
参看图6C，将图6B所展示的结构翻转，且通过导线结合技术将电子组件61a的第一表面60a1电连接到载体60的第一表面601。
将电子组件61b放置在载体60的第一表面601上且跨越开口60h。电子组件61b为双面的，且具有第一表面61b1及面向电子组件61a的第二表面61b2。在一些实施例中，电子组件61b及其连接结构可通过图4A到4G所展示的操作而形成。电子组件61b的第二表面61b2上的导电柱63p穿过开口60h且电连接到电子组件61a的第一表面61a1 上的导电垫。
参看图6D，将底部填充料62u形成在电子组件61a及61b之间以覆盖电子组件61a的第一表面61a1及电子组件61b的第二表面61b2。在一些实施例中，底部填充料62u 包含环氧树脂、封装材料(例如，环氧封装材料或其它封装材料)、聚酰亚胺、酚类化合物或材料、包含分散于其中的硅酮的材料，或其中的两者或多于两者的组合。在一些实施例中，取决于不同实施例，底部填充料62u可为CUF或MUF。电子组件61b的第一表面61b1通过导线结合技术电连接到载体50。
参看图6D，将封装体62a形成在载体60的第一表面601上以覆盖电子组件61b的第一表面61b1。在一些实施例中，封装体62a包含例如有机材料(例如，封装材料、BT、 PI、PBO、阻焊剂、ABF、PP、环氧基材料，或其中的两者或多于两者的组合)、无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两者或多于两者的组合)、液体及/或干膜材料，或其中的两者或多于两者的组合。封装体62a可通过例如转送成型或压缩成型的成型技术而形成。
将电触点66形成在载体60的第一表面601上的导电垫上。在一些实施例中，电触点66为C4凸块、BGA或LGA。在一些实施例中，电触点66可通过电镀、无电镀、溅射、膏印刷、凸块化或结合工艺而形成。在一些实施例中，图6E所展示的半导体封装装置6与图3所展示的半导体封装装置3相同。
在一些实施例中，如图6A到6E所展示，电子组件61a连接到载体60的第二表面 602且电子组件61b连接到载体60的第一表面601。在电子组件61a连接到载体60时，执行回流工艺。在电子组件61b连接到载体60时，执行另一回流工艺。换句话说，电子组件61a与载体60之间的连接结构(相似于图1B到1F所展示的连接结构13)的焊料层可经受回流工艺达两次。因此，载体60的第二表面602上的导电垫的厚度可大于电子组件61a上的导电垫的厚度或被安置电触点66的导电垫的厚度，以避免载体60的第二表面602上的导电垫完全地转化成IMC。
图7A及7B说明根据本公开的一些实施例的各种类型的半导体封装装置。
如图7A所展示，多个芯片70或裸片放置在正方形载体71上。在一些实施例中，载体71可包含有机材料(例如，封装材料、BT、PI、PBO、阻焊剂、ABF、PP、环氧基材料，或其中的两者或多于两者的组合)，或无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两者或多于两者的组合)，或其中的两者或多于两者的组合。
如图7B所展示，多个芯片70或裸片放置在圆形载体72上。在一些实施例中，载体72可包含有机材料(例如，封装材料、BT、PI、PBO、阻焊剂、ABF、PP、环氧基材料，或其中的两者或多于两者的组合)，或无机材料(例如，硅、玻璃、陶瓷、石英，或其中的两者或多于两者的组合)，或其中的两者或多于两者的组合。
如本文中所使用，术语“大约”、“基本上”、“基本”及“约”用于描述及考虑小变化。在结合事件或情境而使用时，所述术语可指所述事件或情境精确地发生的实例以及所述事件或情境相当近似地发生的实例。举例来说，在结合数值而使用时，所述术语可指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％，那么所述值可被认为“基本上”或“约”相同。
如本文中所使用，术语“导电”、“导电性”及“导电率”是指输送电流的能力。导电性材料通常指示对电流流动几乎不展现对抗的那些材料。导电率的一个度量为西门子/米(S/m)。通常，导电性材料为具有大于大约104S/m的导电率的材料，例如至少105S/m 或至少106S/m。材料的导电率有时可随着温度而变化。除非另有指定，否则材料的导电率是在室温下进行测量。
如本文中所使用，除非上下文另有明确规定，否则单数术语“一(a/an)”及“所述”可包含复数指示物。在一些实施例的描述中，一组件提供在另一组件“上”或“上方”可涵盖前一组件直接在后一组件上(例如，物理接触)的状况，以及一或多个介入组件位于前一组件与后一组件之间的状况。
虽然已参考本公开的特定实施例来描述及说明本公开，但这些描述及说明并不限制本公开。所属领域的技术人员可清楚地理解，在不脱离如由所附权利要求书所界定的本公开的真实精神及范围的情况下，可进行各种改变且可在实施例内取代等效组件。绘示可能未必按比例绘制。由于制造工艺中的变量等等，本公开中的精巧呈现与实际设备之间可存在差别。本公开可存在未具体地说明的其它实施例。本说明书及图式应被视为说明性的而非限定性的。可进行修改以使特定情形、材料、物质成分、方法或工艺适应于本公开的目标、精神及范围。所有此类修改意欲属于所附权利要求书的范围内。虽然已参考以特定次序而执行的特定操作来描述本文中所公开的方法，但可理解，在不脱离本公开的教示的情况下，可将这些操作组合、细分或重新排序以形成等效方法。因此，除非本文中有特定指示，否则操作的次序及分组并不限制本公开。

Claims (28)

1.一种半导体封装装置，其包括：
第一介电层，其具有第一表面及与所述第一表面相对的第二表面，所述第一介电层界定从所述第一表面朝向所述第二表面渐缩的第一开口；
第一导电垫，其在所述第一开口内且邻近于所述第一介电层的所述第二表面；
第一导电元件，其中所述第一导电元件的至少一部分安置在所述第一开口内，且所述第一导电元件与所述第一开口的侧壁接合，所述第一导电元件具有面向所述第一导电垫的第一表面，其中所述第一导电元件的所述第一表面与所述第一导电垫隔开。
2.根据权利要求1所述的半导体封装装置，其中
所述导电元件进一步包含第一部分及第二部分；
所述导电元件的所述第二部分与所述第一开口的所述侧壁接合；且
所述第一导电元件的所述第一部分及所述第二部分包括不同材料。
3.根据权利要求2所述的半导体封装装置，其中
所述第一导电垫包括第一部分及覆盖所述第一部分的第二部分；且
所述第一导电垫的所述第一部分及所述第二部分包括不同材料。
4.根据权利要求3所述的半导体封装装置，其进一步包括在所述第一导电元件与所述第一导电垫之间的第一焊料层，其中所述第一焊料层包括邻近于所述第一导电元件的所述第二部分的第一部分、邻近于所述第一导电垫的所述第二部分的第二部分，及第三部分。
5.根据权利要求4所述的半导体封装装置，其中
所述第一焊料层的所述第一部分及所述第一导电元件的所述第二部分形成第一金属间化合物IMC层；
所述第一焊料层的所述第二部分及所述第一导电垫的所述第二部分形成第二IMC层；且
所述第一导电元件的所述第一表面与所述第一导电垫之间的距离大于所述第一金属间化合物IMC层的厚度与所述第二IMC层的厚度的和的一半。
6.根据权利要求5所述的半导体封装装置，其中所述第一金属间化合物IMC层接触所述第二IMC层。
7.根据权利要求4所述的半导体封装装置，其进一步包括：
载体，其具有第一表面，所述第一介电层及所述第一导电垫安置在所述第一表面上，其中所述第一介电层的所述第二表面面向所述载体；及
第一电子组件，其在所述第一介电层上，所述第一电子组件具有面向所述第一介电层的第一表面及与所述第一表面相对的第二表面，其中所述第一电子组件的所述第一表面电连接到所述第一导电元件。
8.根据权利要求7所述的半导体封装装置，其进一步包括：
第二导电垫，其在所述第一电子组件的所述第二表面上；
第二介电层，其在所述第一电子组件的所述第二表面上，所述第二介电层界定朝向所述第一电子组件的所述第二表面渐缩以暴露所述第二导电垫的第二开口；及
第二导电元件，其中所述第二导电元件的至少一部分在所述第二开口内，且所述第二导电元件与所述第二开口的侧壁接合，所述第二导电元件具有面向所述第二导电垫的第一表面。
9.根据权利要求8所述的半导体封装装置，其中所述第一导电元件的所述第一表面与所述第一导电垫之间的距离小于所述第二导电元件的所述第一表面与所述第二导电垫之间的距离。
10.根据权利要求8所述的半导体封装装置，其中所述第一导电垫的厚度大于所述第二导电垫的厚度。
11.根据权利要求10所述的半导体封装装置，其进一步包括在所述载体的与所述第一表面相对的第二表面上的第三导电垫，其中所述第三导电垫的厚度小于所述第一导电垫的所述厚度或所述第二导电垫的所述厚度。
12.根据权利要求8所述的半导体封装装置，其中
所述第二导电元件包括第一部分及由不同材料形成的第二部分；
所述第二导电元件的所述第二部分与所述第二开口的所述侧壁接合；且
所述第二导电垫包括由不同材料形成的第一部分及覆盖所述第一部分的第二部分。
13.根据权利要求12所述的半导体封装装置，其进一步包括在所述第二导电元件与所述第二导电垫之间的第二焊料层，其中所述第二焊料层包括邻近于所述第二导电元件的所述第二部分的第一部分、邻近于所述第二导电垫的所述第二部分的第二部分，及第三部分。
14.根据权利要求13所述的半导体封装装置，其中
所述第二焊料层的所述第一部分及所述第二导电元件的所述第二部分形成第三IMC层；
所述第二焊料层的所述第二部分及所述第二导电垫的所述第二部分形成第四IMC层；且
所述第二导电元件的所述第一表面与所述第二导电垫之间的距离大于所述第三IMC层的厚度与所述第四IMC层的厚度的和的一半。
15.根据权利要求13所述的半导体封装装置，其中所述第一焊料层的熔点大于所述第二焊料层的熔点。
16.根据权利要求15所述的半导体封装装置，其进一步包括在所述载体的与所述第一表面相对的第二表面上的第三焊料层，其中所述第三焊料层的熔点小于所述第一焊料层或所述第二焊料层的所述熔点。
17.根据权利要求8所述的半导体封装装置，其进一步包括在所述第二介电层上的第二电子组件，所述第二电子组件具有面向所述第二介电层的第一表面，其中所述第二电子组件的所述第一表面电连接到所述第二导电元件。
18.根据权利要求4所述的半导体封装装置，其进一步包括第三电子组件，所述第三电子组件具有第一表面及与所述第一表面相对的第二表面，其中所述第一介电层及所述第一导电垫在所述第三电子组件的所述第一表面上且所述第一介电层的所述第二表面面向所述第三电子组件的所述第一表面。
19.根据权利要求18所述的半导体封装装置，其中
所述第一焊料层的所述第一部分及所述第一导电元件的所述第二部分形成第五IMC层；
所述第一焊料层的所述第二部分及所述第一导电垫的所述第二部分形成第六IMC层；且
所述第一导电元件的所述第一表面与所述第一导电垫之间的距离大于所述第五IMC层的厚度与所述第六IMC层的厚度的和的一半。
20.根据权利要求18所述的半导体封装装置，其进一步包括在所述第三电子组件上方的第四电子组件，所述第四电子组件具有面向所述第三电子组件的第一表面，其中所述第四电子组件的所述第一表面电连接到所述第一导电元件。
21.根据权利要求20所述的半导体封装装置，其进一步包括在所述第三电子组件与所述第四电子组件之间的衬底，所述衬底具有面向所述第四电子组件的所述第一表面的第一表面及面向所述第三电子组件的所述第一表面的第二表面。
22.根据权利要求21所述的半导体封装装置，其中所述衬底包括在所述衬底的所述第二表面上的导电垫，且所述衬底的所述第二表面上的所述导电垫的厚度大于所述第一导电垫的厚度。
23.根据权利要求22所述的半导体封装装置，其中所述衬底包括在所述衬底的所述第一表面上的导电垫，且所述衬底的所述第一表面上的所述导电垫的厚度小于所述衬底的所述第二表面上的所述导电垫的所述厚度或所述第一导电垫的所述厚度。
24.根据权利要求21所述的半导体封装装置，其进一步包括第一导电线及第二导电线，其中所述衬底的所述第一表面由所述第一导电线电连接到与所述第四电子组件的所述第一表面相对的第二表面，且所述衬底的所述第二表面由所述第二导电线电连接到与所述第三电子组件的所述第一表面相对的第二表面。
25.根据权利要求1所述的半导体封装装置，其中所述第一导电元件的所述第一表面与所述导电垫之间的距离(D1)是根据以下方程式：
Figure FDA0002301755130000051
其中R1为所述第一导电元件的半径，r1为所述第一开口的底部部分的半径，且θ1为由所述第一开口的所述侧壁与所述第一介电层的所述第二表面界定的角度。
26.一种半导体封装装置，其包括：
介电层，其具有第一表面及与所述第一表面相对的第二表面，所述介电层界定从所述第一表面朝向所述第二表面渐缩的开口；
导电垫，其在所述开口内且邻近于所述介电层的所述第二表面；
导电柱，其中所述导电柱的至少一部分在所述开口内，且所述导电柱具有面向所述导电垫的第一表面；
第一金属间化合物IMC层，其在所述导电柱的所述第一表面上且从所述导电柱的所述第一表面延伸到所述导电柱中，其中所述第一金属间化合物IMC层与所述开口的侧壁接合；以及
第二IMC层，所述第二IMC层在所述导电垫上且延伸到所述导电垫中，
其中所述导电柱的所述第一表面与所述导电垫之间的距离大于所述第一金属间化合物IMC层的厚度与所述第二IMC层的厚度的和的一半。
27.根据权利要求26所述的半导体封装装置，其进一步包括在所述第一金属间化合物IMC层与所述第二IMC层之间的焊料层。
28.根据权利要求26所述的半导体封装装置，其中所述第一金属间化合物IMC层接触所述第二IMC层。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087597A (en) * 1994-07-22 2000-07-11 Nec Corporation Connecting member and a connecting method with ball and tapered via
CN102456650A (zh) * 2010-10-21 2012-05-16 台湾积体电路制造股份有限公司 半导体基板的导电结构以及其制造方法
CN103745965A (zh) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 封装结构
CN104051384A (zh) * 2013-03-13 2014-09-17 台湾积体电路制造股份有限公司 半导体器件的封装方法和装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6517359B1 (en) * 1999-05-21 2003-02-11 Agilent Technologies, Inc. System and method for mating electrical connections
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US7652374B2 (en) * 2006-07-31 2010-01-26 Chi Wah Kok Substrate and process for semiconductor flip chip package
US8076177B2 (en) 2010-05-14 2011-12-13 International Business Machines Corporation Scalable transfer-join bonding lock-and-key structures
US9496238B2 (en) * 2015-02-13 2016-11-15 Advanced Semiconductor Engineering, Inc. Sloped bonding structure for semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087597A (en) * 1994-07-22 2000-07-11 Nec Corporation Connecting member and a connecting method with ball and tapered via
CN102456650A (zh) * 2010-10-21 2012-05-16 台湾积体电路制造股份有限公司 半导体基板的导电结构以及其制造方法
CN104051384A (zh) * 2013-03-13 2014-09-17 台湾积体电路制造股份有限公司 半导体器件的封装方法和装置
CN103745965A (zh) * 2013-12-05 2014-04-23 南通富士通微电子股份有限公司 封装结构

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