TW202125754A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
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- TW202125754A TW202125754A TW109141570A TW109141570A TW202125754A TW 202125754 A TW202125754 A TW 202125754A TW 109141570 A TW109141570 A TW 109141570A TW 109141570 A TW109141570 A TW 109141570A TW 202125754 A TW202125754 A TW 202125754A
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Abstract
一種半導體封裝包括:重佈線基板,包括第一重佈線層;第一模製構件,位於重佈線基板上;第二重佈線層,位於第一模製構件的上表面上且具有重佈線接墊;電性連接接墊,位於第二模製構件的上表面上且電性連接至第二重佈線層;以及鈍化層,位於第二模製構件上且具有暴露出電性連接接墊的至少一部分的開口。電性連接接墊包括包含第一金屬的導體層及位於導體層上且包含第二金屬的接觸層。重佈線接墊包含與第一金屬及第二金屬不同的第三金屬。由開口暴露出的電性連接接墊的所述部分所具有的寬度大於重佈線接墊的寬度。
Description
本揭露大體而言是有關於半導體封裝,且更具體而言有關於包括用於進行電性連接的重佈線層的半導體封裝。
儘管可能需要半導體裝置來處理高容量資料,然而半導體裝置的體積已逐漸減小。因此,在包括彼此耦合的不同半導體晶片的層疊封裝(package-on-package,POP)配置中,設置於下部封裝的背側上的電性連接接墊的數目及將電性連接接墊電性連接至第一重佈線層RDL的背側互連線的數目已增加。然而,由於電性連接接墊需要具有擁有標準大小的面積,因此可能難以將所述面積減小至預定大小或小於預定大小,且在減小背側互連線的寬度及空間方面可能存在技術限制。
示例性實施例提供一種藉由使用第二重佈線層而具有改善的積體密度及可靠性的半導體封裝。
根據示例性實施例,一種半導體封裝包括:重佈線基板,包括第一重佈線層;半導體晶片,位於所述重佈線基板上,且電性連接至所述第一重佈線層;第一模製構件,位於所述重佈線基板及所述半導體晶片上;第二重佈線層,位於所述第一模製構件上且具有重佈線接墊;垂直連接結構,位於所述重佈線基板與所述第二重佈線層之間,且將所述第一重佈線層與所述第二重佈線層彼此電性連接;第二模製構件,位於所述第一模製構件以及所述第二重佈線層的至少一部分上;電性連接接墊,位於所述第二模製構件的最上表面上,且電性連接至所述第二重佈線層;以及鈍化層,位於所述第二模製構件上且具有暴露出所述電性連接接墊的至少一部分的開口。所述電性連接接墊包括包含第一金屬的導體層及位於所述導體層上且包含第二金屬的接觸層。所述重佈線接墊包含與所述第一金屬及所述第二金屬不同的第三金屬。由所述開口暴露出的所述電性連接接墊的所述部分所具有的寬度大於所述重佈線接墊的寬度。
根據示例性實施例,一種半導體封裝包括:重佈線基板,包括第一重佈線層;半導體晶片,位於所述重佈線基板上;第一模製構件,位於所述重佈線基板及所述半導體晶片上;第二重佈線層,位於所述第一模製構件上且包括重佈線接墊;垂直連接結構,位於所述重佈線基板上,且將所述第一重佈線層與所述第二重佈線層彼此電性連接;第二模製構件,位於所述第一模製構件上且覆蓋所述第二重佈線層的至少一部分;以及電性連接結構,位於所述第二模製構件上,且電性連接至所述重佈線接墊。所述電性連接結構包括包含鎳(Ni)的導體層及位於所述導體層的上表面上且包含金(Au)的接觸層。所述重佈線接墊包含銅(Cu)。
根據示例性實施例,一種半導體封裝包括:重佈線基板,包括第一重佈線層;半導體晶片,位於所述重佈線基板上,且電性連接至所述第一重佈線層;第一模製構件,位於所述重佈線基板及所述半導體晶片上;多個垂直連接結構,嵌置於所述第一模製構件中且電性連接至所述第一重佈線層;第二模製構件,包括位於所述第一模製構件的上表面上的基礎模製層及位於所述基礎模製層的上表面上的增層模製層;第二重佈線層,位於所述基礎模製層的所述上表面上,且包括多個重佈線接墊及多個重佈線圖案,所述多個重佈線圖案將所述多個重佈線接墊與所述多個垂直連接結構彼此電性連接;以及多個電性連接結構,位於所述第二模製構件上,且具有自所述增層模製層的所述上表面突出的接墊部分及穿過所述增層模製層與所述多個重佈線接墊中的至少一者物理接觸的通孔部分。所述多個電性連接結構包括包含鎳(Ni)的導體層及位於所述導體層的上表面上且包含金(Au)的接觸層。所述多個重佈線接墊包括彼此相鄰的第一背側重佈線接墊與第二背側重佈線接墊。所述多個電性連接結構包括與所述第一背側重佈線接墊及所述第二背側重佈線接墊分別對應的第一背側電性連接結構及第二背側電性連接結構。所述多個重佈線圖案在所述第一背側重佈線接墊與所述第二背側重佈線接墊之間延伸,且在所述半導體封裝的其中所述重佈線基板充當基礎參考平面的剖視圖中,所述多個重佈線圖案的至少一部分與所述第一背側電性連接結構及所述第二背側電性連接結構中的至少一者垂直重疊。
在下文中,將參照附圖詳細闡述本發明概念的實施例。在圖式中,相同的參考編號用於相同的元件,且將不再對其予以贅述。本文中所使用的用語「及/或」包括相關聯列出項中的一或多個項的任意及所有組合。應理解,當一元件被稱為「位於」另一元件「上」、「附接」至另一元件、「連接」至另一元件、與另一元件「耦合」、「接觸」另一元件等等時,所述元件可直接位於所述另一元件上、附接至所述另一元件、連接至所述另一元件、與所述另一元件耦合或接觸所述另一元件,或者亦可存在中間元件。相反,當一元件被稱為例如「直接位於」另一元件「上」、「直接附接」至另一元件、「直接連接」至另一元件、與另一元件「直接耦合」或「直接接觸」另一元件時,則不存在中間元件。應注意,儘管未關於不同的實施例進行具體闡述,然而關於一個實施例闡述的態樣可併入不同的實施例中。即,所有實施例及/或任何實施例的特徵可以任何方式及/或組合來加以組合。
圖1是根據本發明概念一些示例性實施例的半導體封裝100A的剖視圖,且圖2是示出與圖1所示半導體封裝100A中的區「A」對應的元件的示意性平面圖。圖2示出當自上方(即,平面圖)觀察圖1所示半導體封裝100A時與區「A」對應的元件。
參照圖1及圖2,半導體封裝100A可包括垂直連接結構110、半導體晶片120、第一模製構件130a、第二模製構件130b、具有重佈線接墊132P的第二重佈線層132、具有第一重佈線層142的重佈線基板140、具有電性連接接墊182及電性連接通孔183的電性連接結構185、以及位於電性連接結構185上且至少部分地覆蓋電性連接結構185的一部分的第二鈍化層181。
在示例性實施例中,半導體封裝100A可更包括設置於重佈線基板140上以保護第一重佈線層142的第一鈍化層150、穿透第一鈍化層150的凸塊下金屬160以及連接至凸塊下金屬160的連接凸塊170。
垂直連接結構110可為設置於重佈線基板140的表面(例如,圖1中的重佈線基板的上表面)上且穿過第一模製構件130a的至少一部分將第一重佈線層142與第二重佈線層132彼此電性連接的導電支柱。垂直連接結構110可包括圍繞半導體晶片120設置的多個垂直連接結構110。垂直連接結構110可形成穿透第一模製構件130a的電性路徑。導電支柱可包含導電材料。導電支柱可利用導電材料完全填充,且可具有例如圓柱形形狀或多邊形柱狀形狀。導電支柱的形狀不必受到限制;因此,導電支柱可具有各種形狀。在圖1中,垂直連接結構110藉由背側通孔133連接至第二重佈線層132。然而,與圖1中所示者不同,當垂直連接結構110的上表面藉由例如化學機械磨光(chemical mechanical polishing,CMP)製程等平坦化製程而設置成與第一模製構件130a的上表面共面(參見圖12)時,垂直連接結構110可直接連接至第二重佈線層132。
半導體晶片120可具有上面設置有連接電極120P的主動表面以及與主動表面相對的非主動表面。半導體晶片120可為邏輯晶片或記憶體晶片。舉例而言,半導體晶片120可包括系統大型積體(large scale integration,LSI)、邏輯電路、互補金屬氧化物半導體(complementary metal oxide semiconductor,CMOS)成像感測器(CMOS imaging sensor,CIS)、例如動態隨機存取記憶體(dynamic random access memory,DRAM)、靜態隨機存取記憶體(static random access memory,SRAM)、快閃記憶體、相變隨機存取記憶體(phase-change random access memory,PRAM)、電阻式隨機存取記憶體(resistive random access memory ReRAM)、鐵電式隨機存取記憶體(ferroelectric random access memory,FeRAM)、磁性隨機存取記憶體(magnetic random access memory,MRAM)、高頻寬記憶體(high bandwidth memory,HBM)、混合記憶體立方(hybrid memory cubic,HMC)、微機電系統(microelectromechanical system,MEMS)裝置等記憶體裝置、或者類似物。
連接電極120P與第一重佈線層142之間可設置有附加的連接構件。連接構件可包括焊球或銅柱。舉例而言,半導體晶片120可以倒裝晶片結合方式安裝於重佈線基板140上。在此種實施例中,半導體晶片120與重佈線基板140之間可形成有底部填充樹脂,以與連接構件交接及/或至少部分地環繞連接構件。
第一模製構件130a可設置於重佈線基板140上,且可位於半導體晶片120上且至少部分地覆蓋半導體晶片120。第一模製構件130a可包含絕緣材料,且所述絕緣材料可為包括無機填料及絕緣樹脂的材料,所述絕緣樹脂為例如:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺;或者其中在熱固性樹脂或熱塑性樹脂中包含例如無機填料等加強體的樹脂,詳言之,味之素增層膜(Ajinomoto build-up film,ABF)、弗朗克功能調節劑4(Frankel’s functional regulator-4,FR-4)樹脂、雙馬來醯亞胺三嗪(bismaleimide triazine,BT)樹脂、樹脂或類似物。另外,絕緣材料可為環氧模製化合物(epoxy molding compound,EMC)、感光成像包封劑(photoimageable encapsulant,PIE)或類似物。
第二模製構件130b可為設置於半導體封裝100A的背側及靠近上面未設置半導體晶片120的連接電極120P的表面(非主動表面)的一側上的絕緣層。第二模製構件130b可位於第二重佈線層132上且至少部分地覆蓋第二重佈線層132的一部分。第二模製構件130b可包含絕緣材料,且所述絕緣材料可為包括無機填料及絕緣樹脂的材料,所述絕緣樹脂為例如:熱固性樹脂,例如環氧樹脂;熱塑性樹脂,例如聚醯亞胺;或者其中在熱固性樹脂或熱塑性樹脂中包含例如無機填料等加強體的樹脂,詳言之,味之素增層膜(ABF)、FR-4樹脂、雙馬來醯亞胺三嗪(BT)樹脂、樹脂或類似物。另外,絕緣材料可為環氧模製化合物(EMC)、感光成像包封劑(PIE)或類似物。第二模製構件130b可由與第一模製構件130a相同的材料形成,或者可由與第一模製構件130a的材料不同的材料形成。圖1中示出將第二模製構件130b與第一模製構件130a分離的邊界線,但是端視用於製作的製程,其間的邊界可能並不明顯。
第二模製構件130b可包括被設置成與第一模製構件130a的上表面物理接觸的基礎模製層(下部模製層)130b以及被設置成與基礎模製層(下部模製層)130b的上表面物理接觸的增層模製層(上部模製層)130b。第二重佈線層132可設置於基礎模製層(下部模製層)130b的上表面上,且增層模製層(上部模製層)130b可位於第二重佈線層132上且至少部分地覆蓋第二重佈線層132。
第二重佈線層132可包括設置於基礎模製層(下部模製層)130b的上表面上的重佈線接墊(或「背側重佈線接墊」)132P以及將重佈線接墊132P電性連接至垂直連接結構110的重佈線圖案(或「背側重佈線圖案」)132L。第二重佈線層132可包括多個重佈線接墊132P及將所述多個重佈線接墊132P與所述多個垂直連接結構110彼此連接的多個重佈線圖案132L。第二重佈線層132可設置於第一模製構件130a上,以向封裝100A的背側提供電路。第二重佈線層132可包含導電材料。舉例而言,所述導電材料可為銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。第二重佈線層132可端視其設計執行各種功能。舉例而言,第二重佈線層132可具有接地(ground,GND)圖案、電源(power,PWR)圖案及/或訊號(signal,S)圖案。第二重佈線層132可藉由鍍覆製程形成,且可包括晶種層及導體層。
重佈線接墊132P可為直接連接至電性連接結構185的一部分,且可具有圓形接墊,所述圓形接墊所具有的直徑大於重佈線圖案132L的寬度。然而,在本發明概念的其他實施例中,重佈線接墊132P的形狀不必限於該些實例。
重佈線圖案132L可為被形成為在第一模製構件130a上延伸的電路圖案,且具有連接至重佈線接墊132P的一個端部及連接至垂直連接結構110的另一端部。重佈線圖案132L可自重佈線接墊132P的一側沿基礎模製層(下部模製層130b)的上表面延伸,且可藉由穿透基礎模製層(下部模製層)130b的背側通孔133電性連接至垂直連接結構110。
重佈線基板140可包括絕緣層141、設置於絕緣層141上的第一重佈線層142以及穿過絕緣層141將第一重佈線層142與凸塊下金屬160或垂直連接結構110彼此電性連接的重佈線通孔143。重佈線基板140可對半導體晶片120的連接電極120P進行重佈線,且可藉由連接凸塊170將連接電極120P物理連接及/或電性連接至外部實體。絕緣層141、第一重佈線層142及重佈線通孔143的數目可大於或小於圖式中所示的數目。
絕緣層141可包含絕緣材料。舉例而言,感光成像介電質(photoimageable dielectric,PID)可用作所述絕緣材料。在此種實施例中,可藉由光通孔實施精細節距。絕緣層141之間的邊界可能是明顯的,或者亦可能不明顯。
第一重佈線層142可對半導體晶片120的連接接墊120P進行重佈線,以將垂直連接結構110與連接凸塊170彼此電性連接。第一重佈線層142可為銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。重佈線層142可端視其設計執行各種功能。舉例而言,第一重佈線層142可具有接地(GND)圖案、電源(PWR)圖案及/或訊號(S)圖案、以及類似物。接地(GND)圖案與電源(PWR)圖案可相同。另外,第一重佈線層142可包括重佈線通孔接墊及連接凸塊接墊。第一重佈線層142可藉由鍍覆製程形成,且可包括晶種層及導體層。
重佈線通孔143可將形成於不同層上的第一重佈線層142彼此電性連接,且亦可將半導體晶片120的連接電極120P以及垂直連接結構110連接至第一重佈線層142。當半導體晶片120是裸晶粒時,重佈線通孔143可與連接電極120P物理接觸。重佈線通孔143為銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。重佈線通孔143可具有用於訊號的通孔、用於電源的通孔、用於接地的通孔以及類似物,且用於電源的通孔與用於接地的通孔可相同。重佈線通孔143可為利用金屬材料填充的場型通孔(field type via),或者可為其中沿通孔孔洞的壁表面形成金屬材料的共形型通孔(conformal type via)。重佈線通孔143可藉由鍍覆製程形成,且可包括晶種層及導體層。
電性連接結構185(或背側電性連接結構)可包括設置於第二模製構件130b的上表面上且電性連接至第二重佈線層132的電性連接接墊182以及形成於電性連接接墊182下方且穿過第二模製構件130b將電性連接接墊182與重佈線接墊132P彼此連接的電性連接通孔183。可提供數十至數萬個電性連接結構185。在重佈線基板140上,多個垂直連接結構110可與半導體晶片120的側表面間隔開,以與半導體晶片120交接及/或環繞半導體晶片120。連接結構185可設置於與所述多個垂直連接結構110交接及/或環繞所述多個垂直連接結構110的區中。在此種實施例中,所述多個背側電性連接結構185可不設置於與所述多個垂直連接結構110交接及/或環繞所述多個垂直連接結構110的區的中心部分中。
電性連接接墊182與電性連接通孔183可彼此整合,且在一些實施例中,可包括單片結構(monolithic structure)。因此,電性連接結構185可設置於第二模製構件130b上,且可具有自第二模製構件130b的上表面突出的接墊部分182以及被設置成穿過第二模製構件130b與重佈線接墊132P物理接觸的通孔部分183。電性連接結構185的接墊部分182所具有的寬度D2可大於重佈線接墊132P的寬度D1。
電性連接結構185包括沿第二模製構件130b的表面及重佈線接墊132P的表面形成的晶種層182a及183a、形成於晶種層182a及183a上的導電層182b及183b、以及形成於導電層182b及183b上的接觸層182c。導體層182b及183b可包括在水平方向上沿第二模製構件130b的上表面延伸的本體層182b以及藉由第二模製構件130b朝向重佈線接墊132P延伸的通孔本體層183b。晶種層182a及183a可包含銅(Cu),且可藉由無電鍍覆(electroless plating)形成。導體層182b及183b可包含鎳(Ni),且可藉由電鍍(electroplating)形成。接觸層182c可包含金(Au),且可藉由電鍍形成。晶種層182a及183a、導體層182b及183b以及接觸層182c可分別具有為約0.8微米的厚度、為約5微米的厚度及為約0.5微米的厚度。在電性連接結構185中,形成於用於焊料結合的Cu接墊(包括於第二重佈線層中的接墊)的表面上作為障壁層(barrier layer)及擴散障壁層(diffusion barrier layer)的Ni/Au層可被分離成附加的導電結構,以減小Cu接墊的大小及增加封裝背側上的Cu圖案的積體密度。
第二鈍化層181可具有設置於第二模製構件130b上的開口181h,以暴露出電性連接接墊182的至少一部分。經由第二鈍化層181暴露出的電性連接接墊182的寬度D3可具有滿足預定標準的大小。經由第二鈍化層181的開口181h暴露出的電性連接接墊182的所暴露表面的寬度D3可大於重佈線接墊132P的寬度D1。第二鈍化層181被配置成保護電性連接結構185免受物理及化學損壞。第二鈍化層181可包含熱固性樹脂。舉例而言,第二鈍化層189可為ABF,但實施例不限於此。可提供數十至數萬個開口181h。
在典型的POP中,可形成於下部封裝的背側上的用於POP的背側連接接墊可被設計成具有預定大小。用於POP的背側連接接墊的表面上形成有用於結合至焊料的表面處置層(surface treatment layer)(Ni/Au)。在此種情形中,當用於POP的背側連接接墊的數目增加時,用於形成背側互連線的空間受到約束,且在減小背側互連線的寬度方面可能存在技術限制。因此,可能難以實施用於高效能半導體晶片的POP結合的多個背側連接接墊。
相反,根據一些示例性實施例的半導體封裝100A可包括用於結合至焊料的背側電性連接結構185。背側電性連接結構185包括包含鎳(Ni)的導體層182b及183b以及設置於導體層182b及183b的上表面上且包含金(Au)的接觸層182c。在圖1所示剖視圖中,包含銅(Cu)的第二重佈線層132或重佈線接墊132P可設置於背側電性連接結構185下方。背側電性連接結構185的接墊部分182所具有的寬度D2可大於重佈線接墊132P的寬度D1。因此,電性連接至重佈線接墊132P的重佈線圖案132L可形成得更密集,而沒有由背側電性連接結構185的數目的增加引起的空間限制,焊料被結合至背側電性連接結構185以用於POP結合。
舉例而言,重佈線接墊132P可包括彼此相鄰設置的第一背側重佈線接墊132P-1與第二背側重佈線接墊132P-2。電性連接接墊182可包括設置於第一背側重佈線接墊132P-1上方的第一電性連接接墊182-1以及設置於第二背側重佈線接墊132P-2上方的第二電性連接接墊182-2,如圖2所示平面圖中所示。重佈線圖案132L可包括穿透於第一背側重佈線接墊132P-1與第二背側重佈線接墊132P-2之間以將垂直連接結構110與其他重佈線接墊132P彼此連接的重佈線圖案132L。在半導體封裝100A的剖視圖中,所述多個重佈線圖案的至少一部分可與第一電性連接接墊182-1及第二電性連接接墊182-2中的至少一者垂直重疊。第一電性連接接墊182-1與第二電性連接接墊182-2之間的距離W1可小於第一背側重佈線接墊132P-1與第二背側重佈線接墊132P-2之間的距離W2。
第一鈍化層150被配置成保護重佈線基板140免受物理及化學損壞。第一鈍化層150可包含熱固性樹脂。舉例而言,第一鈍化層150可為ABF,但其實施例不限於此。第一鈍化層150可具有被形成為暴露出第一重佈線層142中最下部的第一重佈線層142的至少一部分的開口。所述開口可以數十至數萬的量提供,或者可以數十至數千或更多的量或者數十至數千或更少的量提供。開口中的每一者可具有多個孔洞。
凸塊下金屬160可改善連接凸塊170的連接可靠性,且可改善半導體封裝100A的板級可靠性。凸塊下金屬160可以數十至數萬的量提供,或者以數十至數千或更多的量或者數十至數千或更少的量提供。凸塊下金屬160中的每一者可形成於第一鈍化層150的開口中,以電性連接至所暴露出的最下部的第一重佈線層142。凸塊下金屬160可藉由使用金屬的金屬化方法形成,但是形成凸塊下金屬160的方法的實施例不限於此。
連接凸塊170被配置成將半導體封裝100A物理及/或電性連接至外部實體。舉例而言,半導體封裝100A可藉由連接凸塊170安裝於電子裝置的主板上。連接凸塊170可設置於第一鈍化層150上,且可分別電性連接至凸塊下金屬160。連接凸塊170可由例如錫(Sn)或包含錫(Sn)的合金等具有低熔點的金屬形成。連接凸塊170可包含焊料,但根據本發明概念的各種實施例,其材料不必受到限制。
連接凸塊170可被實施成接腳(land)、球、引腳(pin)或類似物。連接凸塊170可被形成為具有多層式結構或單層結構。當電性連接凸塊170被形成為具有多層式結構時,電性連接凸塊170可包含銅柱及焊料。當電性連接金屬被形成為具有單層結構時,電性連接凸塊170可包含錫-銀焊料或銅。然而,其示例性實施例不限於此。電性連接凸塊170的數目、間隔、設置形式及類似特徵不必受到限制,而是可由熟習此項技術者根據本發明概念的各種實施例基於設計具體細節來充分修改。
連接凸塊170中的至少一者可設置於扇出區(fan-out region)中。扇出區可指代其中設置有半導體晶片120的區之外的區。相較於扇入封裝(fan-in package),扇出封裝(fan-out package)可具有改善的可靠性,可使得能夠實施多個輸入/輸出(input/output,I/O)端子,且可促進三維(three dimensional,3D)互連。另外,相較於球柵陣列(ball grid array,BGA)封裝、接腳柵陣列(land grid array,LGA)封裝或類似物,扇出封裝可被製造成具有相對小的厚度,且在經濟上可為有利的。
圖3是根據本發明概念又一些示例性實施例的半導體封裝100B的剖視圖,且圖4A至圖6B是示出圖3所示半導體封裝中的元件的各種實例的示意性平面圖。
參照圖3及圖4A至圖6B,半導體封裝100B可具有穿透背側電性連接結構185的電性連接接墊182的第一凹槽182H1及/或第二凹槽182H2。第一凹槽182H1及第二凹槽182H2可藉由電性連接接墊182的鍍覆製程中的圖案化來形成,或者可藉由移除電性連接接墊182的一部分來形成。
圖4A及圖4B示出具有第一孔洞182H1的電性連接接墊182A及182B,第一孔洞182H1各自具有示例性配置。第一孔洞182H1可形成於電性連接接墊182A及182B的外部區中。外部區被第二鈍化層181覆蓋。第一孔洞182H1穿透構成電性連接接墊182的接觸層182c、導體層182b及晶種層182a中的至少一者。第一孔洞182H1中的每一者可具有其中當自上方(即,平面圖)觀察時內部壁連續連接的中空形狀(圖4A),或者可具有其中內壁的一側可敞開的形狀(圖4B)。第一孔洞182H1可利用第二鈍化層181至少部分地填充。因此,第二鈍化層181的黏合及結合可改善,且封裝的可靠性可改善。
圖5示出具有第二孔洞182H2的電性連接接墊182C,第二孔洞182H2各自具有示例性配置。第二孔洞182H2可形成於電性連接接墊182C的內部區中。內部區是未被第二鈍化層181覆蓋且被暴露出的區,且是開口181h的內部區。第二孔洞182H2可穿透構成電性連接接墊182的接觸層182c、導體層182b及晶種層182a中的至少一者。第二孔洞182HC可穿透接觸層182c、導體層182b及晶種層182a中的所有者,以暴露出第二模製構件130b的一部分。在此種實施例中,第二孔洞182HC可用作除氣孔洞(degassing hole),以增加對第二模製構件130b的黏合強度。第二孔洞182H2可具有其中當自上方(即,平面圖)觀察時內部壁連續連接或者空洞(hollow)的至少一部分可連續連接的中空形狀。第二孔洞182H2可在POP結合期間利用焊料至少部分地填充,以改善焊料的結合及封裝的可靠性。
圖6A及圖6B示出具有第一孔洞182H1及第二孔洞182H2的電性連接接墊182D及182F,第一孔洞182H1及第二孔洞182H2各自具有示例性配置。第一孔洞182H1可至少部分地被第二鈍化層181覆蓋,且第二孔洞182H2可自第二鈍化層181暴露出。當自上方(即,平面圖)觀察時,第二孔洞182H2可形成於不與電性連接通孔183重疊的位置中。
圖3及圖4A至圖6B中所示的其他元件與圖1中所示的元件相似,且因此,將不再對其予以贅述。
圖7是根據本發明概念又一些示例性實施例的半導體封裝100C的剖視圖,且圖8是示出與圖7所示半導體封裝中的區「B」對應的元件的示意性平面圖。圖8示出當自上方(即,平面圖)觀察圖7所示半導體封裝100C時與區「B」對應的部分。
參照圖7及圖8,半導體封裝100C可設置於第二模製構件130b的上表面上,且可更包括自電性連接接墊182P8延伸的電性連接圖案182L。電性連接圖案182L可藉由穿透第二模製構件130b的電性連接通孔183連接至重佈線接墊132P。因此,電性連接接墊182P可被設置成相對於重佈線接墊132P偏移。由於可使用電性連接圖案182L來延伸及選擇電性連接接墊182P的佈置區,因此可增加設計的自由度,且可形成更大數目的電性連接接墊182P。
電性連接圖案182L可設置於第二模製構件130b上,以在封裝100C的背側上提供電路。電性連接圖案182L可包括導電材料。舉例而言,導電材料可為銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。第二電性連接圖案182L可端視其設計執行各種功能。舉例而言,第二電性連接圖案182L可包括接地(GND)圖案、電源(PWR)圖案及/或訊號(S)圖案。電性連接圖案182L可藉由鍍覆製程形成,且可包括晶種層及導體層。電性連接圖案182L可為沿第二模製構件130b的上表面延伸的電路圖案,且具有連接至電性連接接墊182P的一個端部及連接至穿透第二模製構件130b的電性連接通孔183的另一端部。電性連接圖案182L可如在圖7及圖8所示剖視圖及平面圖中所示在水平方向上自第二模製構件130b的上表面延伸,且當自上方(即,圖8所示平面圖)觀察時,可在彼此不同的第一方向與第二方向上彎折。
電性連接接墊182P具有由第二鈍化層181的開口181h暴露出的部分,且提供POP結構的上部封裝的連接部分。電性連接接墊182P可為所具有的直徑大於電性連接圖案182L的線寬的圓形接墊。然而,根據本發明概念的各種實施例,電性連接接墊182P的形狀不必限於圖8中所示的形狀。
在圖7及圖8中所示的元件中,由與圖1中的參考編號相同的參考編號表示的元件相似於圖1中所示的元件,且因此,將不再對其予以贅述。
圖9是根據本發明概念又一些示例性實施例的半導體封裝100D的剖視圖,且圖10是示出與圖9所示半導體封裝中的區「C」對應的元件的示意性平面圖。圖10示出當自上方(即,平面圖)觀察圖9所示半導體封裝100D時與區「C」對應的部分。
參照圖9及圖10,半導體封裝100D可包括旁路佈線層184,旁路佈線層184與電性連接接墊182設置於相同的水平高度上,且電性連接彼此間隔開的多個第二重佈線層132。旁路佈線層184可與電性連接接墊182物理間隔開。與具有由開口181h暴露出的部分的電性連接接墊182不同,在一些實施例中,旁路佈線層184可被第二鈍化層181完全覆蓋。第二重佈線層132的密度問題可使用旁路佈線層184來解決。
在圖9所示剖視圖中,旁路佈線層184可與多個重佈線圖案132L重疊,且當自上方(即,圖10所示平面圖)觀察時可橫跨多個重佈線接墊132P延伸。旁路佈線層184可設置於第二模製構件130b上,以向封裝100D的背側提供電路。旁路佈線層184可包含導電材料。舉例而言,所述導電材料可為銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。旁路佈線層184可端視其設計執行各種功能。舉例而言,旁路佈線層184可具有接地(GND)圖案、電源(PWR)圖案及/或訊號(S)圖案。旁路佈線層184可藉由鍍覆製程形成,且可包括晶種層及導體層。
在圖9及圖10中所示的元件中,由與圖1中的參考編號相同的參考編號表示的元件相似於圖1中所示的元件,且因此,將不再對其予以贅述。
圖11A及圖11B是示出半導體封裝的元件的示意性剖視圖。圖11A及圖11B示出根據本發明概念一些示例性實施例的電性連接結構185的示意性配置。
參照圖11A及圖11B,電性連接結構185可包括晶種層182a及183a、導體層CL及接觸層182c。
在圖11A中,導體層CL可包括在水平方向上在第二模製構件130b上延伸的本體層182b-1及182b-2以及朝向重佈線接墊132P延伸的通孔本體層183b-1及183b-2。導體層CL可包括包含彼此不同的金屬材料的下部金屬層182b-1及183b-1與上部金屬層182b-2及183b-2。舉例而言,下部金屬層182b-1及183b-1可包含銅,且上部金屬層182b-2及183b-2可包含鎳。導體層CL可藉由電鍍形成。下部金屬層182b-1及183b-1以及上部金屬層182b-2及183b-2可各自具有為約5微米的厚度。
在圖11B中,晶種層182a及183a可沿導體層CL的下表面連續形成。晶種層183c可包括可包含彼此不同的金屬材料的下部晶種層183a-1與上部晶種層183a-2。舉例而言,下部晶種層183a-1可包含鈦(Ti)或鈦-鎢(Ti-W)合金,且上部晶種層183a-2可包含銅。晶種層183c可藉由無電鍍覆或濺射形成。下部晶種層183a-1可具有為約0.1微米的厚度,且上部晶種層183a-2可具有為約0.3微米的厚度。
接觸層182c可形成於導體層CL的上表面上。接觸層182c可包含與導體層CL及晶種層182a及183a的金屬材料不同的金屬材料。舉例而言,接觸層182c可包含金(Au),且可藉由電鍍形成。接觸層182c可在POP結合期間與焊料直接物理接觸。接觸層182c可具有為約0.5微米的厚度。
在圖11A及圖11B中所示的元件中,由與圖1中的參考編號相同的參考編號表示的元件相似於圖1中所示的元件,且因此,將不再對其予以贅述。
圖12是根據本發明概念又一些示例性實施例的半導體封裝100E的剖視圖。
參照圖12,在半導體封裝100E中,第二重佈線層132可直接設置於第一模製構件130a的上表面上,且自第一模製構件130a的上表面暴露出的垂直連接結構110可直接連接至第二重佈線層132。垂直連接結構110的上表面可設置於第二表面S2上,且第二模製構件130b可設置於第一模製構件130a的上表面上。第一表面S1、半導體晶片120的上表面及第二表面S2可彼此間隔開。與圖12中所示者不同,在另一示例性實施例中,第一表面S1與第二表面S2可設置於同一表面上。
根據本發明概念的一些實施例,上述結構可藉由利用第一模製構件130a對垂直連接結構110及半導體晶片120進行模製且使用磨光製程移除第一模製構件130a的上表面以暴露出垂直連接結構110的上表面來實施。在磨光製程中,甚至半導體晶片120的上表面亦可被暴露出,以使得第一表面S1與第二表面S2能夠彼此共面。在此種實施例中,半導體晶片120的一部分可被移除。因此,第一重佈線層142與第二重佈線層132之間的連接距離可顯著減小,以改善封裝100E的電性特性。
在圖12中所示的元件中,由與圖1中的參考編號相同的參考編號表示的元件相似於圖1中所示的元件,且因此,將不再對其予以贅述。
圖13是根據本發明概念又一些示例性實施例的半導體封裝100F的剖視圖。
參照圖13,在半導體封裝100F中,垂直連接結構110可包括被設置成與重佈線基板140物理接觸的第一絕緣層111a、被設置成與重佈線基板140物理接觸且嵌置於第一絕緣層111a中的第一佈線層112a、設置於與第一絕緣層111a的其中嵌置有第一佈線層112a的一側相對的一側上的第二佈線層112b、設置於第一絕緣層111a上且至少部分地覆蓋第二佈線層112b的第二絕緣層111b、以及設置於與第二絕緣層111b的其中嵌置有第二佈線層112b的一側相對的一側上的第三佈線層112c。第一佈線層112a與第二佈線層112b可藉由穿透第一絕緣層111a的第一佈線通孔113a彼此電性連接,且第二佈線層112b與第三佈線層112c可藉由穿透第二絕緣層111b的第二佈線通孔113b彼此電性連接。另外,第一佈線層至第三佈線層112a、112b及112c可電性連接至重佈線基板140的第一重佈線層142。
垂直連接結構110可根據絕緣層111a及111b的特定材料進一步改善封裝100F的剛性,且可確保第一模製構件130a的厚度均勻性。垂直連接結構110可具有穿透絕緣層111a及111b的貫通孔洞110H。半導體晶片120可設置於貫通孔洞110H中。貫通孔洞110H可具有其中壁表面與半導體晶片120交接及/或環繞半導體晶片120的形狀,但根據本發明概念的各種實施例,貫通孔洞110H的形狀不限於此。
根據本發明概念的各種實施例,絕緣層111a及111b的材料不必受到限制。舉例而言,絕緣層111a及111b的材料可為絕緣材料。在此種情形中,所述絕緣材料可為例如環氧樹脂等熱固性樹脂及/或例如味之素增層膜(ABF)等熱塑性樹脂。在其他實施例中,所述絕緣材料可為其中將熱固性樹脂或熱塑性樹脂與無機填料一起浸漬於例如玻璃纖維(或玻璃布或玻璃纖維布)等芯體材料中的絕緣材料,例如預浸體(prepreg)。
佈線層112a、112b及112c可與佈線通孔113a及113b一起提供封裝的上部/下部電性連接路徑,且可用於對連接電極120P進行重佈線。佈線層112a、112b及112c包含銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。端視對應層的設計,佈線層112a、112b及112c可具有接地(GND)圖案、電源(PWR)圖案及/或訊號(S)圖案。除接地(GND)圖案、電源(PWR)圖案及類似圖案以外,佈線層112a、112b及112c亦可包括例如資料訊號及類似訊號等各種訊號。接地GND圖案與電源PWR圖案可相同。另外,佈線層112a、112b及112c中的每一者可包括各種類型的通孔接墊。佈線層112a、112b及112c可藉由已知的鍍覆製程形成,且可各自包括晶種層及導體層。
佈線通孔113a及113b可將形成於不同層上的佈線層112a、112b及112c彼此電性連接。因此,可在垂直連接結構110中形成電性路徑。佈線通孔113a及113b可包含銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、鈦(Ti)或其合金。佈線通孔113a及113b中的每一者可具有用於訊號的通孔、用於電源的通孔及/或用於接地的通孔、以及類似物,且用於電源的通孔與用於接地的通孔可相同。佈線通孔113a及113b中的每一者可為利用金屬材料至少部分地填充的場型通孔,或者可為其中沿通孔孔洞的壁表面形成金屬材料的共形型通孔。佈線通孔113a及113b可藉由鍍覆製程形成,且可包括晶種層及導體層。
在圖13中所示的元件中,由與圖1中的參考編號相同的參考編號表示的元件相似於圖1中所示的元件,且因此,將不再對其予以贅述。
圖14是根據本發明概念又一些示例性實施例的層疊封裝結構300A的剖視圖。
參照圖14,層疊封裝結構300A可包括與圖1所示半導體封裝100A組合於一起的第二封裝200。第二封裝200可包括第二重佈線基板210、第二半導體晶片220及包封劑230。
第二重佈線基板210可包括分別設置於其上表面及下表面上的重佈線接墊211及212。重佈線接墊211及212中的每一者可電性連接至外部實體。另外,第二重佈線基板210可具有設置於其中的重佈線圖案,所述重佈線圖案被配置成連接至重佈線接墊211及212。重佈線圖案可將第二半導體晶片220的第二連接電極220P重佈線至扇出區。
第二半導體晶片220可包括第二連接電極220P,且第二連接電極220P可藉由金屬凸塊222電性連接至第二重佈線基板210。作為實例,第二封裝200可更包含與金屬凸塊222交接及/或環繞金屬凸塊222的底部填充材料223。底部填充材料223可為包含環氧樹脂或類似物的絕緣材料。金屬凸塊222可包括焊球或銅柱。
在其他示例性實施例中,第二半導體晶片220的第二連接電極220P可與第二重佈線基板210的上表面直接物理接觸,且可藉由第二重佈線基板210中的通孔電性連接至重佈線圖案。
包封劑230可包含與半導體封裝100A的第一模製構件130a及第二模製構件130b的材料相同或相似的材料。
第二封裝200可藉由第二連接凸塊240物理/電性連接至半導體封裝100A。第二連接凸塊240可藉由位於第二重佈線基板210的下表面上的重佈線接墊211電性連接至位於第二重佈線基板210中的重佈線圖案。在其他實施例中,重佈線圖案可藉由設置於位於第二重佈線基板210的下表面上的重佈線接墊241上的凸塊下金屬彼此電性連接。第二連接凸塊240中的每一者可由例如錫(Sn)或包含錫(Sn)的合金等具有相對低熔點的金屬形成。更具體而言,第二連接凸塊240中的每一者可由焊料或類似物形成。然而,根據本發明概念的各種示例性實施例,其材料不必限於此。
在圖14中所示的元件中,由與圖1中的參考編號相同的參考編號表示的元件相似於圖1中所示的元件,且因此,將不再對其予以贅述。
圖15是根據本發明概念又一些示例性實施例的層疊封裝結構300B的剖視圖。
參照圖15,與圖14所示層疊封裝結構300A不同,層疊封裝結構300B包括重佈線基板140,半導體封裝100A'的第一半導體晶片120可以倒裝晶片方式安裝於重佈線基板140上。第一半導體晶片120可藉由金屬凸塊122電性連接至重佈線基板140的重佈線層142。底部填充材料123可設置於第一半導體晶片120下方,以與金屬凸塊122交接及/或環繞金屬凸塊122。底部填充材料123可為包含環氧樹脂或類似物的絕緣材料。金屬凸塊122可包括焊球或銅柱。
在圖15中所示的元件中,由與圖1及圖14中的參考編號相同的參考編號表示的元件相似於圖1及圖14中所示的元件,且因此,將不再對其予以贅述。
圖16是根據本發明概念又一些示例性實施例的層疊封裝結構300C的剖視圖。
參照圖16,層疊封裝結構300C可包括與圖13所示半導體封裝100F組合於一起的第二封裝200。在圖16中所示的元件中,由與圖1及圖14中的參考編號相同的參考編號表示的元件相似於圖1及圖14中所示的元件,且因此,將不再對其予以贅述。
如上所述,電性連接接墊與第二重佈線層可彼此分離,以提供一種具有改善的第二重佈線層的積體密度及改善的可靠性的半導體封裝。
儘管以上已示出並闡述了示例性實施例,然而對於熟習此項技術者而言將顯而易見,在不背離如由隨附申請專利範圍界定的本發明概念的範圍的條件下,可進行修改及變化。
100A、100C、100D、100E、100F:封裝/半導體封裝
100A'、100B:半導體封裝
110:垂直連接結構
111a:絕緣層/第一絕緣層
111b:絕緣層/第二絕緣層
112a:佈線層/第一佈線層
112b:佈線層/第二佈線層
112c:佈線層/第三佈線層
113a:佈線通孔/第一佈線通孔
113b:佈線通孔/第二佈線通孔
120:半導體晶片/第一半導體晶片
120P:連接電極
122:金屬凸塊
123:底部填充材料
130a:第一模製構件
130b:第二模製構件/基礎模製層/增層模製層
132:第二重佈線層
132L:重佈線圖案
132P:重佈線接墊
132P-1:第一背側重佈線接墊
132P-2:第二背側重佈線接墊
133:背側通孔
140:重佈線基板
141:絕緣層
142:重佈線層/第一重佈線層
143:重佈線通孔
150:第一鈍化層
160:凸塊下金屬
170:連接凸塊/電性連接凸塊
181:第二鈍化層
181h:開口
182:接墊部分/電性連接接墊
182-1:第一電性連接接墊
182-2:第二電性連接接墊
182A、182B、182C、182D、182F、182P:電性連接接墊
182a、183a:晶種層
182b:導體層/本體層
182b-1:本體層/下部金屬層
182b-2:本體層/上部金屬層
182c:接觸層
182H1:第一凹槽/第一孔洞
182H2:第二凹槽/第二孔洞
182L:電性連接圖案
183:通孔部分/電性連接通孔
183a-1:下部晶種層
183a-2:上部晶種層
183b:導體層/通孔本體層
183b-1:通孔本體層/下部金屬層
183b-2:通孔本體層/上部金屬層
184:旁路佈線層
185:連接結構/電性連接結構/背側電性連接結構
200:第二封裝
210:第二重佈線基板
211、212:重佈線接墊
220:第二半導體晶片
220P:第二連接電極
222:金屬凸塊
223:底部填充材料
230:包封劑
240:第二連接凸塊
300A、300B、300C:層疊封裝結構
A、B、C:區
CL:導體層
D1、D2:寬度
D3:寬度
S1:第一表面
S2:第二表面
W1、W2:距離
結合附圖閱讀以下詳細說明,將更清楚地理解本揭露的以上及其他態樣、特徵及優點。
圖1是根據本發明概念一些示例性實施例的半導體封裝的剖視圖。
圖2是示出與圖1所示半導體封裝中的區「A」對應的元件的示意性平面圖。
圖3是根據本發明概念又一些示例性實施例的半導體封裝的剖視圖。
圖4A至圖6B是示出圖3所示半導體封裝中的元件的各種實例的示意性平面圖。
圖7是根據本發明概念又一些示例性實施例的半導體封裝的剖視圖。
圖8是示出與圖7所示半導體封裝中的區「B」對應的元件的示意性平面圖。
圖9是根據本發明概念又一些示例性實施例的半導體封裝的剖視圖。
圖10是示出與圖9所示半導體封裝中的區「C」對應的元件的示意性平面圖。
圖11A及圖11B是示出根據本發明概念一些實施例的半導體封裝的元件的示意性剖視圖。
圖12是根據本發明概念又一些示例性實施例的半導體封裝的剖視圖。
圖13是根據本發明概念又一些示例性實施例的半導體封裝的剖視圖。
圖14是根據本發明概念一些示例性實施例的層疊封裝結構的剖視圖。
圖15是根據本發明概念又一些示例性實施例的層疊封裝結構的剖視圖。
圖16是根據本發明概念又一些示例性實施例的層疊封裝結構的剖視圖。
100A:封裝/半導體封裝
110:垂直連接結構
120:半導體晶片/第一半導體晶片
120P:連接電極
130a:第一模製構件
130b:第二模製構件/基礎模製層/增層模製層
132:第二重佈線層
132P:重佈線接墊
133:背側通孔
140:重佈線基板
141:絕緣層
142:重佈線層/第一重佈線層
143:重佈線通孔
150:第一鈍化層
160:凸塊下金屬
170:連接凸塊/電性連接凸塊
181:第二鈍化層
181h:開口
182:接墊部分/電性連接接墊
182a、183a:晶種層
182b:導體層/本體層
182c:接觸層
183:通孔部分/電性連接通孔
183b:導體層/通孔本體層
185:連接結構/電性連接結構/背側電性連接結構
A:區
D1、D2:寬度
D3:寬度
Claims (20)
- 一種半導體封裝,包括: 重佈線基板,包括第一重佈線層; 半導體晶片,位於所述重佈線基板上,且電性連接至所述第一重佈線層; 第一模製構件,位於所述重佈線基板及所述半導體晶片上; 第二重佈線層,位於所述第一模製構件上且具有重佈線接墊; 垂直連接結構,位於所述重佈線基板與所述第二重佈線層之間,且將所述第一重佈線層與所述第二重佈線層彼此電性連接; 第二模製構件,位於所述第一模製構件以及所述第二重佈線層的至少一部分上; 電性連接接墊,位於所述第二模製構件的最上表面上,且電性連接至所述第二重佈線層;以及 鈍化層,位於所述第二模製構件上且具有暴露出所述電性連接接墊的至少一部分的開口, 其中所述電性連接接墊包括包含第一金屬的導體層及位於所述導體層上且包含第二金屬的接觸層, 其中所述重佈線接墊包含與所述第一金屬及所述第二金屬不同的第三金屬,且 其中由所述開口暴露出的所述電性連接接墊的所述部分所具有的寬度大於所述重佈線接墊的寬度。
- 如請求項1所述的半導體封裝,其中所述第二模製構件包括位於所述第一模製構件的上表面上的基礎模製層及位於所述基礎模製層的上表面上的增層模製層, 其中所述第二重佈線層的所述重佈線接墊位於所述基礎模製層的上表面上,且所述增層模製層位於所述重佈線接墊的一部分上, 其中所述電性連接接墊位於所述增層模製層的上表面上, 其中所述第二重佈線層自所述重佈線接墊的一側沿所述基礎模製層的所述上表面延伸,且具有藉由延伸穿過所述基礎模製層的背側通孔電性連接至所述垂直連接結構的重佈線圖案, 其中所述重佈線接墊包括彼此相鄰的第一背側重佈線接墊與第二背側重佈線接墊, 其中所述電性連接接墊包括在所述半導體封裝的其中所述重佈線基板充當基礎參考平面的剖視圖中位於所述第一背側重佈線接墊上方的第一電性連接接墊及位於所述第二背側重佈線接墊上方的第二電性連接接墊, 其中所述重佈線圖案包括在所述第一背側重佈線接墊與所述第二背側重佈線接墊之間延伸的多個重佈線圖案,且 其中在所述半導體封裝的所述剖視圖中,所述多個重佈線圖案的至少一部分與所述第一電性連接接墊及所述第二電性連接接墊中的至少一者垂直交疊。
- 如請求項2所述的半導體封裝,其中所述第一電性連接接墊與所述第二電性連接接墊之間的距離小於所述第一背側重佈線接墊與所述第二背側重佈線接墊之間的距離。
- 如請求項1所述的半導體封裝,其中所述電性連接接墊具有外部區,在所述外部區中形成有延伸穿過所述接觸層及所述導體層的多個第一凹槽, 其中所述鈍化層位於所述電性連接接墊上。
- 如請求項4所述的半導體封裝,其中所述電性連接接墊具有內部區,在所述內部區中形成有延伸穿過所述接觸層及所述導體層的多個第二凹槽, 其中所述電性連接接墊的所述內部區不具有所述鈍化層。
- 如請求項1所述的半導體封裝,更包括: 電性連接圖案,位於所述第二模製構件的所述最上表面上,且自所述電性連接接墊延伸, 其中所述電性連接圖案藉由延伸穿過所述第二模製構件的電性連接通孔連接至所述重佈線接墊,且 其中所述電性連接接墊相對於所述重佈線接墊偏移。
- 如請求項1所述的半導體封裝,其中所述第二重佈線層包括彼此間隔開的多個第二重佈線層, 其中旁路佈線層與所述電性連接接墊位於同一水平高度上,且將所述多個第二重佈線層彼此電性連接,且 其中所述旁路佈線層與所述電性連接接墊間隔開。
- 如請求項7所述的半導體封裝,其中所述鈍化層位於所述旁路佈線層的上表面上。
- 如請求項1所述的半導體封裝,更包括: 電性連接通孔,在所述半導體封裝的其中所述重佈線基板充當基礎參考平面的剖視圖中形成於所述電性連接接墊下方,且穿過所述第二模製構件將所述電性連接接墊與所述重佈線接墊彼此電性連接, 其中所述導體層包括在所述剖視圖中在垂直方向上在所述第二模製構件上延伸的本體層及延伸穿過所述第二模製構件且朝向所述重佈線接墊延伸的通孔本體層。
- 如請求項9所述的半導體封裝,其中所述導體層包括包含銅的下部金屬層及位於所述下部金屬層上且包含鎳的上部金屬層。
- 如請求項9所述的半導體封裝,包括: 晶種層,沿所述導體層的下表面連續延伸。
- 如請求項11所述的半導體封裝,其中所述晶種層包括包含鈦的下部晶種層及位於所述下部晶種層上且包含銅的上部晶種層。
- 如請求項1所述的半導體封裝,其中所述垂直連接結構延伸穿過所述第一模製構件。
- 如請求項1所述的半導體封裝,其中所述垂直連接結構包括與所述重佈線基板物理接觸的第一絕緣層、與所述重佈線基板物理接觸且嵌置於所述第一絕緣層中的第一佈線層、位於與所述第一絕緣層的其中嵌置有所述第一佈線層的一側相對的一側上的第二佈線層、位於所述第一絕緣層及所述第二佈線層上的第二絕緣層、及位於與所述第二絕緣層的其中嵌入有所述第二佈線層的一側相對的一側上的第三佈線層,且 其中所述第一佈線層、所述第二佈線層及所述第三佈線層電性連接至所述第一重佈線層。
- 一種半導體封裝,包括: 重佈線基板,包括第一重佈線層; 半導體晶片,位於所述重佈線基板上; 第一模製構件,位於所述重佈線基板及所述半導體晶片上; 第二重佈線層,位於所述第一模製構件上且包括重佈線接墊; 垂直連接結構,位於所述重佈線基板上,且將所述第一重佈線層與所述第二重佈線層彼此電性連接; 第二模製構件,位於所述第一模製構件以及所述第二重佈線層的至少一部分上;以及 電性連接結構,位於所述第二模製構件上,且電性連接至所述重佈線接墊, 其中所述電性連接結構包括包含鎳的導體層及位於所述導體層的上表面上且包含金的接觸層,且 其中所述重佈線接墊包含銅。
- 如請求項15所述的半導體封裝,其中所述電性連接結構具有自所述第二模製構件的最上表面突出的接墊部分及穿過所述第二模製構件與所述重佈線接墊物理接觸的通孔部分。
- 如請求項16所述的半導體封裝,其中所述電性連接結構的所述接墊部分所具有的寬度大於所述重佈線接墊的寬度。
- 一種半導體封裝,包括: 重佈線基板,包括第一重佈線層; 半導體晶片,位於所述重佈線基板上,且電性連接至所述第一重佈線層; 第一模製構件,位於所述重佈線基板及所述半導體晶片上; 多個垂直連接結構,嵌置於所述第一模製構件中且電性連接至所述第一重佈線層; 第二模製構件,包括位於所述第一模製構件的上表面上的基礎模製層及位於所述基礎模製層的上表面上的增層模製層; 第二重佈線層,位於所述基礎模製層的所述上表面上,且包括多個重佈線接墊及多個重佈線圖案,所述多個重佈線圖案將所述多個重佈線接墊與所述多個垂直連接結構彼此電性連接;以及 多個電性連接結構,位於所述第二模製構件上,且具有自所述增層模製層的所述上表面突出的接墊部分及穿過所述增層模製層與所述多個重佈線接墊中的至少一者物理接觸的通孔部分, 其中所述多個電性連接結構包括包含鎳的導體層及位於所述導體層的上表面上且包含金的接觸層, 其中所述多個重佈線接墊包括彼此相鄰的第一背側重佈線接墊與第二背側重佈線接墊, 其中所述多個電性連接結構包括與所述第一背側重佈線接墊及所述第二背側重佈線接墊分別對應的第一背側電性連接結構及第二背側電性連接結構,且 其中所述多個重佈線圖案在所述第一背側重佈線接墊與所述第二背側重佈線接墊之間延伸,且在所述半導體封裝的其中所述重佈線基板充當基礎參考平面的剖視圖中,所述多個重佈線圖案的至少一部分與所述第一背側電性連接結構及所述第二背側電性連接結構中的至少一者垂直重疊。
- 如請求項18所述的半導體封裝,其中所述多個垂直連接結構在所述重佈線基板上與所述半導體晶片交接,且 其中所述多個電性連接結構位於與所述多個垂直連接結構交接的區中。
- 如請求項19所述的半導體封裝,其中所述多個電性連接結構位於與所述多個垂直連接結構交接的所述區的中心部分之外。
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