CN112447529A - 制造半导体封装件的方法 - Google Patents

制造半导体封装件的方法 Download PDF

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Publication number
CN112447529A
CN112447529A CN202010844089.5A CN202010844089A CN112447529A CN 112447529 A CN112447529 A CN 112447529A CN 202010844089 A CN202010844089 A CN 202010844089A CN 112447529 A CN112447529 A CN 112447529A
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Prior art keywords
layer
barrier layer
redistribution
forming
sacrificial
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CN202010844089.5A
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Inventor
朴正镐
朴镇右
张在权
全光宰
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN112447529A publication Critical patent/CN112447529A/zh
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Abstract

制造半导体封装件的方法可包括：在第一载体上形成第一阻挡层；在第一阻挡层上形成包括暴露第一阻挡层的至少一部分的开口的牺牲层；在第一阻挡层上和牺牲层上形成第二阻挡层。第二阻挡层可包括形成在牺牲层上的部分。所述方法还可包括在开口中形成第一绝缘层，第一绝缘层突出超过第二阻挡层的所述部分的顶表面，第一绝缘层的顶表面比第二阻挡层的所述部分的顶表面更远离第一阻挡层；在第一绝缘层上和第二阻挡层上形成包括再分布层和第二绝缘层的再分布结构；在再分布结构上安装半导体芯片；将第二载体附着到半导体芯片上并去除第一载体；去除第一阻挡层、牺牲层和第二阻挡层以暴露再分布结构的部分；和分别在再分布结构的所述部分上形成焊料球。

Description

制造半导体封装件的方法
相关申请的交叉引用
本申请要求于2019年8月30日在韩国知识产权局提交的韩国专利申请No.10-2019-0107487的优先权，其公开内容通过引用全部合并于此。
技术领域
本公开涉及制造半导体封装件的方法。
背景技术
近来，随着高性能器件越来越受到青睐，不仅半导体芯片的尺寸增加，而且半导体封装件的尺寸也相应地增加。相比之下，随着电子设备变得更纤薄，半导体封装件的厚度减小。
半导体封装是封装半导体芯片以将半导体芯片(或半导体裸片)与电子设备电连接的过程。随着半导体芯片的尺寸减小，已经提出了扇出晶片级封装(FOWLP)，在FOWLP中，半导体封装件的输入端子和输出端子经由再分布层设置在半导体芯片的外部。由于FOWLP简单且可用于形成薄的半导体封装件，因此FOWLP适合于半导体封装件的小型化和薄型化，并且可以提供改善的热特性和电特性。
发明内容
本发明构思的实施例提供了具有改善的产品可靠性的半导体封装件。
本发明构思的实施例还提供了制造具有改善的产品可靠性的半导体封装件的方法。
根据本发明构思的一些实施例，制造半导体封装件的方法可以包括：在第一载体上形成第一阻挡层；在所述第一阻挡层上形成牺牲层，所述牺牲层包括暴露所述第一阻挡层的至少一部分的开口；在所述第一阻挡层上和所述牺牲层上形成第二阻挡层，所述第二阻挡层包括形成在所述牺牲层上的部分；在所述开口中形成第一绝缘层，所述第一绝缘层突出超过所述第二阻挡层的所述部分的顶表面，所述第一绝缘层的顶表面比所述第二阻挡层的所述部分的所述顶表面更远离所述第一阻挡层；在所述第一绝缘层上和所述第二阻挡层上形成包括再分布层和第二绝缘层的再分布结构；在所述再分布结构上安装半导体芯片；将第二载体附着到所述半导体芯片上并去除所述第一载体；去除所述第一阻挡层、所述牺牲层和所述第二阻挡层以暴露所述再分布结构的部分；以及分别在所述再分布结构的所述部分上形成焊料球。
根据本发明构思的一些实施例，制造半导体封装件的方法可以包括：在第一载体上顺序地形成脱模层和第一阻挡层；在所述第一阻挡层上形成牺牲层，所述牺牲层包括金属材料和暴露所述第一阻挡层的至少一部分的开口；形成在所述第一阻挡层上和所述牺牲层上延伸的第二阻挡层；在所述开口中形成比所述牺牲层厚的第一绝缘层；在所述第一绝缘层上和所述第二阻挡层上形成包括再分布层和第二绝缘层的再分布结构；在所述再分布结构上安装半导体芯片；将第二载体附着到所述半导体芯片上，并去除所述第一载体和所述脱模层；去除所述第一阻挡层、所述牺牲层和所述第二阻挡层以暴露所述再分布层的部分；以及分别在所述再分布层的所述部分上形成焊料球。
根据本发明构思的一些实施例，制造半导体封装件的方法可以包括：在第一载体上顺序地形成脱模层和第一阻挡层；在所述第一阻挡层上形成牺牲层，所述牺牲层包括暴露所述第一阻挡层的至少一部分的开口；在所述第一阻挡层上和所述牺牲层上共形地形成第二阻挡层；在所述开口中形成第一绝缘层，所述第一绝缘层的顶表面比所述第二阻挡层的形成在所述牺牲层上的部分的顶表面更远离所述第一阻挡层；在所述第一绝缘层上和所述第二阻挡层上形成再分布结构，所述再分布结构包括再分布层和堆叠在所述再分布层上以围绕所述再分布层的第二绝缘层；在所述再分布结构上安装半导体芯片；将第二载体附着到所述半导体芯片上并去除所述第一载体；去除所述脱模层；顺序地去除所述第一阻挡层、所述牺牲层和所述第二阻挡层；以及在已经去除了所述牺牲层的空间中形成焊料球，所述焊料球电连接到所述再分布层。
本发明构思不限于本文提供的示例实施例。通过参考本文参照附图描述的详细说明，对于本发明构思所属领域的普通技术人员而言，本发明构思的以上以及其他实施例将变得更加显而易见。
附图说明
通过本文参照附图提供的描述，本发明构思的示例实施例和特征将变得更加明显，其中：
图1是根据本发明构思的一些实施例的半导体封装件的截面图；
图2是图1的区域S1的放大截面图；
图3是根据本发明构思的一些实施例的半导体封装件的截面图；
图4至图16是示出根据本发明构思的一些实施例的制造半导体封装件的方法的截面图；以及
图17和图18是示出根据本发明构思的一些实施例的制造半导体封装件的方法的截面图。
具体实施方式
图1是根据本发明构思的一些实施例的半导体封装件的截面图。
参照图1，根据本发明构思的一些实施例的半导体封装件可以包括再分布结构100、半导体芯片200、模制部件300和焊料球400。
再分布结构100可以包括彼此相对的第一表面100a和第二表面100b。例如，第一表面100a可以是再分布结构100的顶表面，而第二表面100b可以是再分布结构100的底表面。
再分布结构100可以包括多个再分布层(120、125、126和128)、多个绝缘层(110、112、114和116)以及多个通路(132和134)。
再分布层(120、125、126和128)可以沿第一方向D1延伸。每个再分布层(120、125、126和128)可以包括在第一方向D1上彼此间隔开的多个再分布层。
再分布层(120、125、126和128)可以从第二表面100b到第一表面100a顺序地堆叠。即，再分布层(120、125、126和128)可以在第二方向D2上彼此间隔开并且可以沿第二方向D2设置在不同的水平高度处。这里，第二方向D2可以是垂直于第一方向D1的方向。
再分布层(120、125、126和128)可以通过多个通路(132和134)电连接。再分布层(120、125、126和128)的数目以及再分布层(120、125、126和128)的位置和布置不限于图1中所示的那些，并且可以与图1所示的那些不同。
再分布层(120、125、126和128)可以通过沟槽100t至少部分地暴露。例如，第一再分布层125可以通过沟槽100t至少部分地暴露。第一再分布层125可以包括电极焊盘122和子再分布层124，将在后面参照图2对此进行描述。在一些实施例中，如图1所示，再分布层(120、125、126和128)的至少一部分可以接触沟槽100t中的绝缘层(例如，110)。
再分布层(120、125、126和128)可以包括例如铜(Cu)，但是本发明构思不限于此。另外，再分布层(120、125、126和128)可以包括例如铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)及其合金中的至少一种。
通路(132和134)可以将以不同水平高度形成的再分布层(120、125、126和128)相互连接。例如，第一通路132可以穿过第二绝缘层112连接第一再分布层125和第二再分布层126，并且第二通路134可以穿过第三绝缘层114连接第二再分布层126和第三再分布层128。通路(132和134)的数目以及通路(132和134)的位置和布置不限于图1所示的那些，并且可以与图1所示的那些不同。
通路(132和134)可以包括导电材料。因此，可以在再分布结构100中形成连接第一表面100a和第二表面100b的电路径。例如，通路(132和134)可以包括与再分布层(120、125、126和128)相同的材料。通路(132和134)可以包括例如Cu。另外，通路(132和134)可以包括例如Al、Ag、Sn、Au、Ni、Pb、Ti及其合金中的至少一种。
绝缘层(110、112、114和116)可以围绕再分布层(120、125、126和128)以及通路(132和134)。
绝缘层(110、112、114和116)可以包括相同的材料。绝缘层(110、112、114和116)可以包括例如光可成像电介质(PID)材料。绝缘层(110、112、114和116)可以包括例如环氧树脂或聚酰亚胺。因此，可以通过光刻以晶片级形成绝缘层(110、112、114和116)。绝缘层(110、112、114和116)可以形成为薄的，并且通路(132和134)可以形成为具有精细的节距。
半导体芯片200可以安装在再分布结构100的第一表面100a上。再分布结构100可以包括与半导体芯片200交叠的扇入区域和不与半导体芯片200交叠的扇出区域(即，除扇入区域以外的区域)。即，根据本发明构思的一些实施例的半导体封装件可以是扇出晶片级封装件，但是本发明构思不限于此。在一些实施例中，根据本发明构思的一些实施例的半导体封装件可以是晶片级封装件。
半导体芯片200可以是例如其中集成有数百至数百万个器件的集成电路(IC)。半导体芯片200可以是例如处理器芯片(例如，中央处理单元(CPU)、图形处理单元(GPU)、现场可编程门阵列(FPGA)、数字信号处理器、密码处理器)，或者微处理器，特别是诸如应用处理器(AP)的逻辑芯片。在一些实施例中，半导体芯片200可以是诸如动态随机存取存储器(DRAM)或静态随机存取存储器(SRAM)的易失性存储器芯片，或者诸如相变随机存取存储器(PRAM)、磁阻随机存取存储器(MRAM)、铁电随机存取存储器(FeRAM)或电阻随机存取存储器(RRAM)的非易失性存储器芯片。在一些实施例中，半导体芯片200可以是逻辑芯片和存储器芯片的组合，但是本发明构思不限于此。
半导体芯片200可以包括连接焊盘210、钝化层220和凸块230。
连接焊盘210可以将半导体芯片200与其他元件电连接。连接焊盘210可以包括例如诸如Al的导电材料。
钝化层220可以至少部分地暴露连接焊盘210。钝化层220可以是例如氧化物膜、氮化物膜、氧化物膜和氮化物膜的双层。钝化层220可以包括绝缘材料，例如，热固性树脂(例如，环氧树脂)、热塑性树脂(例如，聚酰亚胺)，或者热固性或热塑性树脂和无机填充物的混合物，或者通过用无机填料浸渍诸如玻璃纤维的芯材而获得的诸如预浸料、味之素堆积膜(Ajinomoto Build-up Film，ABF)、FR-4或双马来酰亚胺三嗪(BT)的树脂。
凸块230可以设置在再分布结构100的第一表面100a与连接焊盘210之间。凸块230可以与连接焊盘210和再分布层120接触。凸块230可以电连接半导体芯片200和再分布结构100。凸块230可以包括例如Au、Ag、Ni、Cu、Sn及其合金中的至少一种，但是本发明构思不限于此。
模制部件300可以覆盖半导体芯片200的侧面和顶表面。模制部件300可以填充半导体芯片200的侧面和顶表面、再分布结构100的第一表面100a与凸块230之间的间隙。模制部件300的侧面可以与再分布结构100的侧面形成相同的平面。将理解的是，“元件A覆盖元件B”(或类似语言)意味着件A在元件B上延伸，但不一定意味着元件A完全覆盖元件B。还应理解，如本文所使用的“元件A填充元件B”(或类似语言)意味着元件A在元件B中，但不一定意味着元件A完全填充元件B。
模制部件300可以包括例如环氧模塑化合物(EMC)或硅树脂混合材料。
焊料球400可以设置在形成在再分布结构100的第二表面100b上的一个或更多个沟槽100t中。焊料球400可以设置在第一再分布层125上。因此，焊料球400可以电连接到再分布结构100。另外，根据本发明构思的一些实施例的半导体封装件可以通过焊料球400电连接到外部装置。焊料球400的数目以及焊料球400的形状和布置不限于图1所示的那些，并且可以与图1所示的那些不同。
焊料球400可以包括例如Sn、铟(In)、铅(Pb)、锌(Zn)、Ni、Au、Ag、Cu、锑(Sb)、铋(Bi)及它们的组合中的至少一种，但是本发明构思不限于此。
图2是图1的区域S1的放大截面图。
参照图2，第二再分布层126可以设置在第一再分布层125上。第一再分布层125和第二再分布层126可以与第一通路132接触。
第一再分布层125可以包括在第二方向D2上具有第一厚度T1的第一部分I和在第二方向D2上具有第二厚度T2的第二部分II。第一部分I的在第二方向D2上的顶表面和第二部分II的在第二方向D2上的顶表面可以一起形成相同的平面。第一厚度T1可以大于(即，厚于)第二厚度T2。在一些实施例中，第一部分I的顶表面和第二部分II的顶表面面对第二再分布层126并且彼此共面，如图2所示。
第一再分布层125可以包括电极焊盘122和子再分布层124。第一部分I可以包括电极焊盘122和子再分布层124，第二部分II可以包括子再分布层124。
电极焊盘122可以具有从第二表面100b起(即，在第二方向D2上)的第一高度H1。子再分布层124可以具有从第二表面100b起(即，在第二方向D2上)的第二高度H2。第二高度H2可以大于第一高度H1。
电极焊盘122可以具有第一宽度W1。子再分布层124可以具有大于第一宽度W1的第二宽度W2。电极焊盘122可以以第一宽度W1设置在子分布层214的一部分中。在一些实施例中，电极焊盘122可以包括面对焊料球400的下表面，并且电极焊盘122的下表面可以具有第一宽度W1，如图2所示。在一些实施例中，电极焊盘122可以接触焊料球400，并且电极焊盘122可以在与焊料球400的界面处或附近具有第一宽度W1，如图2所示。如本文所使用的术语“一部分”可以与术语“部分”互换，并且“元件A的一部分”(或类似语言)可以指代“元件A的部分”。
电极焊盘122和子再分布层124可以具有一体化的结构。如本文所使用的术语“一体化的结构”可以指具有通过相同工艺制造的部件的结构。即，可以通过相同的工艺形成电极焊盘122和子再分布层124。因此，电极焊盘122和子再分布层124可以包括相同的材料。电极焊盘122和子再分布层124可以包括例如Cu。
再分布结构100可以包括形成在第二表面100b上的沟槽100t。在一些实施例中，沟槽100t可以连接到第二表面100b，如图2所示。
沟槽100t可以由第一绝缘层110限定。
沟槽100t可以由第一绝缘层110和电极焊盘122限定。也就是说，电极焊盘122可以由沟槽100t暴露。电极焊盘122可以沿着每个沟槽100t的侧壁的一部分延伸。即，电极焊盘122可以沿第二方向D2延伸。
焊料球400可以设置在沟槽100t中。即，焊料球400可以包括设置在再分布结构100中的部分和设置在再分布结构100外部的部分。第一再分布层125和焊料球400可以至少部分地被第一绝缘层110围绕。因此，能够提高焊锡球400与电极焊盘122之间的结合的可靠性。
图3是根据本发明构思的一些实施例的半导体封装件的截面图。为了方便起见，在下文中将主要集中于与图1的半导体封装件的区别来描述图3的半导体封装件。
参照图3，模制部件300可以覆盖半导体芯片200的侧面和再分布结构100的第一表面100a。模制部件300可以暴露半导体芯片200的顶表面。模制部件300的顶表面可以设置在与半导体芯片200的顶表面相同的平面上。
传热器(未示出)可以设置在例如模制部件300的顶表面和半导体芯片200的顶表面上。由于半导体芯片200和传热器可以彼此直接接触，因此由半导体芯片200产生的热可以容易地通过传热器释放。
图1或图3的半导体封装件可以安装在主板上。图1或图3的半导体封装件可以经由焊料球400电连接到主板。主板的示例可以包括智能电话、个人数字助理(PDA)、数字摄像机、数字照相机、网络系统、计算机、监视器、平板电脑、便携式计算机、上网本、电视(TV)、视频游戏机和智能手表。
图4至图16是示出根据本发明构思的一些实施例的制造半导体封装件的方法的截面图。在下文中将参照图4至图16描述根据本发明构思的一些实施例的制造半导体封装件的方法。
参照图4，可以在第一载体500上形成脱模层510。第一载体500可以包括例如硅、金属、玻璃、塑料或陶瓷。
脱模层510可以形成为具有预定厚度。例如，脱模层510可以是膜的形式，但是本发明构思不限于此。脱模层510可以通过沉积或涂覆形成。
脱模层510可以包括PID材料。脱模层510可以是例如基于辐射而起反应的正性类型。
例如，可以在第一载体500与脱模层510之间进一步形成粘附层(未示出)。粘附层可以包括例如基于聚合物的光热转换(LTHC)材料，该LTHC材料可以与第一载体500一起被去除。在一些实施例中，粘附层可以包括例如环氧类散热材料或紫外线(UV)粘合剂。
参照图5，可以在脱模层510上形成第一阻挡层512。第一阻挡层512可以包括金属材料。第一阻挡层512可以包括例如Ti。
第一阻挡层512可以通过例如物理气相沉积(PVD)、溅射或化学气相沉积(CVD)形成，但是本发明构思不限于此。
参照图6，可以在第一阻挡层512上形成牺牲层514。牺牲层514可以暴露第一阻挡层512的一部分。例如，牺牲层514可以包括开口515。
可以在第一阻挡层512上形成掩模图案(未示出)。可以在开口515上方形成掩模图案。可以通过应用和图案化光刻胶来形成掩模图案。
牺牲层514可以形成在第一阻挡层512的暴露部分上。牺牲层514可以通过例如PVD、溅射或CVD形成。在一些实施例中，牺牲层514可以通过例如电镀形成。一旦形成牺牲层514，就可以去除掩模图案。开口515可以由第一阻挡层512的被掩模图案暴露的部分的顶表面限定。
牺牲层514可以包括与第一阻挡层512不同的金属材料。牺牲层514可以包括例如Cu。
参照图7，可以在开口515中和牺牲层514上共形地形成第二阻挡层516。第二阻挡层516可以覆盖牺牲层514的顶表面和侧面。第二阻挡层516可以覆盖第一阻挡层512的暴露部分的顶表面。在一些实施例中，第二阻挡层516可以沿着第一阻挡层512和牺牲层514的表面具有均匀的厚度，如图7所示。
第二阻挡层516可以包括与牺牲层514不同的金属材料。第二阻挡层516可以包括例如Ti、铬(Cr)、钨(W)、Al、钯(Pd)及它们的组合中的至少一种，但是本发明构思不限于此。
第二阻挡层516可以通过例如PVD、溅射或CVD形成，但是本发明构思不限于此。
参照图8，可以在第二阻挡层516上形成第一绝缘层110。第一绝缘层110可以暴露第二阻挡层516的一部分。例如，第一绝缘层110可以暴露第二阻挡层516的位于牺牲层514上的部分的顶表面516u。
第一绝缘层110可以比牺牲层514厚。即，第一绝缘层110的顶表面110u可以高于第二阻挡层516的位于牺牲层514上的部分的顶表面516u。在一些实施例中，第一绝缘层110的上部可以向上突出超过第二阻挡层516的该部分的顶表面516u，因此，第一绝缘层110的顶表面可以比第二阻挡层516的该部分的顶表面516u更远离第一阻挡层512，如图8所示。
第一绝缘层110可以包括与脱模层510相同的材料。第一绝缘层110可以包括例如PID材料。
第二阻挡层516的位于牺牲层514上的部分的顶表面516u可以通过例如光刻暴露。
参照图9，可以在第一绝缘层110上以及第二阻挡层516的位于牺牲层514上的部分的顶表面516u上形成第一再分布层125。
第一再分布层125可以包括与牺牲层514相同的材料。例如，第一再分布层125可以包括Cu。
参照图10，可以形成包括第一再分布层125的再分布结构100。例如，可以通过电镀形成多个通路(132和134)和多个再分布层(120、126和128)。例如，可以通过镶嵌工艺同时形成第一通路132和第二再分布层126。在一些实施例中，第一通路132和第二再分布层126可以通过相同的工艺(例如，镶嵌工艺)形成。
此后，可以将半导体芯片200安装在再分布结构100的第一表面100a上。可以在再分布层120上设置半导体芯片200的连接焊盘210和设置在连接焊盘210上的凸块230。
此后，可以形成模制部件300以覆盖半导体芯片200和再分布结构100的第一表面100a。
参照图11，可以将第二载体600附着在模制部件300上。第二载体600可以设置在面对第一载体500的表面上。例如，可以在第二载体600与模制部件300之间进一步形成粘附层(未示出)。粘附层可以包括例如可以与第二载体600一起被去除的LTHC材料。在一些实施例中，粘附层可以包括例如环氧类散热材料或紫外线粘合剂。
第二载体600可以包括例如硅、金属、玻璃、塑料或陶瓷。在一些实施例中，第二载体600可以包括与第一载体500相同的材料。
此后，可以将相应的半导体封装件颠倒。之后，可以从半导体封装件中去除第一载体500。结果，可以暴露脱模层510。
参照图12，可以去除脱模层510。
可以用光或激光辐射脱模层510。可以通过模制显影工艺去除脱模层510的暴露于光的部分。
参照图13，可以去除第一阻挡层512。可以通过例如湿蚀刻来去除第一阻挡层512。在一些实施例中，可以通过例如干蚀刻来去除第一阻挡层512。
参照图14，可以去除牺牲层514。可以通过例如湿蚀刻来去除牺牲层514。在一些实施例中，可以通过例如干蚀刻来去除牺牲层514。
参照图15，可以去除第二阻挡层516。结果，可以至少部分地暴露第一再分布层125。可以暴露第一再分布层125的电极焊盘122。即，可以形成由第一绝缘层110和电极焊盘122限定的沟槽100t。可以通过去除第一阻挡层512、第二阻挡层516和牺牲层514来形成沟槽100t。
可以通过例如湿蚀刻来去除第二阻挡层516。在一些实施例中，可以通过例如干蚀刻来去除第二阻挡层516。
参照图16，可以在沟槽100t中形成焊料球400。焊料球400可以包括设置在再分布结构100内部的部分和设置在再分布结构100外部的部分。第一再分布层125和焊料球400可以至少部分地被第一绝缘层110围绕。因此，可以改善焊料球400与电极焊盘122之间的结合的可靠性。
焊料球400可以形成在第二阻挡层516的暴露部分上。因此，焊料球400可以电连接到再分布层(120、125、126和128)。
图17和图18是示出根据本发明构思的一些实施例的制造半导体封装件的方法的截面图。图17的半导体封装件是通过与图4至图10所示的工艺相同或相似的工艺形成的半导体封装件。下面将参照图17和图18描述根据本发明构思的一些实施例的制造半导体封装件的方法。
参照图17，可以通过平坦化工艺来部分地蚀刻模制部件300。模制部件300可以暴露半导体芯片200的顶表面。即，模制部件300的顶表面可以设置在与半导体芯片200的顶表面相同的平面上。
此后，参照图18，可以将第二载体600附着在半导体芯片200上和模制部件300上。第二载体600可以设置在面对第一载体500的表面上。例如，可以在第二载体600、半导体芯片200和模制部件300之间进一步形成粘附层(未示出)。
此后，将相应的半导体封装件颠倒。可以从半导体封装件中去除第一载体500。结果，可以暴露脱模层510。
此后，进行与图13至图16所示的工艺相同或相似的工艺，从而获得图3的半导体封装件。
在结束详细描述时，本领域技术人员将理解，在不脱离本发明构思的原理的情况下，可以对本文描述的示例实施例进行许多变化和修改。因此，本发明构思的示例实施例仅在一般的和描述性的意义上使用，而不是出于限制的目的。

Claims (20)

1.一种制造半导体封装件的方法，所述方法包括：
在第一载体上形成第一阻挡层；
在所述第一阻挡层上形成牺牲层，所述牺牲层包括暴露所述第一阻挡层的至少一部分的开口；
在所述第一阻挡层上和所述牺牲层上形成第二阻挡层，所述第二阻挡层包括形成在所述牺牲层上的部分；
在所述开口中形成第一绝缘层，所述第一绝缘层突出超过所述第二阻挡层的所述部分的顶表面，所述第一绝缘层的顶表面比所述第二阻挡层的所述部分的所述顶表面更远离所述第一阻挡层；
在所述第一绝缘层上和所述第二阻挡层上形成包括再分布层和第二绝缘层的再分布结构；
在所述再分布结构上安装半导体芯片；
将第二载体附着到所述半导体芯片上并去除所述第一载体；
去除所述第一阻挡层、所述牺牲层和所述第二阻挡层以暴露所述再分布结构的部分；以及
分别在所述再分布结构的所述部分上形成焊料球。
2.根据权利要求1所述的方法，其中，所述牺牲层和所述再分布层包括相同的材料。
3.根据权利要求1所述的方法，其中，所述牺牲层包括金属材料。
4.根据权利要求3所述的方法，其中，所述金属材料包括铜。
5.根据权利要求1所述的方法，其中，所述第一阻挡层和所述第二阻挡层包括与所述牺牲层不同的材料。
6.根据权利要求1所述的方法，其中，去除所述第一阻挡层、所述牺牲层和所述第二阻挡层包括执行湿蚀刻工艺。
7.根据权利要求1所述的方法，其中，所述第二绝缘层在所述再分布层的侧面上延伸，并且
其中，所述第一绝缘层和所述第二绝缘层包括光可成像电介质材料。
8.根据权利要求1所述的方法，其中，去除所述第一阻挡层、所述牺牲层和所述第二阻挡层包括在所述第一绝缘层中形成沟槽。
9.根据权利要求8所述的方法，其中，形成所述焊料球包括分别在所述沟槽中形成所述焊料球。
10.根据权利要求9所述的方法，其中，所述沟槽分别暴露所述再分布层的部分，并且所述焊料球分别接触所述再分布层的所述部分。
11.一种制造半导体封装件的方法，所述方法包括：
在第一载体上顺序地形成脱模层和第一阻挡层；
在所述第一阻挡层上形成牺牲层，所述牺牲层包括金属材料和暴露所述第一阻挡层的至少一部分的开口；
形成在所述第一阻挡层上和所述牺牲层上延伸的第二阻挡层；
在所述开口中形成比所述牺牲层厚的第一绝缘层；
在所述第一绝缘层上和所述第二阻挡层上形成包括再分布层和第二绝缘层的再分布结构；
在所述再分布结构上安装半导体芯片；
将第二载体附着到所述半导体芯片上，并去除所述第一载体和所述脱模层；
去除所述第一阻挡层、所述牺牲层和所述第二阻挡层以暴露所述再分布层的部分；以及
分别在所述再分布层的所述部分上形成焊料球。
12.根据权利要求11所述的方法，其中，所述金属材料包括铜。
13.根据权利要求11所述的方法，其中，所述第一绝缘层包括面对所述第一阻挡层的第一底表面和与所述第一底表面相对的第一顶表面，并且所述第二阻挡层包括面对所述第一阻挡层的第二底表面和与所述第二底面相对的第二顶表面，以及
所述第一绝缘层的所述第一顶表面比所述第二阻挡层的所述第二顶表面更远离所述第一阻挡层。
14.根据权利要求11所述的方法，其中，所述第一阻挡层和所述第二阻挡层包括与所述牺牲层不同的材料。
15.根据权利要求11所述的方法，其中，去除所述第一阻挡层、所述牺牲层和所述第二阻挡层包括通过执行蚀刻工艺顺序地去除所述第一阻挡层、所述牺牲层和所述第二阻挡层。
16.根据权利要求11所述的方法，其中，所述脱模层包括与所述第一绝缘层相同的材料。
17.一种制造半导体封装件的方法，所述方法包括：
在第一载体上顺序地形成脱模层和第一阻挡层；
在所述第一阻挡层上形成牺牲层，所述牺牲层包括暴露所述第一阻挡层的至少一部分的开口；
在所述第一阻挡层上和所述牺牲层上共形地形成第二阻挡层；
在所述开口中形成第一绝缘层，所述第一绝缘层的顶表面比所述第二阻挡层的形成在所述牺牲层上的部分的顶表面更远离所述第一阻挡层；
在所述第一绝缘层上和所述第二阻挡层上形成再分布结构，所述再分布结构包括再分布层和堆叠在所述再分布层上以围绕所述再分布层的第二绝缘层；
在所述再分布结构上安装半导体芯片；
将第二载体附着到所述半导体芯片上并去除所述第一载体；
去除所述脱模层；
顺序地去除所述第一阻挡层、所述牺牲层和所述第二阻挡层；以及
在已经去除了所述牺牲层的空间中形成焊料球，所述焊料球电连接到所述再分布层。
18.根据权利要求17所述的方法，所述方法还包括：
形成覆盖所述半导体芯片的至少一部分和所述再分布结构的至少一部分的模制部件。
19.根据权利要求18所述的方法，其中，所述模制部件的顶表面与所述半导体芯片的顶表面共面。
20.根据权利要求17所述的方法，其中，顺序地去除所述第一阻挡层、所述牺牲层和所述第二阻挡层包括执行湿蚀刻工艺。
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