CN114388471A - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

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Publication number
CN114388471A
CN114388471A CN202110496136.6A CN202110496136A CN114388471A CN 114388471 A CN114388471 A CN 114388471A CN 202110496136 A CN202110496136 A CN 202110496136A CN 114388471 A CN114388471 A CN 114388471A
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China
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pads
bridge
layer
reconfiguration
electrically connected
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刘汉诚
柯正达
林溥如
曾子章
谭瑞敏
杨凯铭
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Unimicron Technology Corp
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Unimicron Technology Corp
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Publication of CN114388471A publication Critical patent/CN114388471A/zh
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Abstract

本发明提供一种封装结构及其制作方法。封装结构包括桥接件、中介基材、第一重配置结构层、第二重配置结构层及多个芯片。桥接件包括硅基底、重配置线路层及多个桥接垫。中介基材包括中介层、多个导电通孔、多个第一接垫及多个第二接垫。桥接件内埋于中介层内，且桥接垫切齐于上表面。第一重配置结构层配置于中介基材的上表面上且与第一接垫及桥接件的桥接垫电性连接。第二重配置结构层配置于中介基材的下表面上且与第二接垫电性连接。芯片配置于第一重配置结构层上且与第一重配置结构层电性连接。芯片通过桥接件而彼此电性连接。本发明的封装结构，具有较佳的结构可靠度，尤其适用于覆晶芯片接合的平坦表面。

Description

封装结构及其制作方法
技术领域
本发明涉及一种半导体结构及其制作方法，尤其涉及一种封装结构及其制作方法。
背景技术
异质芯片整合(heterogeneous chiplet integration)的关键在于两个芯片之间的电性连接。目前，英特尔(Intel’s)是通过嵌入式多芯片互连桥接(Embedded Multi-DieInterconnect Bridge，EMIB)的方式来连接两芯片，而达成局部(partial或local)高密度互联。然而，上述技术所遇到的问题是，桥接件必须通过层压技术嵌入有机基板中，因此表面需要足够平坦才能进行后续芯片的覆晶封装。
发明内容
本发明是针对一种封装结构，具有较佳的结构可靠度，尤其适用于覆晶芯片接合的平坦表面。
本发明还针对一种封装结构的制作方法，用以制作上述的封装结构。
根据本发明的实施例，封装结构包括桥接件、中介基材、第一重配置结构层、第二重配置结构层以及多个芯片。桥接件包括硅基底、重配置线路层以及多个桥接垫。重配置线路层配置于硅基底上。桥接垫配置于重配置线路层上且与重配置线路层电性连接。中介基材包括中介层、多个导电通孔、多个第一接垫以及多个第二接垫。中介层具有彼此相对的上表面与下表面。导电通孔贯穿中介层且分别连接至位于上表面上的第一接垫与位于下表面上的第二接垫。桥接件内埋于中介层内，且桥接垫切齐于上表面。第一重配置结构层配置于中介基材的上表面上，且与第一接垫及桥接件的桥接垫电性连接。第二重配置结构层配置于中介基材的下表面上，且与第二接垫电性连接。芯片配置于第一重配置结构层上，且与第一重配置结构层电性连接。芯片通过桥接件而彼此电性连接。
在根据本发明的实施例的封装结构中，上述的封装结构还包括多个芯片接垫，配置于第一重配置结构层上，且与第一重配置结构层电性连接。芯片通过芯片接垫与第一重配置结构层及桥接件电性连接。
在根据本发明的实施例的封装结构中，上述的封装结构还包括多个铜柱、多个焊料以及多个焊球。铜柱分别配置于芯片上。焊料分别配置于铜柱上，其中铜柱分别位于芯片与焊料之间。芯片通过铜柱、焊料与桥接件电性连接。焊球配置于芯片上，其中芯片通过焊球与第一重配置结构层电性连接。
在根据本发明的实施例的封装结构中，上述的封装结构还包括多个焊球接垫与多个焊球。焊球接垫配置于第二重配置结构层上，且与第二重配置结构层电性连接。焊球分别配置于焊球接垫上。
根据本发明的实施例，封装结构的制作方法，其包括以下步骤。提供桥接件。桥接件包括硅基底、重配置线路层以及多个桥接垫。重配置线路层配置于硅基底上，而桥接垫配置于重配置线路层上且与重配置线路层电性连接。内埋桥接件于中介基材内。中介基材包括中介层、多个导电通孔、多个第一接垫以及多个第二接垫。中介层具有彼此相对的上表面与下表面。导电通孔贯穿中介层且分别连接至位于上表面上的第一接垫与位于下表面上的第二接垫。桥接垫切齐于上表面。形成第一重配置结构层于中介基材的上表面上。第一重配置结构层与第一接垫及桥接件的桥接垫电性连接。形成第二重配置结构层于中介基材的下表面上。第二重配置结构层与第二接垫电性连接。配置多个芯片于第一重配置结构层上。芯片与第一重配置结构层电性连接，且芯片通过桥接件而彼此电性连接。
在根据本发明的实施例的封装结构的制作方法中，上述内埋桥接件于中介基材内的步骤，包括将桥接件配置于暂时基板上，其中桥接垫面对暂时基板。形成中介层于暂时基板上，其中中介层包覆桥接件。移除暂时基板，而暴露出中介层的上表面。形成贯穿中介层的多个通孔。形成导电通孔、第一接垫以及第二接垫于中介层上。导电通孔分别位于通孔内且连接第一接垫与第二接垫。
在根据本发明的实施例的封装结构的制作方法中，上述的封装结构的制作方法，还包括：于形成第一重配置结构层于中介基材的上表面上之后，形成多个芯片接垫于第一重配置结构层上且与第一重配置结构层电性连接。
在根据本发明的实施例的封装结构的制作方法中，上述配置芯片于第一重配置结构层上之前，还包括：形成多个铜柱分别于芯片上。形成多个焊料分别于铜柱上，其中铜柱位于芯片与焊料之间，且芯片通过铜柱与焊料与桥接件电性连接。形成多个焊球于芯片上，其中芯片通过焊球与第一重配置结构层电性连接。
在根据本发明的实施例的封装结构的制作方法中，上述的封装结构的制作方法，还包括：形成第二重配置结构层于中介基材的下表面上之后，形成多个焊球接垫于第二重配置结构层上且与第二重配置结构层电性连接。分别形成多个焊球于焊球接垫上。
在根据本发明的实施例的封装结构的制作方法中，上述的桥接件是由晶圆单体化切割而构成。
基于上述，在本发明的封装结构的设计中，具有重配置线路层及桥接垫的桥接件是内埋于中介基材内，且桥接垫切齐于中介层的上表面，因此后续形成在中介基材上的第一重配置结构层可具有较佳的平坦度。此外，后续将芯片以覆晶方式接合至第一重配置结构层上时，每一芯片除了可通过第一重配置结构层、中介基材及第二重配置线路层与外部电路电性连接之外，两芯片之间亦可通过桥接件而彼此电性连接，而达成局部(partial或local)高密度互联。简言之，本发明的封装结构可以以具有较佳成本效益的方式而具有较佳的结构可靠度(由于平坦度)及芯片与芯片之间的互连密度。
附图说明
图1A至图1J是依照本发明的一实施例的一种封装结构的制作方法的示意图。
附图标记说明
10:晶圆；
20:暂时基板；
22:离型膜；
100:封装结构；
110:桥接件；
112:硅基底；
114:重配置线路层；
116:桥接垫；
120:中介基材；
121:上表面；
122:中介层；
123:下表面；
124:导电通孔；
125:通孔；
126:第一接垫；
128:第二接垫；
130:铜柱；
135:焊料；
137:焊球；
140:第一重配置结构层；
150:第二重配置结构层；
160:芯片接垫；
165:焊球接垫；
170:焊球；
180:芯片。
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附图中。只要有可能，相同元件符号在附图和描述中用来表示相同或相似部分。
图1A至图1J是依照本发明的一实施例的一种封装结构的制作方法的示意图。为了方便说明起见，图1A以简易地俯视图来进行示出，而图1B至图1J则以剖面图来进行示出。
关于本实施例的封装结构的制作方法，首先，请同时参考图1A与图1B，提供桥接件110。桥接件110包括硅基底112、重配置线路层114以及多个桥接垫116。重配置线路层114配置于硅基底112上，而桥接垫116配置于重配置线路层114上且与重配置线路层114电性连接。此处，桥接件110具体化是由晶圆10单体化切割而构成，其中重配置线路层114是采用64纳米的制程技术来制作，而重配置线路层114的线路层数为2层至4层，且线路的最小间距(pitch)为0.4微米。较佳地，桥接件110尺寸为3毫米X 3毫米，意即尺寸非常小。
接着，请先参考图1H，内埋桥接件110于中介基材120内。中介基材120包括中介层122、多个导电通孔124、多个第一接垫126以及多个第二接垫128。中介层122具有彼此相对的上表面121与下表面123。导电通孔124贯穿中介层122且分别连接至位于上表面121上的第一接垫126与位于下表面123上的第二接垫128。特别是，桥接件110的桥接垫116实质上切齐于中介层122的上表面121。
详细来说，内埋桥接件110于中介基材120内的步骤，首先，请参考图1C，将桥接件110配置于暂时基板20上，其中桥接垫116面对暂时基板20。此处，暂时基板20上还有配置离型膜22，其中暂时基板20例如是圆形或矩形的玻璃基板或钢制(steel)基板，而桥接件110以面朝下(face-down)的方式通过离型膜22而定位于暂时基板20上。
接着，请参考图1D，形成中介层122于暂时基板20上，其中中介层122包覆桥接件110，且中介层122的材质例如是味之素堆积薄膜(Ajinomoto Build-up Film,ABF)或环氧模压树脂(Epoxy Molding Compound,EMC)，但不以此为限。
接着，请参考图1E，移除暂时基板20及离型膜22，而暴露出中介层122的上表面121。
接着，请参考图1F，通过雷射钻孔的方式，形成贯穿中介层122的多个通孔125，其中通孔125贯穿中介层122且连接上表面121与下表面123，而通孔125位于桥接件110的两侧。
接着，请参考图1G，翻转中介层122，而使中介层122的上表面121朝上。此时，桥接件110呈现面朝上(face-up)，且桥接件110的桥接垫116仍切齐中介层122的上表面121。
接着，请参考图1H，以电镀的方式，形成导电通孔124、第一接垫126以及第二接垫128于中介层122上，其中导电通孔124分别位于通孔125内，且导电通孔124彼此相对的两端分别连接第一接垫126与第二接垫128。
接着，请参考图1I，形成第一重配置结构层140于中介基材120的上表面121上，其中第一重配置结构层140与第一接垫126及桥接件110的桥接垫116电性连接。
接着，请再参考图1I，形成第二重配置结构层150于中介基材120的下表面123上，其中第二重配置结构层150与第二接垫128电性连接。
此处，并不限制第一重配置结构层140与第二重配置结构层150的形成顺序。举例来说，可先形成第一重配置结构层140，而后再形成第二重配置结构层150；或者是，可先形成第二重配置结构层150，而后再形成第一重配置结构层140；或者是，可同时形成第一重配置结构层140及第二重配置结构层150。
之后，请再参考图1I，形成多个芯片接垫160于第一重配置结构层140上且与第一重配置结构层140电性连接。紧接着，形成多个焊球接垫165于第二重配置结构层150上且与第二重配置结构层150电性连接。之后，分别形成多个焊球170于焊球接垫165上。此处，芯片接垫160与焊球接垫165的形成顺序并不加以限制。
最后，请再参考图1J，配置多个芯片180于第一重配置结构层140上，其中芯片180与第一重配置结构层140电性连接，且芯片180通过桥接件110而彼此电性连接。此处，芯片180可为不同型态类型的芯片，于此不加以限制。进一步来说，将芯片180配置于第一重配置结构层140之前，还包括形成多个铜柱130分别于芯片180上。接着，形成多个焊料135分别于铜柱130上，其中铜柱130位于芯片180与焊料135之间。紧接着，形成多个焊球137于芯片180上，其中芯片180通过焊球137与第一重配置结构层140电性连接，而芯片180通过铜柱130与焊料135与桥接件110电性连接。至此，已完成封装结构100的制作。
在结构上，请再参考图1J，封装结构100包括桥接件110、中介基材120、第一重配置结构层140、第二重配置结构层150以及芯片180。桥接件110包括硅基底112、重配置线路层114以及桥接垫116。重配置线路层114配置于硅基底112上。桥接垫116配置于重配置线路层114上且与重配置线路层114电性连接。中介基材120包括中介层122、导电通孔124、第一接垫126以及第二接垫128。中介层122具有彼此相对的上表面121与下表面123。导电通孔124贯穿中介层122且分别连接至位于上表面121上的第一接垫126与位于下表面123上的第二接垫128。桥接件110内埋于中介层120内，且桥接垫116切齐于上表面121。第一重配置结构层140配置于中介基材120的上表面121上，且与第一接垫126及桥接件110的桥接垫116电性连接。第二重配置结构层150配置于中介基材120的下表面123上，且与第二接垫128电性连接。芯片180配置于第一重配置结构层140上，且与第一重配置结构层140电性连接。芯片180通过桥接件110而彼此电性连接。
再者，在本实施例中，封装结构100还包括芯片接垫160、焊球接垫165以及焊球170。芯片接垫160配置于第一重配置结构层140上，且与第一重配置结构层140电性连接。芯片180可通过芯片接垫160与第一重配置结构层140及桥接件110电性连接。焊球接垫165配置于第二重配置结构层150上，且与第二重配置结构层150电性连接。焊球170分别配置于焊球接垫165上，其中封装结构100可通过焊球170与外部电路(如印刷电路板)电性连接。
此外，本实施例的封装结构100还包括铜柱130、焊料135以及焊球137。铜柱130分别配置于芯片180上。焊料135分别配置于铜柱130上，其中铜柱130分别位于芯片180与焊料135之间。芯片180通过铜柱130、焊料135与桥接件110电性连接。焊球137配置于芯片180上，其中芯片180通过焊球137与第一重配置结构层140电性连接。
简言之，本实施例是先将桥接件110以面朝下(face-down)的方式进行封装而内埋于中介基材120内。在对桥接件110进行封装成型后，无须采用研磨且也无须电镀铜柱，因此，本实施例的封装结构100具有制程简单且成本低的优势。再者，由于桥接件110的桥接垫116切齐于中介层122的上表面121，因此后续形成在中介基材120上的第一重配置结构层140可具有较佳的平坦度。此外，后续将芯片180以覆晶方式接合至第一重配置结构层140上时，每一芯片180除了可通过第一重配置结构层140、中介基材120及第二重配置线路层150与外部电路电性连接之外，两芯片180之间亦可通过桥接件110而彼此电性连接，而达成局部(partial或local)高密度互联。换言之，本实施例的封装结构100可以以具有较佳成本效益的方式而具有较佳的表面平坦度及芯片与芯片之间的互连密度。
综上所述，在本发明的封装结构的设计中，具有重配置线路层及桥接垫的桥接件是内埋于中介基材内，且桥接垫切齐于中介层的上表面，因此后续形成在中介基材上的第一重配置结构层可具有较佳的平坦度。此外，后续将芯片以覆晶方式接合至第一重配置结构层上时，每一芯片除了可通过第一重配置结构层、中介基材及第二重配置线路层与外部电路电性连接之外，两芯片之间亦可通过桥接件而彼此电性连接，而达成局部(partial或local)高密度互联。简言之，本发明的封装结构可以以具有较佳成本效益的方式而具有较佳的表面平坦度及芯片与芯片之间的互连密度。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (10)

1.一种封装结构，其特征在于，包括：
桥接件，包括硅基底、重配置线路层以及多个桥接垫，其中所述重配置线路层配置于所述硅基底上，而所述多个桥接垫配置于所述重配置线路层上且与所述重配置线路层电性连接；
中介基材，包括中介层、多个导电通孔、多个第一接垫以及多个第二接垫，所述中介层具有彼此相对的上表面与下表面，所述多个导电通孔贯穿所述中介层且分别连接至位于所述上表面上的所述多个第一接垫与位于所述下表面上的所述多个第二接垫，其中所述桥接件内埋于所述中介层内，且所述多个桥接垫切齐于所述上表面；
第一重配置结构层，配置于所述中介基材的所述上表面上，且与所述多个第一接垫及所述桥接件的所述多个桥接垫电性连接；
第二重配置结构层，配置于所述中介基材的所述下表面上，且与所述多个第二接垫电性连接；以及
多个芯片，配置于所述第一重配置结构层上，且与所述第一重配置结构层电性连接，其中所述多个芯片通过所述桥接件而彼此电性连接。
2.根据权利要求1所述的封装结构，其特征在于，还包括：
多个芯片接垫，配置于所述第一重配置结构层上，且与所述第一重配置结构层电性连接，其中所述多个芯片通过所述多个芯片接垫与所述第一重配置结构层及所述桥接件电性连接。
3.根据权利要求1所述的封装结构，其特征在于，还包括：
多个铜柱，分别配置于所述多个芯片上；
多个焊料，分别配置于所述多个铜柱上，其中所述多个铜柱分别位于所述多个芯片与所述多个焊料之间，且所述多个芯片通过所述多个铜柱、所述多个焊料与所述桥接件电性连接；以及
多个焊球，配置于所述多个芯片上，其中所述多个芯片通过所述多个焊球与所述第一重配置结构层电性连接。
4.根据权利要求1所述的封装结构，其特征在于，还包括：
多个焊球接垫，配置于所述第二重配置结构层上，且与所述第二重配置结构层电性连接；以及
多个焊球，分别配置于所述多个焊球接垫上。
5.一种封装结构的制作方法，其特征在于，包括：
提供桥接件，所述桥接件包括硅基底、重配置线路层以及多个桥接垫，其中所述重配置线路层配置于所述硅基底上，而所述多个桥接垫配置于所述重配置线路层上且与所述重配置线路层电性连接；
内埋所述桥接件于中介基材内，所述中介基材包括中介层、多个导电通孔、多个第一接垫以及多个第二接垫，所述中介层具有彼此相对的上表面与下表面，所述多个导电通孔贯穿所述中介层且分别连接至位于所述上表面上的所述多个第一接垫与位于所述下表面上的所述多个第二接垫，所述多个桥接垫切齐于所述上表面；
形成第一重配置结构层于所述中介基材的所述上表面上，其中所述第一重配置结构层与所述多个第一接垫及所述桥接件的所述多个桥接垫电性连接；
形成第二重配置结构层于所述中介基材的所述下表面上，其中所述第二重配置结构层与所述多个第二接垫电性连接；以及
配置多个芯片于所述第一重配置结构层上，其中所述多个芯片与所述第一重配置结构层电性连接，且所述多个芯片通过所述桥接件而彼此电性连接。
6.根据权利要求5所述的封装结构的制作方法，其特征在于，其中内埋所述桥接件于所述中介基材内的步骤，包括：
将所述桥接件配置于暂时基板上，其中所述多个桥接垫面对所述暂时基板；
形成所述中介层于所述暂时基板上，其中所述中介层包覆所述桥接件；
移除所述暂时基板，而暴露出所述中介层的所述上表面；
形成贯穿所述中介层的多个通孔；以及
形成所述多个导电通孔、所述多个第一接垫以及所述多个第二接垫于所述中介层上，其中所述多个导电通孔分别位于所述多个通孔内且连接所述多个第一接垫与所述多个第二接垫。
7.根据权利要求5所述的封装结构的制作方法，其特征在于，还包括：
于形成所述第一重配置结构层于所述中介基材的所述上表面上之后，形成多个芯片接垫于所述第一重配置结构层上且与所述第一重配置结构层电性连接。
8.根据权利要求5所述的封装结构的制作方法，其特征在于，其中配置所述多个芯片于所述第一重配置结构层上之前，还包括：
形成多个铜柱分别于所述多个芯片上；
形成多个焊料分别于所述多个铜柱上，其中所述多个铜柱位于所述多个芯片与所述多个焊料之间，所述多个芯片通过所述多个铜柱与所述多个焊料与所述桥接件电性连接；以及
形成多个焊球于所述多个芯片上，其中所述多个芯片通过所述多个焊球与所述第一重配置结构层电性连接。
9.根据权利要求5所述的封装结构的制作方法，其特征在于，还包括：
形成所述第二重配置结构层于所述中介基材的所述下表面上之后，形成多个焊球接垫于所述第二重配置结构层上且与所述第二重配置结构层电性连接；以及
分别形成多个焊球于所述多个焊球接垫上。
10.根据权利要求5所述的封装结构的制作方法，其特征在于，其中所述桥接件是由晶圆单体化切割而构成。
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