CN116314102A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN116314102A
CN116314102A CN202111623673.9A CN202111623673A CN116314102A CN 116314102 A CN116314102 A CN 116314102A CN 202111623673 A CN202111623673 A CN 202111623673A CN 116314102 A CN116314102 A CN 116314102A
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China
Prior art keywords
layer
conductive elements
package
packaging
wiring structure
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Pending
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CN202111623673.9A
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English (en)
Inventor
柯仲禹
黄柏凯
陈亮斌
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN116314102A publication Critical patent/CN116314102A/zh
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Abstract

本发明涉及一种电子封装件及其制法，包括将包含线路结构、电子元件、多个第一导电元件及第一封装层的第一封装模块以及包含布线结构、多个第二导电元件及第二封装层的第二封装模块相堆叠，以令该第二封装层设于该第一封装层上，使该布线结构叠合于该线路结构上，且各该第二导电元件对应结合各该第一导电元件，以经由将该线路结构与该布线结构同时分开制作，以缩短制程时间，且能分别控制该线路结构与该布线结构上的应力分布。

Description

电子封装件及其制法
技术领域
本发明有关一种半导体装置，尤指一种可减少应力的电子封装件及其制法。
背景技术
为了确保电子产品和通信设备的持续小型化和多功能性，半导体封装需朝尺寸微小化发展，以利于多引脚的连接，并具备高功能性。例如，于先进制程封装中，常用的封装型式如2.5D封装制程、扇出(Fan-Out)布线配合封装体堆叠(Package on Package)元件的制程(简称FO-POP)等，其中，FO-POP相对于2.5D封装制程具有低成本及材料供应商多等优势。
图1A至图1B现有FO-POP的半导体封装件1的制法的剖面示意图。
如图1A所示，于一具有扇出(Fan-Out)型线路重布层(redistribution layer，简称RDL)100的线路结构10上设置至少一半导体芯片11及多个导电柱13。
如图1B所示，形成一包覆层15于该线路结构10上，以令该包覆层15包覆该半导体芯片11与该些导电柱13，使该半导体芯片11埋设于该包覆层15中。接着，经由扇出(Fan-Out)规格的RDL制程形成一布线结构12于该包覆层15上，且令该布线结构12的线路重布层120电性连接该些导电柱13，使该半导体芯片11经由该线路结构10的线路重布层100与该导电柱13电性连接该布线结构12的线路重布层120。
然而，前述半导体封装件1中，由于进行扇出制程所需时间较长，故先后制作该线路结构10与该布线结构12将加长制作时间，导致制作成本增加。
此外，若该半导体封装件1需配置多层线路重布层100,120时，于该线路结构10上制作该布线结构12，容易发生应力分布不均的情况，导致部分线路重布层100,120因无法承受应力集中而断裂。
因此，如何克服上述现有技术的问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件，包括：线路结构；电子元件，其设于该线路结构上并电性连接该线路结构；多个第一导电元件，其设于该线路结构上并电性连接该线路结构；第一封装层，其设于该线路结构上以包覆该电子元件及该多个第一导电元件；以及封装模块，其结合于该第一封装层上，其中，该封装模块包含布线结构、设于该布线结构上并电性连接该布线结构的多个第二导电元件及一设于该布线结构上以包覆该多个第二导电元件的第二封装层，以令该封装模块以其第二封装层设于该第一封装层上，使该布线结构叠合于该线路结构上，且各该第二导电元件对应结合各该第一导电元件，使该多个第二导电元件电性连接该多个第一导电元件。
本发明亦提供一种电子封装件的制法，包括：于一线路结构上配置电子元件及多个第一导电元件，且该线路结构电性连接该电子元件及该多个第一导电元件；形成第一封装层于该线路结构上，以令该第一封装层包覆该电子元件及该多个第一导电元件，以形成第一封装模块；提供一该第二封装模块，其包含布线结构、设于该布线结构上的多个第二导电元件及一设于该布线结构上以包覆该多个第二导电元件的第二封装层；以及将该第二封装模块以其第二封装层设于该第一封装模块的第一封装层上，使该布线结构叠合于该线路结构上，且各该第二导电元件对应结合各该第一导电元件，以令该多个第二导电元件电性连接该多个第一导电元件。
前述的电子封装件及其制法中，该第一封装层的热膨胀系数不同于该第二封装层的热膨胀系数。
前述的电子封装件及其制法中，该第一封装层上形成有结合层，以令该第二封装层通过该结合层设于该第一封装层上。例如，该结合层包覆该多个第一导电元件及该多个第二导电元件之间的对接处。
前述的电子封装件及其制法中，该多个第一导电元件与该多个第二导电元件的端部分别外露出该第一封装层及该第二封装层。
由上可知，本发明的电子封装件及其制法中，主要经由将该线路结构与该布线结构同时分开制作，以缩短制程时间，故相比于现有技术，本发明的制法能有效降低制作成本。
再者，本发明由于该线路结构与该布线结构分开制作，使该布线结构并非于该线路结构上制作，故相比于现有技术，若该电子封装件需配置多层线路重布层时，可分别控制该线路结构与该布线结构上的应力分布，因而能有效减少应力，以避免该线路层与该布线层因无法承受应力集中而断裂的问题。
附图说明
图1A至图1B为现有半导体封装件的制法的剖视示意图。
图2A至图2E为本发明的电子封装件的制法的剖视示意图。
附图标记说明
1:半导体封装件
10,20:线路结构
100,120:线路重布层
11:半导体芯片
12,22:布线结构
13:导电柱
15:包覆层
2:电子封装件
2a:第一封装模块
2b:第二封装模块
20a:第一侧
20b:第二侧
200:介电层
201:线路层
21:电子元件
21a:作用面
21b:非作用面
210:电极垫
211:导电凸块
212:底胶
220:绝缘层
221:布线层
23:第一导电元件
230:凸出部
24:结合层
25:第一封装层
25a:表面
26:第二导电元件
26b:端部
27:第二封装层
9:承载件
90:离型层。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”、“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2E为本发明的电子封装件2的制法的剖面示意图。
如图2A所示，于一承载件9上形成一线路结构20，该线路结构20具有相对的第一侧20a与第二侧20b，以令该线路结构20以其第二侧20b结合该承载件9。
于本实施例中，该线路结构20如具有核心层与线路层的封装基板(substrate)或无核心层(coreless)的基板结构，其包含至少一介电层200及结合该介电层200的线路层201。例如，以线路重布层(redistribution layer，简称RDL)的制作方式形成无核心层(coreless)基板结构，其中，形成该线路层201的材料为铜，且形成该介电层200的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。应可理解地，该线路结构20亦可为其它可供承载如芯片等电子元件的载板，如硅中介板(interposer)，并不限于上述。
再者，该承载件9例如为半导体材料(如硅或玻璃)的板体，其上形成有一离型层90，使该线路结构20结合于该离型层90上。
如图2B所示，设置至少一电子元件21于该线路结构20的第一侧20a上，且形成多个第一导电元件23于该线路结构20的第一侧20a的线路层201上。
于本实施例中，该电子元件21为主动元件、被动元件或其二者组合，其中，该主动元件为例如半导体芯片，且该被动元件为例如电阻、电容或电感。例如，该电子元件21为半导体芯片，其具有相对的作用面21a与非作用面21b，且该作用面21a具有多个电极垫210，使该电子元件21以其电极垫210经由覆晶方式(通过如图所示的多个导电凸块211)电性连接该线路层201，再以底胶212包覆该些导电凸块211；或者，该电子元件21亦可经由多个焊线(图略)以打线方式电性连接该线路层201；亦或，该电子元件21可直接接触该线路层201。然而，有关该电子元件21电性连接线路层201的方式不限于上述。
再者，该第一导电元件23为如焊锡球的块体，其以如植球(ball placement)制程将该多个第一导电元件23结合(如熔接)于该线路层201上，使该多个第一导电元件23电性连接该线路层201。
如图2C所示，形成一第一封装层25于该线路结构20的第一侧20a上，以令该第一封装层25包覆该电子元件21与该多个第一导电元件23。接着，形成一结合层24于该第一封装层25上，以于该承载件9上形成一第一封装模块2a。
于本实施例中，该第一封装层25为绝缘材，如聚酰亚胺PI)、干膜(dry film)、环氧树脂(epoxy)环氧树脂的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该线路结构20的第一侧20a上。
再者，可经由整平制程，如蚀刻方式，移除该第一封装层25的部分材料，以令该第一封装层25的上侧的表面25a齐平该电子元件21的非作用面21b，并使该些第一导电元件23凸出及外露于该第一封装层25的表面25a，而形成有凸出部230，故该结合层24接触覆盖该电子元件21的非作用面21b且包覆该些第一导电元件23的凸出部230。
另外，该结合层24为粘着材，如胶膜，其不同于该第一封装层25的材料。
如图2D所示，于进行图2A至图2C所示的制程时，同步进行其它制程，即于一布线结构22上形成多个第二导电元件26，再于该布线结构22上形成一第二封装层27，以包覆该些第二导电元件26，并使该多个第二导电元件26的端部26b外露出该第二封装层27，以形成一第二封装模块2b。
于本实施例中，该布线结构22如具有核心层与线路层的封装基板(substrate)或无核心层(coreless)的基板结构，其包含至少一绝缘层220及结合该绝缘层220的布线层221。例如，以线路重布层(redistribution layer，简称RDL)的制作方式形成无核心层(coreless)基板结构，其中，形成该布线层221的材料为铜，且形成该绝缘层220的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)等的介电材。应可理解地，该布线结构22亦可为其它可供承载如芯片等电子元件的载板，如硅中介板(interposer)，并不限于上述。
再者，该第二导电元件26电性连接该布线结构22，且该第二导电元件26为如铜柱的金属柱或其它材料的柱体。
另外，该第二封装层27为绝缘材，如聚酰亚胺(polyimide，简称PI)、干膜(dryfilm)、如环氧树脂(epoxy)的封装胶体或封装材(molding compound)，其可用压合(lamination)或模压(molding)的方式形成于该布线结构22上。应可理解地，形成该第二封装层27的材料可相同或相异于该第一封装层25的材料，例如，该第一封装层25的热膨胀系数(Coefficient of thermal expansion，简称CTE)与第二封装层27的热膨胀系数不相同。
如图2E所示，将该第二封装模块2b以其第二封装层27结合至该第一封装模块2a的结合层24上，使该布线结构22叠合于该线路结构20上，且各该第二导电元件26对应结合各该第一导电元件23，使该多个第二导电元件26电性连接该多个第一导电元件23。之后，移除该承载件9与离型层90，以外露出该线路结构20的第二侧20b，进而制得电子封装件2。
于本实施例中，该多个第二导电元件26可插入该结合层24中以接触该多个第一导电元件23，以令该结合层24包覆该多个第一导电元件23及该多个第二导电元件26之间的对接处。
另外，于后续制程中，可于该线路结构20的第二侧20b进行植球制程以形成多个焊球(图略)，供接置一电路板(图略)。
因此，本发明的制法，主要经由将该线路结构20与该布线结构22同时分开制作，以缩短制程时间，故相比于现有技术，本发明的制法能有效降低制作成本。
再者，由于该线路结构20与该布线结构22分开制作，使该布线结构22并非于该线路结构20上制作，故若该电子封装件2需配置多层线路重布层时，可分别控制该线路结构20与该布线结构22上的应力分布，因而能有效减少应力，以避免该线路层201与该布线层221因无法承受应力集中而断裂的问题。
另一方面，亦可经由该第一封装层25的热膨胀系数不同于该第二封装层27的热膨胀系数，以分散应力，故当该第二封装层27结合至该结合层24上后，能有效分散该布线结构22与该线路结构20的应力，以减少应力，因而能避免该线路层201与该布线层221因无法承受应力集中而断裂的问题。
本发明亦提供一种电子封装件2，包括：一线路结构20、至少一电子元件21、多个第一导电元件23、一第一封装层25以及一第二封装模块2b。
所述的电子元件21设于该线路结构20上并电性连接该线路结构20。
所述的多个第一导电元件23设于该线路结构20上并电性连接该线路结构20。
所述的第一封装层25设于该线路结构20上以包覆该电子元件21及该多个第一导电元件23。
所述的第二封装模块2b结合于该第一封装层25上，其中，该第二封装模块2b包含一布线结构22、设于该布线结构22上并电性连接该布线结构22的多个第二导电元件26、及一设于该布线结构22上以包覆该多个第二导电元件26的第二封装层27，以令该第二封装模块2b以其第二封装层27设于该第一封装层27上，使该布线结构22叠合于该线路结构20上，且各该第二导电元件26对应结合各该第一导电元件23，使该第二导电元件26电性连接该第一导电元件23。
于一实施例中，该第一封装层25的热膨胀系数不同于该第二封装层27的热膨胀系数。
于一实施例中，该第一封装层25上形成有一结合层24，以令该第二封装层27结合该结合层24。例如，该结合层24包覆该第一导电元件23及第二导电元件26之间的对接处。
于一实施例中，该第一与第二导电元件23,26的至少一者为焊锡球或金属柱。
综上所述，本发明的电子封装件及其制法，经由将该线路结构与该布线结构同时分开制作，以缩短制程时间，且能分别控制该线路结构与该布线结构上的应力分布，故本发明不仅能降低制作成本，且能避免线路断裂的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (10)

1.一种电子封装件，包括：
线路结构；
电子元件，其设于该线路结构上并电性连接该线路结构；
多个第一导电元件，其设于该线路结构上并电性连接该线路结构；
第一封装层，其设于该线路结构上以包覆该电子元件及该多个第一导电元件；以及
封装模块，其结合于该第一封装层上，其中，该封装模块包含布线结构、设于该布线结构上并电性连接该布线结构的多个第二导电元件及一设于该布线结构上以包覆该多个第二导电元件的第二封装层，以令该封装模块以其第二封装层设于该第一封装层上，使该布线结构叠合于该线路结构上，且各该第二导电元件对应结合并电性连接各该第一导电元件。
2.如权利要求1所述的电子封装件，其中，该第一封装层的热膨胀系数不同于该第二封装层的热膨胀系数。
3.如权利要求1所述的电子封装件，其中，该第一封装层上形成有结合层，以令该第二封装层通过该结合层设于该第一封装层上。
4.如权利要求3所述的电子封装件，其中，该结合层包覆该多个第一导电元件及该多个第二导电元件之间的对接处。
5.如权利要求1所述的电子封装件，其中，该多个第一导电元件与该多个第二导电元件的端部分别外露出该第一封装层及该第二封装层。
6.一种电子封装件的制法，包括：
于一线路结构上配置电子元件及多个第一导电元件，且该线路结构电性连接该电子元件及该多个第一导电元件；
形成第一封装层于该线路结构上，以令该第一封装层包覆该电子元件及该多个第一导电元件，以形成第一封装模块；
提供一该第二封装模块，其包含布线结构、设于该布线结构上的多个第二导电元件及一设于该布线结构上以包覆该多个第二导电元件的第二封装层；以及
将该第二封装模块以其第二封装层设于该第一封装模块的第一封装层上，使该布线结构叠合于该线路结构上，且各该第二导电元件对应结合并电性连接各该第一导电元件。
7.如权利要求6所述的电子封装件的制法，其中，该第一封装层的热膨胀系数不同于该第二封装层的热膨胀系数。
8.如权利要求6所述的电子封装件的制法，其中，该第一封装层上形成有结合层，以令该第二封装层通过该结合层设于该第一封装层上。
9.如权利要求8所述的电子封装件的制法，其中，该结合层包覆该多个第一导电元件及该多个第二导电元件之间的对接处。
10.如权利要求6所述的电子封装件的制法，其中，该多个第一导电元件与该多个第二导电元件的端部分别外露出该第一封装层及该第二封装层。
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